usb/chipidea/ci_hdrc_tegra.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2016, NVIDIA Corporation
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/of_device.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/reset.h>
0012
0013 #include <linux/usb.h>
0014 #include <linux/usb/chipidea.h>
0015 #include <linux/usb/hcd.h>
0016 #include <linux/usb/of.h>
0017 #include <linux/usb/phy.h>
0018
0019 #include <soc/tegra/common.h>
0020
0021 #include "../host/ehci.h"
0022
0023 #include "ci.h"
0024
0025 struct tegra_usb {
0026     struct ci_hdrc_platform_data data;
0027     struct platform_device *dev;
0028
0029     const struct tegra_usb_soc_info *soc;
0030     struct usb_phy *phy;
0031     struct clk *clk;
0032
0033     bool needs_double_reset;
0034 };
0035
0036 struct tegra_usb_soc_info {
0037     unsigned long flags;
0038     unsigned int txfifothresh;
0039     enum usb_dr_mode dr_mode;
0040 };
0041
0042 static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
0043     .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
0044          CI_HDRC_OVERRIDE_PHY_CONTROL |
0045          CI_HDRC_SUPPORTS_RUNTIME_PM,
0046     .dr_mode = USB_DR_MODE_HOST,
0047     .txfifothresh = 10,
0048 };
0049
0050 static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
0051     .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
0052          CI_HDRC_OVERRIDE_PHY_CONTROL |
0053          CI_HDRC_SUPPORTS_RUNTIME_PM,
0054     .dr_mode = USB_DR_MODE_HOST,
0055     .txfifothresh = 16,
0056 };
0057
0058 static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
0059     .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
0060          CI_HDRC_OVERRIDE_PHY_CONTROL |
0061          CI_HDRC_SUPPORTS_RUNTIME_PM,
0062     .dr_mode = USB_DR_MODE_UNKNOWN,
0063     .txfifothresh = 10,
0064 };
0065
0066 static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
0067     .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
0068          CI_HDRC_OVERRIDE_PHY_CONTROL |
0069          CI_HDRC_SUPPORTS_RUNTIME_PM,
0070     .dr_mode = USB_DR_MODE_UNKNOWN,
0071     .txfifothresh = 16,
0072 };
0073
0074 static const struct of_device_id tegra_usb_of_match[] = {
0075     {
0076         .compatible = "nvidia,tegra20-ehci",
0077         .data = &tegra20_ehci_soc_info,
0078     }, {
0079         .compatible = "nvidia,tegra30-ehci",
0080         .data = &tegra30_ehci_soc_info,
0081     }, {
0082         .compatible = "nvidia,tegra20-udc",
0083         .data = &tegra20_udc_soc_info,
0084     }, {
0085         .compatible = "nvidia,tegra30-udc",
0086         .data = &tegra30_udc_soc_info,
0087     }, {
0088         .compatible = "nvidia,tegra114-udc",
0089         .data = &tegra30_udc_soc_info,
0090     }, {
0091         .compatible = "nvidia,tegra124-udc",
0092         .data = &tegra30_udc_soc_info,
0093     }, {
0094         /* sentinel */
0095     }
0096 };
0097 MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
0098
0099 static int tegra_usb_reset_controller(struct device *dev)
0100 {
0101     struct reset_control *rst, *rst_utmi;
0102     struct device_node *phy_np;
0103     int err;
0104
0105     rst = devm_reset_control_get_shared(dev, "usb");
0106     if (IS_ERR(rst)) {
0107         dev_err(dev, "can't get ehci reset: %pe\n", rst);
0108         return PTR_ERR(rst);
0109     }
0110
0111     phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
0112     if (!phy_np)
0113         return -ENOENT;
0114
0115     /*
0116      * The 1st USB controller contains some UTMI pad registers that are
0117      * global for all the controllers on the chip. Those registers are
0118      * also cleared when reset is asserted to the 1st controller.
0119      */
0120     rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
0121     if (IS_ERR(rst_utmi)) {
0122         dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
0123         dev_warn(dev, "continuing, but please update your DT\n");
0124     } else {
0125         /*
0126          * PHY driver performs UTMI-pads reset in a case of a
0127          * non-legacy DT.
0128          */
0129         reset_control_put(rst_utmi);
0130     }
0131
0132     of_node_put(phy_np);
0133
0134     /* reset control is shared, hence initialize it first */
0135     err = reset_control_deassert(rst);
0136     if (err)
0137         return err;
0138
0139     err = reset_control_assert(rst);
0140     if (err)
0141         return err;
0142
0143     udelay(1);
0144
0145     err = reset_control_deassert(rst);
0146     if (err)
0147         return err;
0148
0149     return 0;
0150 }
0151
0152 static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
0153 {
0154     struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
0155     struct ehci_hcd *ehci;
0156
0157     switch (event) {
0158     case CI_HDRC_CONTROLLER_RESET_EVENT:
0159         if (ci->hcd) {
0160             ehci = hcd_to_ehci(ci->hcd);
0161             ehci->has_tdi_phy_lpm = false;
0162             ehci_writel(ehci, usb->soc->txfifothresh << 16,
0163                     &ehci->regs->txfill_tuning);
0164         }
0165         break;
0166     }
0167
0168     return 0;
0169 }
0170
0171 static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
0172                      u32 __iomem *portsc_reg,
0173                      unsigned long *flags)
0174 {
0175     u32 saved_usbintr, temp;
0176     unsigned int i, tries;
0177     int retval = 0;
0178
0179     saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
0180     /* disable USB interrupt */
0181     ehci_writel(ehci, 0, &ehci->regs->intr_enable);
0182     spin_unlock_irqrestore(&ehci->lock, *flags);
0183
0184     /*
0185      * Here we have to do Port Reset at most twice for
0186      * Port Enable bit to be set.
0187      */
0188     for (i = 0; i < 2; i++) {
0189         temp = ehci_readl(ehci, portsc_reg);
0190         temp |= PORT_RESET;
0191         ehci_writel(ehci, temp, portsc_reg);
0192         fsleep(10000);
0193         temp &= ~PORT_RESET;
0194         ehci_writel(ehci, temp, portsc_reg);
0195         fsleep(1000);
0196         tries = 100;
0197         do {
0198             fsleep(1000);
0199             /*
0200              * Up to this point, Port Enable bit is
0201              * expected to be set after 2 ms waiting.
0202              * USB1 usually takes extra 45 ms, for safety,
0203              * we take 100 ms as timeout.
0204              */
0205             temp = ehci_readl(ehci, portsc_reg);
0206         } while (!(temp & PORT_PE) && tries--);
0207         if (temp & PORT_PE)
0208             break;
0209     }
0210     if (i == 2)
0211         retval = -ETIMEDOUT;
0212
0213     /*
0214      * Clear Connect Status Change bit if it's set.
0215      * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
0216      */
0217     if (temp & PORT_CSC)
0218         ehci_writel(ehci, PORT_CSC, portsc_reg);
0219
0220     /*
0221      * Write to clear any interrupt status bits that might be set
0222      * during port reset.
0223      */
0224     temp = ehci_readl(ehci, &ehci->regs->status);
0225     ehci_writel(ehci, temp, &ehci->regs->status);
0226
0227     /* restore original interrupt-enable bits */
0228     spin_lock_irqsave(&ehci->lock, *flags);
0229     ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
0230
0231     return retval;
0232 }
0233
0234 static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
0235                   u16 wIndex, char *buf, u16 wLength,
0236                   bool *done, unsigned long *flags)
0237 {
0238     struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
0239     struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
0240     u32 __iomem *status_reg;
0241     int retval = 0;
0242
0243     status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
0244
0245     switch (typeReq) {
0246     case SetPortFeature:
0247         if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
0248             break;
0249
0250         /* for USB1 port we need to issue Port Reset twice internally */
0251         retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
0252         *done  = true;
0253         break;
0254     }
0255
0256     return retval;
0257 }
0258
0259 static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
0260 {
0261     /*
0262      * Touching any register which belongs to AHB clock domain will
0263      * hang CPU if USB controller is put into low power mode because
0264      * AHB USB clock is gated on Tegra in the LPM.
0265      *
0266      * Tegra PHY has a separate register for checking the clock status
0267      * and usb_phy_set_suspend() takes care of gating/ungating the clocks
0268      * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
0269      * shouldn't be touched directly by the CI driver.
0270      */
0271     usb_phy_set_suspend(ci->usb_phy, enable);
0272 }
0273
0274 static int tegra_usb_probe(struct platform_device *pdev)
0275 {
0276     const struct tegra_usb_soc_info *soc;
0277     struct tegra_usb *usb;
0278     int err;
0279
0280     usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
0281     if (!usb)
0282         return -ENOMEM;
0283
0284     platform_set_drvdata(pdev, usb);
0285
0286     soc = of_device_get_match_data(&pdev->dev);
0287     if (!soc) {
0288         dev_err(&pdev->dev, "failed to match OF data\n");
0289         return -EINVAL;
0290     }
0291
0292     usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
0293     if (IS_ERR(usb->phy))
0294         return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
0295                      "failed to get PHY\n");
0296
0297     usb->clk = devm_clk_get(&pdev->dev, NULL);
0298     if (IS_ERR(usb->clk)) {
0299         err = PTR_ERR(usb->clk);
0300         dev_err(&pdev->dev, "failed to get clock: %d\n", err);
0301         return err;
0302     }
0303
0304     err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
0305     if (err)
0306         return err;
0307
0308     pm_runtime_enable(&pdev->dev);
0309     err = pm_runtime_resume_and_get(&pdev->dev);
0310     if (err)
0311         return err;
0312
0313     if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
0314         usb->needs_double_reset = true;
0315
0316     err = tegra_usb_reset_controller(&pdev->dev);
0317     if (err) {
0318         dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
0319         goto fail_power_off;
0320     }
0321
0322     /*
0323      * USB controller registers shouldn't be touched before PHY is
0324      * initialized, otherwise CPU will hang because clocks are gated.
0325      * PHY driver controls gating of internal USB clocks on Tegra.
0326      */
0327     err = usb_phy_init(usb->phy);
0328     if (err)
0329         goto fail_power_off;
0330
0331     /* setup and register ChipIdea HDRC device */
0332     usb->soc = soc;
0333     usb->data.name = "tegra-usb";
0334     usb->data.flags = soc->flags;
0335     usb->data.usb_phy = usb->phy;
0336     usb->data.dr_mode = soc->dr_mode;
0337     usb->data.capoffset = DEF_CAPOFFSET;
0338     usb->data.enter_lpm = tegra_usb_enter_lpm;
0339     usb->data.hub_control = tegra_ehci_hub_control;
0340     usb->data.notify_event = tegra_usb_notify_event;
0341
0342     /* Tegra PHY driver currently doesn't support LPM for ULPI */
0343     if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
0344         usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
0345
0346     usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
0347                       pdev->num_resources, &usb->data);
0348     if (IS_ERR(usb->dev)) {
0349         err = PTR_ERR(usb->dev);
0350         dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
0351         goto phy_shutdown;
0352     }
0353
0354     return 0;
0355
0356 phy_shutdown:
0357     usb_phy_shutdown(usb->phy);
0358 fail_power_off:
0359     pm_runtime_put_sync_suspend(&pdev->dev);
0360     pm_runtime_force_suspend(&pdev->dev);
0361
0362     return err;
0363 }
0364
0365 static int tegra_usb_remove(struct platform_device *pdev)
0366 {
0367     struct tegra_usb *usb = platform_get_drvdata(pdev);
0368
0369     ci_hdrc_remove_device(usb->dev);
0370     usb_phy_shutdown(usb->phy);
0371
0372     pm_runtime_put_sync_suspend(&pdev->dev);
0373     pm_runtime_force_suspend(&pdev->dev);
0374
0375     return 0;
0376 }
0377
0378 static int __maybe_unused tegra_usb_runtime_resume(struct device *dev)
0379 {
0380     struct tegra_usb *usb = dev_get_drvdata(dev);
0381     int err;
0382
0383     err = clk_prepare_enable(usb->clk);
0384     if (err < 0) {
0385         dev_err(dev, "failed to enable clock: %d\n", err);
0386         return err;
0387     }
0388
0389     return 0;
0390 }
0391
0392 static int __maybe_unused tegra_usb_runtime_suspend(struct device *dev)
0393 {
0394     struct tegra_usb *usb = dev_get_drvdata(dev);
0395
0396     clk_disable_unprepare(usb->clk);
0397
0398     return 0;
0399 }
0400
0401 static const struct dev_pm_ops tegra_usb_pm = {
0402     SET_RUNTIME_PM_OPS(tegra_usb_runtime_suspend, tegra_usb_runtime_resume,
0403                NULL)
0404 };
0405
0406 static struct platform_driver tegra_usb_driver = {
0407     .driver = {
0408         .name = "tegra-usb",
0409         .of_match_table = tegra_usb_of_match,
0410         .pm = &tegra_usb_pm,
0411     },
0412     .probe = tegra_usb_probe,
0413     .remove = tegra_usb_remove,
0414 };
0415 module_platform_driver(tegra_usb_driver);
0416
0417 MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
0418 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
0419 MODULE_LICENSE("GPL v2");