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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ci.h - common structures, functions, and macros of the ChipIdea driver
0004  *
0005  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
0006  *
0007  * Author: David Lopo
0008  */
0009 
0010 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
0011 #define __DRIVERS_USB_CHIPIDEA_CI_H
0012 
0013 #include <linux/list.h>
0014 #include <linux/irqreturn.h>
0015 #include <linux/usb.h>
0016 #include <linux/usb/gadget.h>
0017 #include <linux/usb/otg-fsm.h>
0018 #include <linux/usb/otg.h>
0019 #include <linux/usb/role.h>
0020 #include <linux/ulpi/interface.h>
0021 
0022 /******************************************************************************
0023  * DEFINE
0024  *****************************************************************************/
0025 #define TD_PAGE_COUNT      5
0026 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
0027 #define ENDPT_MAX          32
0028 #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
0029 
0030 /******************************************************************************
0031  * REGISTERS
0032  *****************************************************************************/
0033 /* Identification Registers */
0034 #define ID_ID               0x0
0035 #define ID_HWGENERAL            0x4
0036 #define ID_HWHOST           0x8
0037 #define ID_HWDEVICE         0xc
0038 #define ID_HWTXBUF          0x10
0039 #define ID_HWRXBUF          0x14
0040 #define ID_SBUSCFG          0x90
0041 
0042 /* register indices */
0043 enum ci_hw_regs {
0044     CAP_CAPLENGTH,
0045     CAP_HCCPARAMS,
0046     CAP_DCCPARAMS,
0047     CAP_TESTMODE,
0048     CAP_LAST = CAP_TESTMODE,
0049     OP_USBCMD,
0050     OP_USBSTS,
0051     OP_USBINTR,
0052     OP_FRINDEX,
0053     OP_DEVICEADDR,
0054     OP_ENDPTLISTADDR,
0055     OP_TTCTRL,
0056     OP_BURSTSIZE,
0057     OP_ULPI_VIEWPORT,
0058     OP_PORTSC,
0059     OP_DEVLC,
0060     OP_OTGSC,
0061     OP_USBMODE,
0062     OP_ENDPTSETUPSTAT,
0063     OP_ENDPTPRIME,
0064     OP_ENDPTFLUSH,
0065     OP_ENDPTSTAT,
0066     OP_ENDPTCOMPLETE,
0067     OP_ENDPTCTRL,
0068     /* endptctrl1..15 follow */
0069     OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
0070 };
0071 
0072 /******************************************************************************
0073  * STRUCTURES
0074  *****************************************************************************/
0075 /**
0076  * struct ci_hw_ep - endpoint representation
0077  * @ep: endpoint structure for gadget drivers
0078  * @dir: endpoint direction (TX/RX)
0079  * @num: endpoint number
0080  * @type: endpoint type
0081  * @name: string description of the endpoint
0082  * @qh: queue head for this endpoint
0083  * @wedge: is the endpoint wedged
0084  * @ci: pointer to the controller
0085  * @lock: pointer to controller's spinlock
0086  * @td_pool: pointer to controller's TD pool
0087  */
0088 struct ci_hw_ep {
0089     struct usb_ep               ep;
0090     u8                  dir;
0091     u8                  num;
0092     u8                  type;
0093     char                    name[16];
0094     struct {
0095         struct list_head    queue;
0096         struct ci_hw_qh     *ptr;
0097         dma_addr_t      dma;
0098     }                   qh;
0099     int                 wedge;
0100 
0101     /* global resources */
0102     struct ci_hdrc              *ci;
0103     spinlock_t              *lock;
0104     struct dma_pool             *td_pool;
0105     struct td_node              *pending_td;
0106 };
0107 
0108 enum ci_role {
0109     CI_ROLE_HOST = 0,
0110     CI_ROLE_GADGET,
0111     CI_ROLE_END,
0112 };
0113 
0114 enum ci_revision {
0115     CI_REVISION_1X = 10,    /* Revision 1.x */
0116     CI_REVISION_20 = 20, /* Revision 2.0 */
0117     CI_REVISION_21, /* Revision 2.1 */
0118     CI_REVISION_22, /* Revision 2.2 */
0119     CI_REVISION_23, /* Revision 2.3 */
0120     CI_REVISION_24, /* Revision 2.4 */
0121     CI_REVISION_25, /* Revision 2.5 */
0122     CI_REVISION_25_PLUS, /* Revision above than 2.5 */
0123     CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
0124 };
0125 
0126 /**
0127  * struct ci_role_driver - host/gadget role driver
0128  * @start: start this role
0129  * @stop: stop this role
0130  * @irq: irq handler for this role
0131  * @name: role name string (host/gadget)
0132  */
0133 struct ci_role_driver {
0134     int     (*start)(struct ci_hdrc *);
0135     void        (*stop)(struct ci_hdrc *);
0136     irqreturn_t (*irq)(struct ci_hdrc *);
0137     const char  *name;
0138 };
0139 
0140 /**
0141  * struct hw_bank - hardware register mapping representation
0142  * @lpm: set if the device is LPM capable
0143  * @phys: physical address of the controller's registers
0144  * @abs: absolute address of the beginning of register window
0145  * @cap: capability registers
0146  * @op: operational registers
0147  * @size: size of the register window
0148  * @regmap: register lookup table
0149  */
0150 struct hw_bank {
0151     unsigned    lpm;
0152     resource_size_t phys;
0153     void __iomem    *abs;
0154     void __iomem    *cap;
0155     void __iomem    *op;
0156     size_t      size;
0157     void __iomem    *regmap[OP_LAST + 1];
0158 };
0159 
0160 /**
0161  * struct ci_hdrc - chipidea device representation
0162  * @dev: pointer to parent device
0163  * @lock: access synchronization
0164  * @hw_bank: hardware register mapping
0165  * @irq: IRQ number
0166  * @roles: array of supported roles for this controller
0167  * @role: current role
0168  * @is_otg: if the device is otg-capable
0169  * @fsm: otg finite state machine
0170  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
0171  * @hr_timeouts: time out list for active otg fsm timers
0172  * @enabled_otg_timer_bits: bits of enabled otg timers
0173  * @next_otg_timer: next nearest enabled timer to be expired
0174  * @work: work for role changing
0175  * @wq: workqueue thread
0176  * @qh_pool: allocation pool for queue heads
0177  * @td_pool: allocation pool for transfer descriptors
0178  * @gadget: device side representation for peripheral controller
0179  * @driver: gadget driver
0180  * @resume_state: save the state of gadget suspend from
0181  * @hw_ep_max: total number of endpoints supported by hardware
0182  * @ci_hw_ep: array of endpoints
0183  * @ep0_dir: ep0 direction
0184  * @ep0out: pointer to ep0 OUT endpoint
0185  * @ep0in: pointer to ep0 IN endpoint
0186  * @status: ep0 status request
0187  * @setaddr: if we should set the address on status completion
0188  * @address: usb address received from the host
0189  * @remote_wakeup: host-enabled remote wakeup
0190  * @suspended: suspended by host
0191  * @test_mode: the selected test mode
0192  * @platdata: platform specific information supplied by parent device
0193  * @vbus_active: is VBUS active
0194  * @ulpi: pointer to ULPI device, if any
0195  * @ulpi_ops: ULPI read/write ops for this device
0196  * @phy: pointer to PHY, if any
0197  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
0198  * @hcd: pointer to usb_hcd for ehci host driver
0199  * @id_event: indicates there is an id event, and handled at ci_otg_work
0200  * @b_sess_valid_event: indicates there is a vbus event, and handled
0201  * at ci_otg_work
0202  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
0203  * @supports_runtime_pm: if runtime pm is supported
0204  * @in_lpm: if the core in low power mode
0205  * @wakeup_int: if wakeup interrupt occur
0206  * @rev: The revision number for controller
0207  */
0208 struct ci_hdrc {
0209     struct device           *dev;
0210     spinlock_t          lock;
0211     struct hw_bank          hw_bank;
0212     int             irq;
0213     struct ci_role_driver       *roles[CI_ROLE_END];
0214     enum ci_role            role;
0215     bool                is_otg;
0216     struct usb_otg          otg;
0217     struct otg_fsm          fsm;
0218     struct hrtimer          otg_fsm_hrtimer;
0219     ktime_t             hr_timeouts[NUM_OTG_FSM_TIMERS];
0220     unsigned            enabled_otg_timer_bits;
0221     enum otg_fsm_timer      next_otg_timer;
0222     struct usb_role_switch      *role_switch;
0223     struct work_struct      work;
0224     struct workqueue_struct     *wq;
0225 
0226     struct dma_pool         *qh_pool;
0227     struct dma_pool         *td_pool;
0228 
0229     struct usb_gadget       gadget;
0230     struct usb_gadget_driver    *driver;
0231     enum usb_device_state       resume_state;
0232     unsigned            hw_ep_max;
0233     struct ci_hw_ep         ci_hw_ep[ENDPT_MAX];
0234     u32             ep0_dir;
0235     struct ci_hw_ep         *ep0out, *ep0in;
0236 
0237     struct usb_request      *status;
0238     bool                setaddr;
0239     u8              address;
0240     u8              remote_wakeup;
0241     u8              suspended;
0242     u8              test_mode;
0243 
0244     struct ci_hdrc_platform_data    *platdata;
0245     int             vbus_active;
0246     struct ulpi         *ulpi;
0247     struct ulpi_ops         ulpi_ops;
0248     struct phy          *phy;
0249     /* old usb_phy interface */
0250     struct usb_phy          *usb_phy;
0251     struct usb_hcd          *hcd;
0252     bool                id_event;
0253     bool                b_sess_valid_event;
0254     bool                imx28_write_fix;
0255     bool                supports_runtime_pm;
0256     bool                in_lpm;
0257     bool                wakeup_int;
0258     enum ci_revision        rev;
0259 };
0260 
0261 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
0262 {
0263     BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
0264     return ci->roles[ci->role];
0265 }
0266 
0267 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
0268 {
0269     int ret;
0270 
0271     if (role >= CI_ROLE_END)
0272         return -EINVAL;
0273 
0274     if (!ci->roles[role])
0275         return -ENXIO;
0276 
0277     ret = ci->roles[role]->start(ci);
0278     if (!ret)
0279         ci->role = role;
0280     return ret;
0281 }
0282 
0283 static inline void ci_role_stop(struct ci_hdrc *ci)
0284 {
0285     enum ci_role role = ci->role;
0286 
0287     if (role == CI_ROLE_END)
0288         return;
0289 
0290     ci->role = CI_ROLE_END;
0291 
0292     ci->roles[role]->stop(ci);
0293 }
0294 
0295 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
0296 {
0297     if (ci->role == CI_ROLE_HOST)
0298         return USB_ROLE_HOST;
0299     else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
0300         return USB_ROLE_DEVICE;
0301     else
0302         return USB_ROLE_NONE;
0303 }
0304 
0305 static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
0306 {
0307     if (role == USB_ROLE_HOST)
0308         return CI_ROLE_HOST;
0309     else if (role == USB_ROLE_DEVICE)
0310         return CI_ROLE_GADGET;
0311     else
0312         return CI_ROLE_END;
0313 }
0314 
0315 /**
0316  * hw_read_id_reg: reads from a identification register
0317  * @ci: the controller
0318  * @offset: offset from the beginning of identification registers region
0319  * @mask: bitfield mask
0320  *
0321  * This function returns register contents
0322  */
0323 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
0324 {
0325     return ioread32(ci->hw_bank.abs + offset) & mask;
0326 }
0327 
0328 /**
0329  * hw_write_id_reg: writes to a identification register
0330  * @ci: the controller
0331  * @offset: offset from the beginning of identification registers region
0332  * @mask: bitfield mask
0333  * @data: new value
0334  */
0335 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
0336                 u32 mask, u32 data)
0337 {
0338     if (~mask)
0339         data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
0340             | (data & mask);
0341 
0342     iowrite32(data, ci->hw_bank.abs + offset);
0343 }
0344 
0345 /**
0346  * hw_read: reads from a hw register
0347  * @ci: the controller
0348  * @reg:  register index
0349  * @mask: bitfield mask
0350  *
0351  * This function returns register contents
0352  */
0353 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
0354 {
0355     return ioread32(ci->hw_bank.regmap[reg]) & mask;
0356 }
0357 
0358 #ifdef CONFIG_SOC_IMX28
0359 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
0360 {
0361     __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
0362 }
0363 #else
0364 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
0365 {
0366 }
0367 #endif
0368 
0369 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
0370         void __iomem *addr)
0371 {
0372     if (ci->imx28_write_fix)
0373         imx28_ci_writel(val, addr);
0374     else
0375         iowrite32(val, addr);
0376 }
0377 
0378 /**
0379  * hw_write: writes to a hw register
0380  * @ci: the controller
0381  * @reg:  register index
0382  * @mask: bitfield mask
0383  * @data: new value
0384  */
0385 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
0386                 u32 mask, u32 data)
0387 {
0388     if (~mask)
0389         data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
0390             | (data & mask);
0391 
0392     __hw_write(ci, data, ci->hw_bank.regmap[reg]);
0393 }
0394 
0395 /**
0396  * hw_test_and_clear: tests & clears a hw register
0397  * @ci: the controller
0398  * @reg:  register index
0399  * @mask: bitfield mask
0400  *
0401  * This function returns register contents
0402  */
0403 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
0404                     u32 mask)
0405 {
0406     u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
0407 
0408     __hw_write(ci, val, ci->hw_bank.regmap[reg]);
0409     return val;
0410 }
0411 
0412 /**
0413  * hw_test_and_write: tests & writes a hw register
0414  * @ci: the controller
0415  * @reg:  register index
0416  * @mask: bitfield mask
0417  * @data: new value
0418  *
0419  * This function returns register contents
0420  */
0421 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
0422                     u32 mask, u32 data)
0423 {
0424     u32 val = hw_read(ci, reg, ~0);
0425 
0426     hw_write(ci, reg, mask, data);
0427     return (val & mask) >> __ffs(mask);
0428 }
0429 
0430 /**
0431  * ci_otg_is_fsm_mode: runtime check if otg controller
0432  * is in otg fsm mode.
0433  *
0434  * @ci: chipidea device
0435  */
0436 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
0437 {
0438 #ifdef CONFIG_USB_OTG_FSM
0439     struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
0440 
0441     return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
0442         ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
0443         otg_caps->hnp_support || otg_caps->adp_support);
0444 #else
0445     return false;
0446 #endif
0447 }
0448 
0449 int ci_ulpi_init(struct ci_hdrc *ci);
0450 void ci_ulpi_exit(struct ci_hdrc *ci);
0451 int ci_ulpi_resume(struct ci_hdrc *ci);
0452 
0453 u32 hw_read_intr_enable(struct ci_hdrc *ci);
0454 
0455 u32 hw_read_intr_status(struct ci_hdrc *ci);
0456 
0457 int hw_device_reset(struct ci_hdrc *ci);
0458 
0459 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
0460 
0461 u8 hw_port_test_get(struct ci_hdrc *ci);
0462 
0463 void hw_phymode_configure(struct ci_hdrc *ci);
0464 
0465 void ci_platform_configure(struct ci_hdrc *ci);
0466 
0467 void dbg_create_files(struct ci_hdrc *ci);
0468 
0469 void dbg_remove_files(struct ci_hdrc *ci);
0470 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */
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