usb/chipidea/bits.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * bits.h - register bits of the ChipIdea USB IP core
0004  *
0005  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
0006  *
0007  * Author: David Lopo
0008  */
0009
0010 #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
0011 #define __DRIVERS_USB_CHIPIDEA_BITS_H
0012
0013 #include <linux/usb/ehci_def.h>
0014
0015 /*
0016  * ID
0017  * For 1.x revision, bit24 - bit31 are reserved
0018  * For 2.x revision, bit25 - bit28 are 0x2
0019  */
0020 #define TAG           (0x1F << 16)
0021 #define REVISION          (0xF << 21)
0022 #define VERSION           (0xF << 25)
0023 #define CIVERSION         (0x7 << 29)
0024
0025 /* SBUSCFG */
0026 #define AHBBRST_MASK        0x7
0027
0028 /* HCCPARAMS */
0029 #define HCCPARAMS_LEN         BIT(17)
0030
0031 /* DCCPARAMS */
0032 #define DCCPARAMS_DEN         (0x1F << 0)
0033 #define DCCPARAMS_DC          BIT(7)
0034 #define DCCPARAMS_HC          BIT(8)
0035
0036 /* TESTMODE */
0037 #define TESTMODE_FORCE        BIT(0)
0038
0039 /* USBCMD */
0040 #define USBCMD_RS             BIT(0)
0041 #define USBCMD_RST            BIT(1)
0042 #define USBCMD_SUTW           BIT(13)
0043 #define USBCMD_ATDTW          BIT(14)
0044
0045 /* USBSTS & USBINTR */
0046 #define USBi_UI               BIT(0)
0047 #define USBi_UEI              BIT(1)
0048 #define USBi_PCI              BIT(2)
0049 #define USBi_URI              BIT(6)
0050 #define USBi_SLI              BIT(8)
0051
0052 /* DEVICEADDR */
0053 #define DEVICEADDR_USBADRA    BIT(24)
0054 #define DEVICEADDR_USBADR     (0x7FUL << 25)
0055
0056 /* TTCTRL */
0057 #define TTCTRL_TTHA_MASK    (0x7fUL << 24)
0058 /* Set non-zero value for internal TT Hub address representation */
0059 #define TTCTRL_TTHA     (0x7fUL << 24)
0060
0061 /* BURSTSIZE */
0062 #define RX_BURST_MASK       0xff
0063 #define TX_BURST_MASK       0xff00
0064
0065 /* PORTSC */
0066 #define PORTSC_CCS            BIT(0)
0067 #define PORTSC_CSC            BIT(1)
0068 #define PORTSC_PEC            BIT(3)
0069 #define PORTSC_OCC            BIT(5)
0070 #define PORTSC_FPR            BIT(6)
0071 #define PORTSC_SUSP           BIT(7)
0072 #define PORTSC_HSP            BIT(9)
0073 #define PORTSC_PP             BIT(12)
0074 #define PORTSC_PTC            (0x0FUL << 16)
0075 #define PORTSC_WKCN           BIT(20)
0076 #define PORTSC_PHCD(d)        ((d) ? BIT(22) : BIT(23))
0077 /* PTS and PTW for non lpm version only */
0078 #define PORTSC_PFSC           BIT(24)
0079 #define PORTSC_PTS(d)                       \
0080     (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
0081 #define PORTSC_PTW            BIT(28)
0082 #define PORTSC_STS            BIT(29)
0083
0084 #define PORTSC_W1C_BITS                     \
0085     (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
0086
0087 /* DEVLC */
0088 #define DEVLC_PFSC            BIT(23)
0089 #define DEVLC_PSPD            (0x03UL << 25)
0090 #define DEVLC_PSPD_HS         (0x02UL << 25)
0091 #define DEVLC_PTW             BIT(27)
0092 #define DEVLC_STS             BIT(28)
0093 #define DEVLC_PTS(d)          (u32)(((d) & 0x7) << 29)
0094
0095 /* Encoding for DEVLC_PTS and PORTSC_PTS */
0096 #define PTS_UTMI              0
0097 #define PTS_ULPI              2
0098 #define PTS_SERIAL            3
0099 #define PTS_HSIC              4
0100
0101 /* OTGSC */
0102 #define OTGSC_IDPU        BIT(5)
0103 #define OTGSC_HADP        BIT(6)
0104 #define OTGSC_HABA        BIT(7)
0105 #define OTGSC_ID          BIT(8)
0106 #define OTGSC_AVV         BIT(9)
0107 #define OTGSC_ASV         BIT(10)
0108 #define OTGSC_BSV         BIT(11)
0109 #define OTGSC_BSE         BIT(12)
0110 #define OTGSC_IDIS        BIT(16)
0111 #define OTGSC_AVVIS       BIT(17)
0112 #define OTGSC_ASVIS       BIT(18)
0113 #define OTGSC_BSVIS       BIT(19)
0114 #define OTGSC_BSEIS       BIT(20)
0115 #define OTGSC_1MSIS       BIT(21)
0116 #define OTGSC_DPIS        BIT(22)
0117 #define OTGSC_IDIE        BIT(24)
0118 #define OTGSC_AVVIE       BIT(25)
0119 #define OTGSC_ASVIE       BIT(26)
0120 #define OTGSC_BSVIE       BIT(27)
0121 #define OTGSC_BSEIE       BIT(28)
0122 #define OTGSC_1MSIE       BIT(29)
0123 #define OTGSC_DPIE        BIT(30)
0124 #define OTGSC_INT_EN_BITS   (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
0125                 | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
0126                 | OTGSC_DPIE)
0127 #define OTGSC_INT_STATUS_BITS   (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \
0128                 | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
0129                 | OTGSC_DPIS)
0130
0131 /* USBMODE */
0132 #define USBMODE_CM            (0x03UL <<  0)
0133 #define USBMODE_CM_DC         (0x02UL <<  0)
0134 #define USBMODE_SLOM          BIT(3)
0135 #define USBMODE_CI_SDIS       BIT(4)
0136
0137 /* ENDPTCTRL */
0138 #define ENDPTCTRL_RXS         BIT(0)
0139 #define ENDPTCTRL_RXT         (0x03UL <<  2)
0140 #define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
0141 #define ENDPTCTRL_RXE         BIT(7)
0142 #define ENDPTCTRL_TXS         BIT(16)
0143 #define ENDPTCTRL_TXT         (0x03UL << 18)
0144 #define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
0145 #define ENDPTCTRL_TXE         BIT(23)
0146
0147 #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */