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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * USBSS device controller driver header file
0004  *
0005  * Copyright (C) 2018-2019 Cadence.
0006  * Copyright (C) 2017-2018 NXP
0007  *
0008  * Author: Pawel Laszczak <pawell@cadence.com>
0009  *         Pawel Jez <pjez@cadence.com>
0010  *         Peter Chen <peter.chen@nxp.com>
0011  */
0012 #ifndef __LINUX_CDNS3_GADGET
0013 #define __LINUX_CDNS3_GADGET
0014 #include <linux/usb/gadget.h>
0015 #include <linux/dma-direction.h>
0016 
0017 /*
0018  * USBSS-DEV register interface.
0019  * This corresponds to the USBSS Device Controller Interface
0020  */
0021 
0022 /**
0023  * struct cdns3_usb_regs - device controller registers.
0024  * @usb_conf:      Global Configuration.
0025  * @usb_sts:       Global Status.
0026  * @usb_cmd:       Global Command.
0027  * @usb_itpn:      ITP/SOF number.
0028  * @usb_lpm:       Global Command.
0029  * @usb_ien:       USB Interrupt Enable.
0030  * @usb_ists:      USB Interrupt Status.
0031  * @ep_sel:        Endpoint Select.
0032  * @ep_traddr:     Endpoint Transfer Ring Address.
0033  * @ep_cfg:        Endpoint Configuration.
0034  * @ep_cmd:        Endpoint Command.
0035  * @ep_sts:        Endpoint Status.
0036  * @ep_sts_sid:    Endpoint Status.
0037  * @ep_sts_en:     Endpoint Status Enable.
0038  * @drbl:          Doorbell.
0039  * @ep_ien:        EP Interrupt Enable.
0040  * @ep_ists:       EP Interrupt Status.
0041  * @usb_pwr:       Global Power Configuration.
0042  * @usb_conf2:     Global Configuration 2.
0043  * @usb_cap1:      Capability 1.
0044  * @usb_cap2:      Capability 2.
0045  * @usb_cap3:      Capability 3.
0046  * @usb_cap4:      Capability 4.
0047  * @usb_cap5:      Capability 5.
0048  * @usb_cap6:      Capability 6.
0049  * @usb_cpkt1:     Custom Packet 1.
0050  * @usb_cpkt2:     Custom Packet 2.
0051  * @usb_cpkt3:     Custom Packet 3.
0052  * @ep_dma_ext_addr: Upper address for DMA operations.
0053  * @buf_addr:      Address for On-chip Buffer operations.
0054  * @buf_data:      Data for On-chip Buffer operations.
0055  * @buf_ctrl:      On-chip Buffer Access Control.
0056  * @dtrans:        DMA Transfer Mode.
0057  * @tdl_from_trb:  Source of TD Configuration.
0058  * @tdl_beh:       TDL Behavior Configuration.
0059  * @ep_tdl:        Endpoint TDL.
0060  * @tdl_beh2:      TDL Behavior 2 Configuration.
0061  * @dma_adv_td:    DMA Advance TD Configuration.
0062  * @reserved1:     Reserved.
0063  * @cfg_regs:      Configuration.
0064  * @reserved2:     Reserved.
0065  * @dma_axi_ctrl:  AXI Control.
0066  * @dma_axi_id:    AXI ID register.
0067  * @dma_axi_cap:   AXI Capability.
0068  * @dma_axi_ctrl0: AXI Control 0.
0069  * @dma_axi_ctrl1: AXI Control 1.
0070  */
0071 struct cdns3_usb_regs {
0072     __le32 usb_conf;
0073     __le32 usb_sts;
0074     __le32 usb_cmd;
0075     __le32 usb_itpn;
0076     __le32 usb_lpm;
0077     __le32 usb_ien;
0078     __le32 usb_ists;
0079     __le32 ep_sel;
0080     __le32 ep_traddr;
0081     __le32 ep_cfg;
0082     __le32 ep_cmd;
0083     __le32 ep_sts;
0084     __le32 ep_sts_sid;
0085     __le32 ep_sts_en;
0086     __le32 drbl;
0087     __le32 ep_ien;
0088     __le32 ep_ists;
0089     __le32 usb_pwr;
0090     __le32 usb_conf2;
0091     __le32 usb_cap1;
0092     __le32 usb_cap2;
0093     __le32 usb_cap3;
0094     __le32 usb_cap4;
0095     __le32 usb_cap5;
0096     __le32 usb_cap6;
0097     __le32 usb_cpkt1;
0098     __le32 usb_cpkt2;
0099     __le32 usb_cpkt3;
0100     __le32 ep_dma_ext_addr;
0101     __le32 buf_addr;
0102     __le32 buf_data;
0103     __le32 buf_ctrl;
0104     __le32 dtrans;
0105     __le32 tdl_from_trb;
0106     __le32 tdl_beh;
0107     __le32 ep_tdl;
0108     __le32 tdl_beh2;
0109     __le32 dma_adv_td;
0110     __le32 reserved1[26];
0111     __le32 cfg_reg1;
0112     __le32 dbg_link1;
0113     __le32 dbg_link2;
0114     __le32 cfg_regs[74];
0115     __le32 reserved2[51];
0116     __le32 dma_axi_ctrl;
0117     __le32 dma_axi_id;
0118     __le32 dma_axi_cap;
0119     __le32 dma_axi_ctrl0;
0120     __le32 dma_axi_ctrl1;
0121 };
0122 
0123 /* USB_CONF - bitmasks */
0124 /* Reset USB device configuration. */
0125 #define USB_CONF_CFGRST     BIT(0)
0126 /* Set Configuration. */
0127 #define USB_CONF_CFGSET     BIT(1)
0128 /* Disconnect USB device in SuperSpeed. */
0129 #define USB_CONF_USB3DIS    BIT(3)
0130 /* Disconnect USB device in HS/FS */
0131 #define USB_CONF_USB2DIS    BIT(4)
0132 /* Little Endian access - default */
0133 #define USB_CONF_LENDIAN    BIT(5)
0134 /*
0135  * Big Endian access. Driver assume that byte order for
0136  * SFRs access always is as Little Endian so this bit
0137  * is not used.
0138  */
0139 #define USB_CONF_BENDIAN    BIT(6)
0140 /* Device software reset. */
0141 #define USB_CONF_SWRST      BIT(7)
0142 /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
0143 #define USB_CONF_DSING      BIT(8)
0144 /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
0145 #define USB_CONF_DMULT      BIT(9)
0146 /* DMA clock turn-off enable. */
0147 #define USB_CONF_DMAOFFEN   BIT(10)
0148 /* DMA clock turn-off disable. */
0149 #define USB_CONF_DMAOFFDS   BIT(11)
0150 /* Clear Force Full Speed. */
0151 #define USB_CONF_CFORCE_FS  BIT(12)
0152 /* Set Force Full Speed. */
0153 #define USB_CONF_SFORCE_FS  BIT(13)
0154 /* Device enable. */
0155 #define USB_CONF_DEVEN      BIT(14)
0156 /* Device disable. */
0157 #define USB_CONF_DEVDS      BIT(15)
0158 /* L1 LPM state entry enable (used in HS/FS mode). */
0159 #define USB_CONF_L1EN       BIT(16)
0160 /* L1 LPM state entry disable (used in HS/FS mode). */
0161 #define USB_CONF_L1DS       BIT(17)
0162 /* USB 2.0 clock gate disable. */
0163 #define USB_CONF_CLK2OFFEN  BIT(18)
0164 /* USB 2.0 clock gate enable. */
0165 #define USB_CONF_CLK2OFFDS  BIT(19)
0166 /* L0 LPM state entry request (used in HS/FS mode). */
0167 #define USB_CONF_LGO_L0     BIT(20)
0168 /* USB 3.0 clock gate disable. */
0169 #define USB_CONF_CLK3OFFEN  BIT(21)
0170 /* USB 3.0 clock gate enable. */
0171 #define USB_CONF_CLK3OFFDS  BIT(22)
0172 /* Bit 23 is reserved*/
0173 /* U1 state entry enable (used in SS mode). */
0174 #define USB_CONF_U1EN       BIT(24)
0175 /* U1 state entry disable (used in SS mode). */
0176 #define USB_CONF_U1DS       BIT(25)
0177 /* U2 state entry enable (used in SS mode). */
0178 #define USB_CONF_U2EN       BIT(26)
0179 /* U2 state entry disable (used in SS mode). */
0180 #define USB_CONF_U2DS       BIT(27)
0181 /* U0 state entry request (used in SS mode). */
0182 #define USB_CONF_LGO_U0     BIT(28)
0183 /* U1 state entry request (used in SS mode). */
0184 #define USB_CONF_LGO_U1     BIT(29)
0185 /* U2 state entry request (used in SS mode). */
0186 #define USB_CONF_LGO_U2     BIT(30)
0187 /* SS.Inactive state entry request (used in SS mode) */
0188 #define USB_CONF_LGO_SSINACT    BIT(31)
0189 
0190 /* USB_STS - bitmasks */
0191 /*
0192  * Configuration status.
0193  * 1 - device is in the configured state.
0194  * 0 - device is not configured.
0195  */
0196 #define USB_STS_CFGSTS_MASK BIT(0)
0197 #define USB_STS_CFGSTS(p)   ((p) & USB_STS_CFGSTS_MASK)
0198 /*
0199  * On-chip memory overflow.
0200  * 0 - On-chip memory status OK.
0201  * 1 - On-chip memory overflow.
0202  */
0203 #define USB_STS_OV_MASK     BIT(1)
0204 #define USB_STS_OV(p)       ((p) & USB_STS_OV_MASK)
0205 /*
0206  * SuperSpeed connection status.
0207  * 0 - USB in SuperSpeed mode disconnected.
0208  * 1 - USB in SuperSpeed mode connected.
0209  */
0210 #define USB_STS_USB3CONS_MASK   BIT(2)
0211 #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
0212 /*
0213  * DMA transfer configuration status.
0214  * 0 - single request.
0215  * 1 - multiple TRB chain
0216  * Supported only for controller version <  DEV_VER_V3
0217  */
0218 #define USB_STS_DTRANS_MASK BIT(3)
0219 #define USB_STS_DTRANS(p)   ((p) & USB_STS_DTRANS_MASK)
0220 /*
0221  * Device speed.
0222  * 0 - Undefined (value after reset).
0223  * 1 - Low speed
0224  * 2 - Full speed
0225  * 3 - High speed
0226  * 4 - Super speed
0227  */
0228 #define USB_STS_USBSPEED_MASK   GENMASK(6, 4)
0229 #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
0230 #define USB_STS_LS      (0x1 << 4)
0231 #define USB_STS_FS      (0x2 << 4)
0232 #define USB_STS_HS      (0x3 << 4)
0233 #define USB_STS_SS      (0x4 << 4)
0234 #define DEV_UNDEFSPEED(p)   (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
0235 #define DEV_LOWSPEED(p)     (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
0236 #define DEV_FULLSPEED(p)    (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
0237 #define DEV_HIGHSPEED(p)    (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
0238 #define DEV_SUPERSPEED(p)   (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
0239 /*
0240  * Endianness for SFR access.
0241  * 0 - Little Endian order (default after hardware reset).
0242  * 1 - Big Endian order
0243  */
0244 #define USB_STS_ENDIAN_MASK BIT(7)
0245 #define USB_STS_ENDIAN(p)   ((p) & USB_STS_ENDIAN_MASK)
0246 /*
0247  * HS/FS clock turn-off status.
0248  * 0 - hsfs clock is always on.
0249  * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
0250  *          (default after hardware reset).
0251  */
0252 #define USB_STS_CLK2OFF_MASK    BIT(8)
0253 #define USB_STS_CLK2OFF(p)  ((p) & USB_STS_CLK2OFF_MASK)
0254 /*
0255  * PCLK clock turn-off status.
0256  * 0 - pclk clock is always on.
0257  * 1 - pclk clock turn-off in U3 (SS mode) is enabled
0258  *          (default after hardware reset).
0259  */
0260 #define USB_STS_CLK3OFF_MASK    BIT(9)
0261 #define USB_STS_CLK3OFF(p)  ((p) & USB_STS_CLK3OFF_MASK)
0262 /*
0263  * Controller in reset state.
0264  * 0 - Internal reset is active.
0265  * 1 - Internal reset is not active and controller is fully operational.
0266  */
0267 #define USB_STS_IN_RST_MASK BIT(10)
0268 #define USB_STS_IN_RST(p)   ((p) & USB_STS_IN_RST_MASK)
0269 /*
0270  * Status of the "TDL calculation basing on TRB" feature.
0271  * 0 - disabled
0272  * 1 - enabled
0273  * Supported only for DEV_VER_V2 controller version.
0274  */
0275 #define USB_STS_TDL_TRB_ENABLED BIT(11)
0276 /*
0277  * Device enable Status.
0278  * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
0279  * 1 - USB device is enabled (VBUS input is connected to the internal logic).
0280  */
0281 #define USB_STS_DEVS_MASK   BIT(14)
0282 #define USB_STS_DEVS(p)     ((p) & USB_STS_DEVS_MASK)
0283 /*
0284  * Address status.
0285  * 0 - USB device is default state.
0286  * 1 - USB device is at least in address state.
0287  */
0288 #define USB_STS_ADDRESSED_MASK  BIT(15)
0289 #define USB_STS_ADDRESSED(p)    ((p) & USB_STS_ADDRESSED_MASK)
0290 /*
0291  * L1 LPM state enable status (used in HS/FS mode).
0292  * 0 - Entering to L1 LPM state disabled.
0293  * 1 - Entering to L1 LPM state enabled.
0294  */
0295 #define USB_STS_L1ENS_MASK  BIT(16)
0296 #define USB_STS_L1ENS(p)    ((p) & USB_STS_L1ENS_MASK)
0297 /*
0298  * Internal VBUS connection status (used both in HS/FS  and SS mode).
0299  * 0 - internal VBUS is not detected.
0300  * 1 - internal VBUS is detected.
0301  */
0302 #define USB_STS_VBUSS_MASK  BIT(17)
0303 #define USB_STS_VBUSS(p)    ((p) & USB_STS_VBUSS_MASK)
0304 /*
0305  * HS/FS LPM  state (used in FS/HS mode).
0306  * 0 - L0 State
0307  * 1 - L1 State
0308  * 2 - L2 State
0309  * 3 - L3 State
0310  */
0311 #define USB_STS_LPMST_MASK  GENMASK(19, 18)
0312 #define DEV_L0_STATE(p)     (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
0313 #define DEV_L1_STATE(p)     (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
0314 #define DEV_L2_STATE(p)     (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
0315 #define DEV_L3_STATE(p)     (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
0316 /*
0317  * Disable HS status (used in FS/HS mode).
0318  * 0 - the disconnect bit for HS/FS mode is set .
0319  * 1 - the disconnect bit for HS/FS mode is not set.
0320  */
0321 #define USB_STS_USB2CONS_MASK   BIT(20)
0322 #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
0323 /*
0324  * HS/FS mode connection status (used in FS/HS mode).
0325  * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
0326  * 1 - High Speed operations in USB2.0 (FS/HS).
0327  */
0328 #define USB_STS_DISABLE_HS_MASK BIT(21)
0329 #define USB_STS_DISABLE_HS(p)   ((p) & USB_STS_DISABLE_HS_MASK)
0330 /*
0331  * U1 state enable status (used in SS mode).
0332  * 0 - Entering to  U1 state disabled.
0333  * 1 - Entering to  U1 state enabled.
0334  */
0335 #define USB_STS_U1ENS_MASK  BIT(24)
0336 #define USB_STS_U1ENS(p)    ((p) & USB_STS_U1ENS_MASK)
0337 /*
0338  * U2 state enable status (used in SS mode).
0339  * 0 - Entering to  U2 state disabled.
0340  * 1 - Entering to  U2 state enabled.
0341  */
0342 #define USB_STS_U2ENS_MASK  BIT(25)
0343 #define USB_STS_U2ENS(p)    ((p) & USB_STS_U2ENS_MASK)
0344 /*
0345  * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
0346  * SuperSpeed link state
0347  */
0348 #define USB_STS_LST_MASK    GENMASK(29, 26)
0349 #define DEV_LST_U0      (((p) & USB_STS_LST_MASK) == (0x0 << 26))
0350 #define DEV_LST_U1      (((p) & USB_STS_LST_MASK) == (0x1 << 26))
0351 #define DEV_LST_U2      (((p) & USB_STS_LST_MASK) == (0x2 << 26))
0352 #define DEV_LST_U3      (((p) & USB_STS_LST_MASK) == (0x3 << 26))
0353 #define DEV_LST_DISABLED    (((p) & USB_STS_LST_MASK) == (0x4 << 26))
0354 #define DEV_LST_RXDETECT    (((p) & USB_STS_LST_MASK) == (0x5 << 26))
0355 #define DEV_LST_INACTIVE    (((p) & USB_STS_LST_MASK) == (0x6 << 26))
0356 #define DEV_LST_POLLING     (((p) & USB_STS_LST_MASK) == (0x7 << 26))
0357 #define DEV_LST_RECOVERY    (((p) & USB_STS_LST_MASK) == (0x8 << 26))
0358 #define DEV_LST_HOT_RESET   (((p) & USB_STS_LST_MASK) == (0x9 << 26))
0359 #define DEV_LST_COMP_MODE   (((p) & USB_STS_LST_MASK) == (0xa << 26))
0360 #define DEV_LST_LB_STATE    (((p) & USB_STS_LST_MASK) == (0xb << 26))
0361 /*
0362  * DMA clock turn-off status.
0363  * 0 - DMA clock is always on (default after hardware reset).
0364  * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
0365  */
0366 #define USB_STS_DMAOFF_MASK BIT(30)
0367 #define USB_STS_DMAOFF(p)   ((p) & USB_STS_DMAOFF_MASK)
0368 /*
0369  * SFR Endian status.
0370  * 0 - Little Endian order (default after hardware reset).
0371  * 1 - Big Endian order.
0372  */
0373 #define USB_STS_ENDIAN2_MASK    BIT(31)
0374 #define USB_STS_ENDIAN2(p)  ((p) & USB_STS_ENDIAN2_MASK)
0375 
0376 /* USB_CMD -  bitmasks */
0377 /* Set Function Address */
0378 #define USB_CMD_SET_ADDR    BIT(0)
0379 /*
0380  * Function Address This field is saved to the device only when the field
0381  * SET_ADDR is set '1 ' during write to USB_CMD register.
0382  * Software is responsible for entering the address of the device during
0383  * SET_ADDRESS request service. This field should be set immediately after
0384  * the SETUP packet is decoded, and prior to confirmation of the status phase
0385  */
0386 #define USB_CMD_FADDR_MASK  GENMASK(7, 1)
0387 #define USB_CMD_FADDR(p)    (((p) << 1) & USB_CMD_FADDR_MASK)
0388 /* Send Function Wake Device Notification TP (used only in SS mode). */
0389 #define USB_CMD_SDNFW       BIT(8)
0390 /* Set Test Mode (used only in HS/FS mode). */
0391 #define USB_CMD_STMODE      BIT(9)
0392 /* Test mode selector (used only in HS/FS mode) */
0393 #define USB_STS_TMODE_SEL_MASK  GENMASK(11, 10)
0394 #define USB_STS_TMODE_SEL(p)    (((p) << 10) & USB_STS_TMODE_SEL_MASK)
0395 /*
0396  *  Send Latency Tolerance Message Device Notification TP (used only
0397  *  in SS mode).
0398  */
0399 #define USB_CMD_SDNLTM      BIT(12)
0400 /* Send Custom Transaction Packet (used only in SS mode) */
0401 #define USB_CMD_SPKT        BIT(13)
0402 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
0403 #define USB_CMD_DNFW_INT_MASK   GENMASK(23, 16)
0404 #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
0405 /*
0406  * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
0407  * (used only in SS mode).
0408  */
0409 #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
0410 #define USB_STS_DNLTM_BELT(p)   (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
0411 
0412 /* USB_ITPN - bitmasks */
0413 /*
0414  * ITP(SS) / SOF (HS/FS) number
0415  * In SS mode this field represent number of last ITP received from host.
0416  * In HS/FS mode this field represent number of last SOF received from host.
0417  */
0418 #define USB_ITPN_MASK       GENMASK(13, 0)
0419 #define USB_ITPN(p)     ((p) & USB_ITPN_MASK)
0420 
0421 /* USB_LPM - bitmasks */
0422 /* Host Initiated Resume Duration. */
0423 #define USB_LPM_HIRD_MASK   GENMASK(3, 0)
0424 #define USB_LPM_HIRD(p)     ((p) & USB_LPM_HIRD_MASK)
0425 /* Remote Wakeup Enable (bRemoteWake). */
0426 #define USB_LPM_BRW     BIT(4)
0427 
0428 /* USB_IEN - bitmasks */
0429 /* SS connection interrupt enable */
0430 #define USB_IEN_CONIEN      BIT(0)
0431 /* SS disconnection interrupt enable. */
0432 #define USB_IEN_DISIEN      BIT(1)
0433 /* USB SS warm reset interrupt enable. */
0434 #define USB_IEN_UWRESIEN    BIT(2)
0435 /* USB SS hot reset interrupt enable */
0436 #define USB_IEN_UHRESIEN    BIT(3)
0437 /* SS link U3 state enter interrupt enable (suspend).*/
0438 #define USB_IEN_U3ENTIEN    BIT(4)
0439 /* SS link U3 state exit interrupt enable (wakeup). */
0440 #define USB_IEN_U3EXTIEN    BIT(5)
0441 /* SS link U2 state enter interrupt enable.*/
0442 #define USB_IEN_U2ENTIEN    BIT(6)
0443 /* SS link U2 state exit interrupt enable.*/
0444 #define USB_IEN_U2EXTIEN    BIT(7)
0445 /* SS link U1 state enter interrupt enable.*/
0446 #define USB_IEN_U1ENTIEN    BIT(8)
0447 /* SS link U1 state exit interrupt enable.*/
0448 #define USB_IEN_U1EXTIEN    BIT(9)
0449 /* ITP/SOF packet detected interrupt enable.*/
0450 #define USB_IEN_ITPIEN      BIT(10)
0451 /* Wakeup interrupt enable.*/
0452 #define USB_IEN_WAKEIEN     BIT(11)
0453 /* Send Custom Packet interrupt enable.*/
0454 #define USB_IEN_SPKTIEN     BIT(12)
0455 /* HS/FS mode connection interrupt enable.*/
0456 #define USB_IEN_CON2IEN     BIT(16)
0457 /* HS/FS mode disconnection interrupt enable.*/
0458 #define USB_IEN_DIS2IEN     BIT(17)
0459 /* USB reset (HS/FS mode) interrupt enable.*/
0460 #define USB_IEN_U2RESIEN    BIT(18)
0461 /* LPM L2 state enter interrupt enable.*/
0462 #define USB_IEN_L2ENTIEN    BIT(20)
0463 /* LPM  L2 state exit interrupt enable.*/
0464 #define USB_IEN_L2EXTIEN    BIT(21)
0465 /* LPM L1 state enter interrupt enable.*/
0466 #define USB_IEN_L1ENTIEN    BIT(24)
0467 /* LPM  L1 state exit interrupt enable.*/
0468 #define USB_IEN_L1EXTIEN    BIT(25)
0469 /* Configuration reset interrupt enable.*/
0470 #define USB_IEN_CFGRESIEN   BIT(26)
0471 /* Start of the USB SS warm reset interrupt enable.*/
0472 #define USB_IEN_UWRESSIEN   BIT(28)
0473 /* End of the USB SS warm reset interrupt enable.*/
0474 #define USB_IEN_UWRESEIEN   BIT(29)
0475 
0476 #define USB_IEN_INIT  (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
0477                | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
0478                | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
0479                | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
0480 
0481 /* USB_ISTS - bitmasks */
0482 /* SS Connection detected. */
0483 #define USB_ISTS_CONI       BIT(0)
0484 /* SS Disconnection detected. */
0485 #define USB_ISTS_DISI       BIT(1)
0486 /* UUSB warm reset detectede. */
0487 #define USB_ISTS_UWRESI     BIT(2)
0488 /* USB hot reset detected. */
0489 #define USB_ISTS_UHRESI     BIT(3)
0490 /* U3 link state enter detected (suspend).*/
0491 #define USB_ISTS_U3ENTI     BIT(4)
0492 /* U3 link state exit detected (wakeup). */
0493 #define USB_ISTS_U3EXTI     BIT(5)
0494 /* U2 link state enter detected.*/
0495 #define USB_ISTS_U2ENTI     BIT(6)
0496 /* U2 link state exit detected.*/
0497 #define USB_ISTS_U2EXTI     BIT(7)
0498 /* U1 link state enter detected.*/
0499 #define USB_ISTS_U1ENTI     BIT(8)
0500 /* U1 link state exit detected.*/
0501 #define USB_ISTS_U1EXTI     BIT(9)
0502 /* ITP/SOF packet detected.*/
0503 #define USB_ISTS_ITPI       BIT(10)
0504 /* Wakeup detected.*/
0505 #define USB_ISTS_WAKEI      BIT(11)
0506 /* Send Custom Packet detected.*/
0507 #define USB_ISTS_SPKTI      BIT(12)
0508 /* HS/FS mode connection detected.*/
0509 #define USB_ISTS_CON2I      BIT(16)
0510 /* HS/FS mode disconnection detected.*/
0511 #define USB_ISTS_DIS2I      BIT(17)
0512 /* USB reset (HS/FS mode) detected.*/
0513 #define USB_ISTS_U2RESI     BIT(18)
0514 /* LPM L2 state enter detected.*/
0515 #define USB_ISTS_L2ENTI     BIT(20)
0516 /* LPM  L2 state exit detected.*/
0517 #define USB_ISTS_L2EXTI     BIT(21)
0518 /* LPM L1 state enter detected.*/
0519 #define USB_ISTS_L1ENTI     BIT(24)
0520 /* LPM L1 state exit detected.*/
0521 #define USB_ISTS_L1EXTI     BIT(25)
0522 /* USB configuration reset detected.*/
0523 #define USB_ISTS_CFGRESI    BIT(26)
0524 /* Start of the USB warm reset detected.*/
0525 #define USB_ISTS_UWRESSI    BIT(28)
0526 /* End of the USB warm reset detected.*/
0527 #define USB_ISTS_UWRESEI    BIT(29)
0528 
0529 /* USB_SEL - bitmasks */
0530 #define EP_SEL_EPNO_MASK    GENMASK(3, 0)
0531 /* Endpoint number. */
0532 #define EP_SEL_EPNO(p)      ((p) & EP_SEL_EPNO_MASK)
0533 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
0534 #define EP_SEL_DIR      BIT(7)
0535 
0536 #define select_ep_in(nr)    (EP_SEL_EPNO(p) | EP_SEL_DIR)
0537 #define select_ep_out       (EP_SEL_EPNO(p))
0538 
0539 /* EP_TRADDR - bitmasks */
0540 /* Transfer Ring address. */
0541 #define EP_TRADDR_TRADDR(p) ((p))
0542 
0543 /* EP_CFG - bitmasks */
0544 /* Endpoint enable */
0545 #define EP_CFG_ENABLE       BIT(0)
0546 /*
0547  *  Endpoint type.
0548  * 1 - isochronous
0549  * 2 - bulk
0550  * 3 - interrupt
0551  */
0552 #define EP_CFG_EPTYPE_MASK  GENMASK(2, 1)
0553 #define EP_CFG_EPTYPE(p)    (((p) << 1)  & EP_CFG_EPTYPE_MASK)
0554 /* Stream support enable (only in SS mode). */
0555 #define EP_CFG_STREAM_EN    BIT(3)
0556 /* TDL check (only in SS mode for BULK EP). */
0557 #define EP_CFG_TDL_CHK      BIT(4)
0558 /* SID check (only in SS mode for BULK OUT EP). */
0559 #define EP_CFG_SID_CHK      BIT(5)
0560 /* DMA transfer endianness. */
0561 #define EP_CFG_EPENDIAN     BIT(7)
0562 /* Max burst size (used only in SS mode). */
0563 #define EP_CFG_MAXBURST_MASK    GENMASK(11, 8)
0564 #define EP_CFG_MAXBURST(p)  (((p) << 8) & EP_CFG_MAXBURST_MASK)
0565 #define EP_CFG_MAXBURST_MAX 15
0566 /* ISO max burst. */
0567 #define EP_CFG_MULT_MASK    GENMASK(15, 14)
0568 #define EP_CFG_MULT(p)      (((p) << 14) & EP_CFG_MULT_MASK)
0569 #define EP_CFG_MULT_MAX     2
0570 /* ISO max burst. */
0571 #define EP_CFG_MAXPKTSIZE_MASK  GENMASK(26, 16)
0572 #define EP_CFG_MAXPKTSIZE(p)    (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
0573 /* Max number of buffered packets. */
0574 #define EP_CFG_BUFFERING_MASK   GENMASK(31, 27)
0575 #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
0576 #define EP_CFG_BUFFERING_MAX    15
0577 
0578 /* EP_CMD - bitmasks */
0579 /* Endpoint reset. */
0580 #define EP_CMD_EPRST        BIT(0)
0581 /* Endpoint STALL set. */
0582 #define EP_CMD_SSTALL       BIT(1)
0583 /* Endpoint STALL clear. */
0584 #define EP_CMD_CSTALL       BIT(2)
0585 /* Send ERDY TP. */
0586 #define EP_CMD_ERDY     BIT(3)
0587 /* Request complete. */
0588 #define EP_CMD_REQ_CMPL     BIT(5)
0589 /* Transfer descriptor ready. */
0590 #define EP_CMD_DRDY     BIT(6)
0591 /* Data flush. */
0592 #define EP_CMD_DFLUSH       BIT(7)
0593 /*
0594  * Transfer Descriptor Length write  (used only for Bulk Stream capable
0595  * endpoints in SS mode).
0596  * Bit Removed from DEV_VER_V3 controller version.
0597  */
0598 #define EP_CMD_STDL     BIT(8)
0599 /*
0600  * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
0601  * Bits Removed from DEV_VER_V3 controller version.
0602  */
0603 #define EP_CMD_TDL_MASK     GENMASK(15, 9)
0604 #define EP_CMD_TDL_SET(p)   (((p) << 9) & EP_CMD_TDL_MASK)
0605 #define EP_CMD_TDL_GET(p)   (((p) & EP_CMD_TDL_MASK) >> 9)
0606 #define EP_CMD_TDL_MAX      (EP_CMD_TDL_MASK >> 9)
0607 
0608 /* ERDY Stream ID value (used in SS mode). */
0609 #define EP_CMD_ERDY_SID_MASK    GENMASK(31, 16)
0610 #define EP_CMD_ERDY_SID(p)  (((p) << 16) & EP_CMD_ERDY_SID_MASK)
0611 
0612 /* EP_STS - bitmasks */
0613 /* Setup transfer complete. */
0614 #define EP_STS_SETUP        BIT(0)
0615 /* Endpoint STALL status. */
0616 #define EP_STS_STALL(p)     ((p) & BIT(1))
0617 /* Interrupt On Complete. */
0618 #define EP_STS_IOC      BIT(2)
0619 /* Interrupt on Short Packet. */
0620 #define EP_STS_ISP      BIT(3)
0621 /* Transfer descriptor missing. */
0622 #define EP_STS_DESCMIS      BIT(4)
0623 /* Stream Rejected (used only in SS mode) */
0624 #define EP_STS_STREAMR      BIT(5)
0625 /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
0626 #define EP_STS_MD_EXIT      BIT(6)
0627 /* TRB error. */
0628 #define EP_STS_TRBERR       BIT(7)
0629 /* Not ready (used only in SS mode). */
0630 #define EP_STS_NRDY     BIT(8)
0631 /* DMA busy bit. */
0632 #define EP_STS_DBUSY        BIT(9)
0633 /* Endpoint Buffer Empty */
0634 #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
0635 /* Current Cycle Status */
0636 #define EP_STS_CCS(p)       ((p) & BIT(11))
0637 /* Prime (used only in SS mode. */
0638 #define EP_STS_PRIME        BIT(12)
0639 /* Stream error (used only in SS mode). */
0640 #define EP_STS_SIDERR       BIT(13)
0641 /* OUT size mismatch. */
0642 #define EP_STS_OUTSMM       BIT(14)
0643 /* ISO transmission error. */
0644 #define EP_STS_ISOERR       BIT(15)
0645 /* Host Packet Pending (only for SS mode). */
0646 #define EP_STS_HOSTPP(p)    ((p) & BIT(16))
0647 /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
0648 #define EP_STS_SPSMST_MASK      GENMASK(18, 17)
0649 #define EP_STS_SPSMST_DISABLED(p)   (((p) & EP_STS_SPSMST_MASK) >> 17)
0650 #define EP_STS_SPSMST_IDLE(p)       (((p) & EP_STS_SPSMST_MASK) >> 17)
0651 #define EP_STS_SPSMST_START_STREAM(p)   (((p) & EP_STS_SPSMST_MASK) >> 17)
0652 #define EP_STS_SPSMST_MOVE_DATA(p)  (((p) & EP_STS_SPSMST_MASK) >> 17)
0653 /* Interrupt On Transfer complete. */
0654 #define EP_STS_IOT      BIT(19)
0655 /* OUT queue endpoint number. */
0656 #define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
0657 #define EP_STS_OUTQ_NO(p)   (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
0658 /* OUT queue valid flag. */
0659 #define EP_STS_OUTQ_VAL_MASK    BIT(28)
0660 #define EP_STS_OUTQ_VAL(p)  ((p) & EP_STS_OUTQ_VAL_MASK)
0661 /* SETUP WAIT. */
0662 #define EP_STS_STPWAIT      BIT(31)
0663 
0664 /* EP_STS_SID - bitmasks */
0665 /* Stream ID (used only in SS mode). */
0666 #define EP_STS_SID_MASK     GENMASK(15, 0)
0667 #define EP_STS_SID(p)       ((p) & EP_STS_SID_MASK)
0668 
0669 /* EP_STS_EN - bitmasks */
0670 /* SETUP interrupt enable. */
0671 #define EP_STS_EN_SETUPEN   BIT(0)
0672 /* OUT transfer missing descriptor enable. */
0673 #define EP_STS_EN_DESCMISEN BIT(4)
0674 /* Stream Rejected enable. */
0675 #define EP_STS_EN_STREAMREN BIT(5)
0676 /* Move Data Exit enable.*/
0677 #define EP_STS_EN_MD_EXITEN BIT(6)
0678 /* TRB enable. */
0679 #define EP_STS_EN_TRBERREN  BIT(7)
0680 /* NRDY enable. */
0681 #define EP_STS_EN_NRDYEN    BIT(8)
0682 /* Prime enable. */
0683 #define EP_STS_EN_PRIMEEEN  BIT(12)
0684 /* Stream error enable. */
0685 #define EP_STS_EN_SIDERREN  BIT(13)
0686 /* OUT size mismatch enable. */
0687 #define EP_STS_EN_OUTSMMEN  BIT(14)
0688 /* ISO transmission error enable. */
0689 #define EP_STS_EN_ISOERREN  BIT(15)
0690 /* Interrupt on Transmission complete enable. */
0691 #define EP_STS_EN_IOTEN     BIT(19)
0692 /* Setup Wait interrupt enable. */
0693 #define EP_STS_EN_STPWAITEN BIT(31)
0694 
0695 /* DRBL- bitmasks */
0696 #define DB_VALUE_BY_INDEX(index) (1 << (index))
0697 #define DB_VALUE_EP0_OUT    BIT(0)
0698 #define DB_VALUE_EP0_IN     BIT(16)
0699 
0700 /* EP_IEN - bitmasks */
0701 #define EP_IEN(index)       (1 << (index))
0702 #define EP_IEN_EP_OUT0      BIT(0)
0703 #define EP_IEN_EP_IN0       BIT(16)
0704 
0705 /* EP_ISTS - bitmasks */
0706 #define EP_ISTS(index)      (1 << (index))
0707 #define EP_ISTS_EP_OUT0     BIT(0)
0708 #define EP_ISTS_EP_IN0      BIT(16)
0709 
0710 /* USB_PWR- bitmasks */
0711 /*Power Shut Off capability enable*/
0712 #define PUSB_PWR_PSO_EN     BIT(0)
0713 /*Power Shut Off capability disable*/
0714 #define PUSB_PWR_PSO_DS     BIT(1)
0715 /*
0716  * Enables turning-off Reference Clock.
0717  * This bit is optional and implemented only when support for OTG is
0718  * implemented (indicated by OTG_READY bit set to '1').
0719  */
0720 #define PUSB_PWR_STB_CLK_SWITCH_EN  BIT(8)
0721 /*
0722  * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
0723  * is completed
0724  */
0725 #define PUSB_PWR_STB_CLK_SWITCH_DONE    BIT(9)
0726 /* This bit informs if Fast Registers Access is enabled. */
0727 #define PUSB_PWR_FST_REG_ACCESS_STAT    BIT(30)
0728 /* Fast Registers Access Enable. */
0729 #define PUSB_PWR_FST_REG_ACCESS     BIT(31)
0730 
0731 /* USB_CONF2- bitmasks */
0732 /*
0733  * Writing 1 disables TDL calculation basing on TRB feature in controller
0734  * for DMULT mode.
0735  * Bit supported only for DEV_VER_V2 version.
0736  */
0737 #define USB_CONF2_DIS_TDL_TRB       BIT(1)
0738 /*
0739  * Writing 1 enables TDL calculation basing on TRB feature in controller
0740  * for DMULT mode.
0741  * Bit supported only for DEV_VER_V2 version.
0742  */
0743 #define USB_CONF2_EN_TDL_TRB        BIT(2)
0744 
0745 /* USB_CAP1- bitmasks */
0746 /*
0747  * SFR Interface type
0748  * These field reflects type of SFR interface implemented:
0749  * 0x0 - OCP
0750  * 0x1 - AHB,
0751  * 0x2 - PLB
0752  * 0x3 - AXI
0753  * 0x4-0xF - reserved
0754  */
0755 #define USB_CAP1_SFR_TYPE_MASK  GENMASK(3, 0)
0756 #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
0757 #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
0758 #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
0759 #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
0760 /*
0761  * SFR Interface width
0762  * These field reflects width of SFR interface implemented:
0763  * 0x0 - 8 bit interface,
0764  * 0x1 - 16 bit interface,
0765  * 0x2 - 32 bit interface
0766  * 0x3 - 64 bit interface
0767  * 0x4-0xF - reserved
0768  */
0769 #define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
0770 #define DEV_SFR_WIDTH_8(p)  (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
0771 #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
0772 #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
0773 #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
0774 /*
0775  * DMA Interface type
0776  * These field reflects type of DMA interface implemented:
0777  * 0x0 - OCP
0778  * 0x1 - AHB,
0779  * 0x2 - PLB
0780  * 0x3 - AXI
0781  * 0x4-0xF - reserved
0782  */
0783 #define USB_CAP1_DMA_TYPE_MASK  GENMASK(11, 8)
0784 #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
0785 #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
0786 #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
0787 #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
0788 /*
0789  * DMA Interface width
0790  * These field reflects width of DMA interface implemented:
0791  * 0x0 - reserved,
0792  * 0x1 - reserved,
0793  * 0x2 - 32 bit interface
0794  * 0x3 - 64 bit interface
0795  * 0x4-0xF - reserved
0796  */
0797 #define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
0798 #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
0799 #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
0800 /*
0801  * USB3 PHY Interface type
0802  * These field reflects type of USB3 PHY interface implemented:
0803  * 0x0 - USB PIPE,
0804  * 0x1 - RMMI,
0805  * 0x2-0xF - reserved
0806  */
0807 #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
0808 #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
0809 #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
0810 /*
0811  * USB3 PHY Interface width
0812  * These field reflects width of USB3 PHY interface implemented:
0813  * 0x0 - 8 bit PIPE interface,
0814  * 0x1 - 16 bit PIPE interface,
0815  * 0x2 - 32 bit PIPE interface,
0816  * 0x3 - 64 bit PIPE interface
0817  * 0x4-0xF - reserved
0818  * Note: When SSIC interface is implemented this field shows the width of
0819  * internal PIPE interface. The RMMI interface is always 20bit wide.
0820  */
0821 #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
0822 #define DEV_U3PHY_WIDTH_8(p) \
0823     (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
0824 #define DEV_U3PHY_WIDTH_16(p) \
0825     (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
0826 #define DEV_U3PHY_WIDTH_32(p) \
0827     (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
0828 #define DEV_U3PHY_WIDTH_64(p) \
0829     (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
0830 
0831 /*
0832  * USB2 PHY Interface enable
0833  * These field informs if USB2 PHY interface is implemented:
0834  * 0x0 - interface NOT implemented,
0835  * 0x1 - interface implemented
0836  */
0837 #define USB_CAP1_U2PHY_EN(p)    ((p) & BIT(24))
0838 /*
0839  * USB2 PHY Interface type
0840  * These field reflects type of USB2 PHY interface implemented:
0841  * 0x0 - UTMI,
0842  * 0x1 - ULPI
0843  */
0844 #define DEV_U2PHY_ULPI(p)   ((p) & BIT(25))
0845 /*
0846  * USB2 PHY Interface width
0847  * These field reflects width of USB2 PHY interface implemented:
0848  * 0x0 - 8 bit interface,
0849  * 0x1 - 16 bit interface,
0850  * Note: The ULPI interface is always 8bit wide.
0851  */
0852 #define DEV_U2PHY_WIDTH_16(p)   ((p) & BIT(26))
0853 /*
0854  * OTG Ready
0855  * 0x0 - pure device mode
0856  * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
0857  */
0858 #define USB_CAP1_OTG_READY(p)   ((p) & BIT(27))
0859 
0860 /*
0861  * When set, indicates that controller supports automatic internal TDL
0862  * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
0863  * Supported only for DEV_VER_V2 controller version.
0864  */
0865 #define USB_CAP1_TDL_FROM_TRB(p)    ((p) & BIT(28))
0866 
0867 /* USB_CAP2- bitmasks */
0868 /*
0869  * The actual size of the connected On-chip RAM memory in kB:
0870  * - 0 means 256 kB (max supported mem size)
0871  * - value other than 0 reflects the mem size in kB
0872  */
0873 #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
0874 /*
0875  * Max supported mem size
0876  * These field reflects width of on-chip RAM address bus width,
0877  * which determines max supported mem size:
0878  * 0x0-0x7 - reserved,
0879  * 0x8 - support for 4kB mem,
0880  * 0x9 - support for 8kB mem,
0881  * 0xA - support for 16kB mem,
0882  * 0xB - support for 32kB mem,
0883  * 0xC - support for 64kB mem,
0884  * 0xD - support for 128kB mem,
0885  * 0xE - support for 256kB mem,
0886  * 0xF - reserved
0887  */
0888 #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
0889 
0890 /* USB_CAP3- bitmasks */
0891 #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
0892 
0893 /* USB_CAP4- bitmasks */
0894 #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
0895 
0896 /* USB_CAP5- bitmasks */
0897 #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
0898 
0899 /* USB_CAP6- bitmasks */
0900 /* The USBSS-DEV Controller  Internal build number. */
0901 #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
0902 /* The USBSS-DEV Controller version number. */
0903 #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
0904 
0905 #define DEV_VER_NXP_V1      0x00024502
0906 #define DEV_VER_TI_V1       0x00024509
0907 #define DEV_VER_V2      0x0002450C
0908 #define DEV_VER_V3      0x0002450d
0909 
0910 /* DBG_LINK1- bitmasks */
0911 /*
0912  * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
0913  * time required for decoding the received LFPS as an LFPS.U1_Exit.
0914  */
0915 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p)   ((p) & GENMASK(7, 0))
0916 /*
0917  * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
0918  * phytxelecidle deassertion when LFPS.U1_Exit
0919  */
0920 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
0921 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p)   (((p) << 8) & GENMASK(15, 8))
0922 /*
0923  * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
0924  * Receiver termination detection sequence:
0925  * 0: it is possible that USBSS_DEV will terminate Farend receiver
0926  *    termination detection sequence
0927  * 1: USBSS_DEV will not terminate Far-end receiver termination
0928  *    detection sequence
0929  */
0930 #define DBG_LINK1_RXDET_BREAK_DIS       BIT(16)
0931 /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
0932 #define DBG_LINK1_LFPS_GEN_PING(p)      (((p) << 17) & GENMASK(21, 17))
0933 /*
0934  * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
0935  * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
0936  * cleared. Writing '0' has no effect
0937  */
0938 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET  BIT(24)
0939 /*
0940  * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
0941  * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
0942  * cleared. Writing '0' has no effect
0943  */
0944 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET  BIT(25)
0945 /*
0946  * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
0947  * the RXDET_BREAK_DIS field value to the device. This bit is automatically
0948  * cleared. Writing '0' has no effect
0949  */
0950 #define DBG_LINK1_RXDET_BREAK_DIS_SET       BIT(26)
0951 /*
0952  * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
0953  * the LFPS_GEN_PING field value to the device. This bit is automatically
0954  * cleared. Writing '0' has no effect."
0955  */
0956 #define DBG_LINK1_LFPS_GEN_PING_SET     BIT(27)
0957 
0958 /* DMA_AXI_CTRL- bitmasks */
0959 /* The mawprot pin configuration. */
0960 #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
0961 /* The marprot pin configuration. */
0962 #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
0963 #define DMA_AXI_CTRL_NON_SECURE 0x02
0964 
0965 #define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
0966 
0967 #define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
0968 
0969 /*-------------------------------------------------------------------------*/
0970 /*
0971  * USBSS-DEV DMA interface.
0972  */
0973 #define TRBS_PER_SEGMENT    600
0974 
0975 #define ISO_MAX_INTERVAL    10
0976 
0977 #define MAX_TRB_LENGTH          BIT(16)
0978 
0979 #if TRBS_PER_SEGMENT < 2
0980 #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
0981 #endif
0982 
0983 #define TRBS_PER_STREAM_SEGMENT 2
0984 
0985 #if TRBS_PER_STREAM_SEGMENT < 2
0986 #error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
0987 #endif
0988 
0989 /*
0990  *Only for ISOC endpoints - maximum number of TRBs is calculated as
0991  * pow(2, bInterval-1) * number of usb requests. It is limitation made by
0992  * driver to save memory. Controller must prepare TRB for each ITP even
0993  * if bInterval > 1. It's the reason why driver needs so many TRBs for
0994  * isochronous endpoints.
0995  */
0996 #define TRBS_PER_ISOC_SEGMENT   (ISO_MAX_INTERVAL * 8)
0997 
0998 #define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
0999                       TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
1000 /**
1001  * struct cdns3_trb - represent Transfer Descriptor block.
1002  * @buffer: pointer to buffer data
1003  * @length: length of data
1004  * @control:    control flags.
1005  *
1006  * This structure describes transfer block serviced by DMA module.
1007  */
1008 struct cdns3_trb {
1009     __le32 buffer;
1010     __le32 length;
1011     __le32 control;
1012 };
1013 
1014 #define TRB_SIZE        (sizeof(struct cdns3_trb))
1015 #define TRB_RING_SIZE       (TRB_SIZE * TRBS_PER_SEGMENT)
1016 #define TRB_STREAM_RING_SIZE    (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
1017 #define TRB_ISO_RING_SIZE   (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1018 #define TRB_CTRL_RING_SIZE  (TRB_SIZE * 2)
1019 
1020 /* TRB bit mask */
1021 #define TRB_TYPE_BITMASK    GENMASK(15, 10)
1022 #define TRB_TYPE(p)     ((p) << 10)
1023 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1024 
1025 /* TRB type IDs */
1026 /* bulk, interrupt, isoc , and control data stage */
1027 #define TRB_NORMAL      1
1028 /* TRB for linking ring segments */
1029 #define TRB_LINK        6
1030 
1031 /* Cycle bit - indicates TRB ownership by driver or hw*/
1032 #define TRB_CYCLE       BIT(0)
1033 /*
1034  * When set to '1', the device will toggle its interpretation of the Cycle bit
1035  */
1036 #define TRB_TOGGLE      BIT(1)
1037 /*
1038  * The controller will set it if OUTSMM (OUT size mismatch) is detected,
1039  * this bit is for normal TRB
1040  */
1041 #define TRB_SMM         BIT(1)
1042 
1043 /*
1044  * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1045  * processed while USB short packet was received. No more buffers defined by
1046  * the TD will be used. DMA will automatically advance to next TD.
1047  * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1048  * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1049  *   is detected independent if ISP is set or not.
1050  */
1051 #define TRB_SP          BIT(1)
1052 
1053 /* Interrupt on short packet*/
1054 #define TRB_ISP         BIT(2)
1055 /*Setting this bit enables FIFO DMA operation mode*/
1056 #define TRB_FIFO_MODE       BIT(3)
1057 /* Set PCIe no snoop attribute */
1058 #define TRB_CHAIN       BIT(4)
1059 /* Interrupt on completion */
1060 #define TRB_IOC         BIT(5)
1061 
1062 /* stream ID bitmasks. */
1063 #define TRB_STREAM_ID_BITMASK       GENMASK(31, 16)
1064 #define TRB_STREAM_ID(p)        ((p) << 16)
1065 #define TRB_FIELD_TO_STREAMID(p)    (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1066 
1067 /* Size of TD expressed in USB packets for HS/FS mode. */
1068 #define TRB_TDL_HS_SIZE(p)  (((p) << 16) & GENMASK(31, 16))
1069 #define TRB_TDL_HS_SIZE_GET(p)  (((p) & GENMASK(31, 16)) >> 16)
1070 
1071 /* transfer_len bitmasks. */
1072 #define TRB_LEN(p)      ((p) & GENMASK(16, 0))
1073 
1074 /* Size of TD expressed in USB packets for SS mode. */
1075 #define TRB_TDL_SS_SIZE(p)  (((p) << 17) & GENMASK(23, 17))
1076 #define TRB_TDL_SS_SIZE_GET(p)  (((p) & GENMASK(23, 17)) >> 17)
1077 
1078 /* transfer_len bitmasks - bits 31:24 */
1079 #define TRB_BURST_LEN(p)    ((unsigned int)((p) << 24) & GENMASK(31, 24))
1080 #define TRB_BURST_LEN_GET(p)    (((p) & GENMASK(31, 24)) >> 24)
1081 
1082 /* Data buffer pointer bitmasks*/
1083 #define TRB_BUFFER(p)       ((p) & GENMASK(31, 0))
1084 
1085 /*-------------------------------------------------------------------------*/
1086 /* Driver numeric constants */
1087 
1088 /* Such declaration should be added to ch9.h */
1089 #define USB_DEVICE_MAX_ADDRESS      127
1090 
1091 /* Endpoint init values */
1092 #define CDNS3_EP_MAX_PACKET_LIMIT   1024
1093 #define CDNS3_EP_MAX_STREAMS        15
1094 #define CDNS3_EP0_MAX_PACKET_LIMIT  512
1095 
1096 /* All endpoints including EP0 */
1097 #define CDNS3_ENDPOINTS_MAX_COUNT   32
1098 #define CDNS3_EP_ZLP_BUF_SIZE       1024
1099 
1100 #define CDNS3_MAX_NUM_DESCMISS_BUF  32
1101 #define CDNS3_DESCMIS_BUF_SIZE      2048    /* Bytes */
1102 #define CDNS3_WA2_NUM_BUFFERS       128
1103 /*-------------------------------------------------------------------------*/
1104 /* Used structs */
1105 
1106 struct cdns3_device;
1107 
1108 /**
1109  * struct cdns3_endpoint - extended device side representation of USB endpoint.
1110  * @endpoint: usb endpoint
1111  * @pending_req_list: list of requests queuing on transfer ring.
1112  * @deferred_req_list: list of requests waiting for queuing on transfer ring.
1113  * @wa2_descmiss_req_list: list of requests internally allocated by driver.
1114  * @trb_pool: transfer ring - array of transaction buffers
1115  * @trb_pool_dma: dma address of transfer ring
1116  * @cdns3_dev: device associated with this endpoint
1117  * @name: a human readable name e.g. ep1out
1118  * @flags: specify the current state of endpoint
1119  * @descmis_req: internal transfer object used for getting data from on-chip
1120  *     buffer. It can happen only if function driver doesn't send usb_request
1121  *     object on time.
1122  * @dir: endpoint direction
1123  * @num: endpoint number (1 - 15)
1124  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
1125  * @interval: interval between packets used for ISOC endpoint.
1126  * @free_trbs: number of free TRBs in transfer ring
1127  * @num_trbs: number of all TRBs in transfer ring
1128  * @alloc_ring_size: size of the allocated TRB ring
1129  * @pcs: producer cycle state
1130  * @ccs: consumer cycle state
1131  * @enqueue: enqueue index in transfer ring
1132  * @dequeue: dequeue index in transfer ring
1133  * @trb_burst_size: number of burst used in trb.
1134  */
1135 struct cdns3_endpoint {
1136     struct usb_ep       endpoint;
1137     struct list_head    pending_req_list;
1138     struct list_head    deferred_req_list;
1139     struct list_head    wa2_descmiss_req_list;
1140     int         wa2_counter;
1141 
1142     struct cdns3_trb    *trb_pool;
1143     dma_addr_t      trb_pool_dma;
1144 
1145     struct cdns3_device *cdns3_dev;
1146     char            name[20];
1147 
1148 #define EP_ENABLED      BIT(0)
1149 #define EP_STALLED      BIT(1)
1150 #define EP_STALL_PENDING    BIT(2)
1151 #define EP_WEDGE        BIT(3)
1152 #define EP_TRANSFER_STARTED BIT(4)
1153 #define EP_UPDATE_EP_TRBADDR    BIT(5)
1154 #define EP_PENDING_REQUEST  BIT(6)
1155 #define EP_RING_FULL        BIT(7)
1156 #define EP_CLAIMED      BIT(8)
1157 #define EP_DEFERRED_DRDY    BIT(9)
1158 #define EP_QUIRK_ISO_OUT_EN BIT(10)
1159 #define EP_QUIRK_END_TRANSFER   BIT(11)
1160 #define EP_QUIRK_EXTRA_BUF_DET  BIT(12)
1161 #define EP_QUIRK_EXTRA_BUF_EN   BIT(13)
1162 #define EP_TDLCHK_EN        BIT(15)
1163 #define EP_CONFIGURED       BIT(16)
1164     u32         flags;
1165 
1166     struct cdns3_request    *descmis_req;
1167 
1168     u8          dir;
1169     u8          num;
1170     u8          type;
1171     int         interval;
1172 
1173     int         free_trbs;
1174     int         num_trbs;
1175     int         alloc_ring_size;
1176     u8          pcs;
1177     u8          ccs;
1178     int         enqueue;
1179     int         dequeue;
1180     u8          trb_burst_size;
1181 
1182     unsigned int        wa1_set:1;
1183     struct cdns3_trb    *wa1_trb;
1184     unsigned int        wa1_trb_index;
1185     unsigned int        wa1_cycle_bit:1;
1186 
1187     /* Stream related */
1188     unsigned int        use_streams:1;
1189     unsigned int        prime_flag:1;
1190     u32         ep_sts_pending;
1191     u16         last_stream_id;
1192     u16         pending_tdl;
1193     unsigned int        stream_sg_idx;
1194 };
1195 
1196 /**
1197  * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1198  * @buf: aligned to 8 bytes data buffer. Buffer address used in
1199  *       TRB shall be aligned to 8.
1200  * @dma: dma address
1201  * @size: size of buffer
1202  * @in_use: inform if this buffer is associated with usb_request
1203  * @list: used to adding instance of this object to list
1204  */
1205 struct cdns3_aligned_buf {
1206     void            *buf;
1207     dma_addr_t      dma;
1208     u32         size;
1209     enum dma_data_direction dir;
1210     unsigned        in_use:1;
1211     struct list_head    list;
1212 };
1213 
1214 /**
1215  * struct cdns3_request - extended device side representation of usb_request
1216  *                        object .
1217  * @request: generic usb_request object describing single I/O request.
1218  * @priv_ep: extended representation of usb_ep object
1219  * @trb: the first TRB association with this request
1220  * @start_trb: number of the first TRB in transfer ring
1221  * @end_trb: number of the last TRB in transfer ring
1222  * @aligned_buf: object holds information about aligned buffer associated whit
1223  *               this endpoint
1224  * @flags: flag specifying special usage of request
1225  * @list: used by internally allocated request to add to wa2_descmiss_req_list.
1226  * @finished_trb: number of trb has already finished per request
1227  * @num_of_trb: how many trbs in this request
1228  */
1229 struct cdns3_request {
1230     struct usb_request      request;
1231     struct cdns3_endpoint       *priv_ep;
1232     struct cdns3_trb        *trb;
1233     int             start_trb;
1234     int             end_trb;
1235     struct cdns3_aligned_buf    *aligned_buf;
1236 #define REQUEST_PENDING         BIT(0)
1237 #define REQUEST_INTERNAL        BIT(1)
1238 #define REQUEST_INTERNAL_CH     BIT(2)
1239 #define REQUEST_ZLP         BIT(3)
1240 #define REQUEST_UNALIGNED       BIT(4)
1241     u32             flags;
1242     struct list_head        list;
1243     int             finished_trb;
1244     int             num_of_trb;
1245 };
1246 
1247 #define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1248 
1249 /*Stages used during enumeration process.*/
1250 #define CDNS3_SETUP_STAGE       0x0
1251 #define CDNS3_DATA_STAGE        0x1
1252 #define CDNS3_STATUS_STAGE      0x2
1253 
1254 /**
1255  * struct cdns3_device - represent USB device.
1256  * @dev: pointer to device structure associated whit this controller
1257  * @sysdev: pointer to the DMA capable device
1258  * @gadget: device side representation of the peripheral controller
1259  * @gadget_driver: pointer to the gadget driver
1260  * @dev_ver: device controller version.
1261  * @lock: for synchronizing
1262  * @regs: base address for device side registers
1263  * @setup_buf: used while processing usb control requests
1264  * @setup_dma: dma address for setup_buf
1265  * @zlp_buf - zlp buffer
1266  * @ep0_stage: ep0 stage during enumeration process.
1267  * @ep0_data_dir: direction for control transfer
1268  * @eps: array of pointers to all endpoints with exclusion ep0
1269  * @aligned_buf_list: list of aligned buffers internally allocated by driver
1270  * @aligned_buf_wq: workqueue freeing  no longer used aligned buf.
1271  * @selected_ep: actually selected endpoint. It's used only to improve
1272  *               performance.
1273  * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1274  * @u1_allowed: allow device transition to u1 state
1275  * @u2_allowed: allow device transition to u2 state
1276  * @is_selfpowered: device is self powered
1277  * @setup_pending: setup packet is processing by gadget driver
1278  * @hw_configured_flag: hardware endpoint configuration was set.
1279  * @wake_up_flag: allow device to remote up the host
1280  * @status_completion_no_call: indicate that driver is waiting for status s
1281  *     stage completion. It's used in deferred SET_CONFIGURATION request.
1282  * @onchip_buffers: number of available on-chip buffers.
1283  * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1284  * @pending_status_wq: workqueue handling status stage for deferred requests.
1285  * @pending_status_request: request for which status stage was deferred
1286  */
1287 struct cdns3_device {
1288     struct device           *dev;
1289     struct device           *sysdev;
1290 
1291     struct usb_gadget       gadget;
1292     struct usb_gadget_driver    *gadget_driver;
1293 
1294 #define CDNS_REVISION_V0        0x00024501
1295 #define CDNS_REVISION_V1        0x00024509
1296     u32             dev_ver;
1297 
1298     /* generic spin-lock for drivers */
1299     spinlock_t          lock;
1300 
1301     struct cdns3_usb_regs       __iomem *regs;
1302 
1303     struct dma_pool         *eps_dma_pool;
1304     struct usb_ctrlrequest      *setup_buf;
1305     dma_addr_t          setup_dma;
1306     void                *zlp_buf;
1307 
1308     u8              ep0_stage;
1309     int             ep0_data_dir;
1310 
1311     struct cdns3_endpoint       *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1312 
1313     struct list_head        aligned_buf_list;
1314     struct work_struct      aligned_buf_wq;
1315 
1316     u32             selected_ep;
1317     u16             isoch_delay;
1318 
1319     unsigned            wait_for_setup:1;
1320     unsigned            u1_allowed:1;
1321     unsigned            u2_allowed:1;
1322     unsigned            is_selfpowered:1;
1323     unsigned            setup_pending:1;
1324     unsigned            hw_configured_flag:1;
1325     unsigned            wake_up_flag:1;
1326     unsigned            status_completion_no_call:1;
1327     unsigned            using_streams:1;
1328     int             out_mem_is_allocated;
1329 
1330     struct work_struct      pending_status_wq;
1331     struct usb_request      *pending_status_request;
1332 
1333     /*in KB */
1334     u16             onchip_buffers;
1335     u16             onchip_used_size;
1336 
1337     u16             ep_buf_size;
1338     u16             ep_iso_burst;
1339 };
1340 
1341 void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1342 dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1343                  struct cdns3_trb *trb);
1344 enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1345 void cdns3_pending_setup_status_handler(struct work_struct *work);
1346 void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1347 void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1348 void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1349 void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1350 struct usb_request *cdns3_next_request(struct list_head *list);
1351 void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1352 int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1353 u8 cdns3_ep_addr_to_index(u8 ep_addr);
1354 int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1355 int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1356 void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1357 int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1358 struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1359                           gfp_t gfp_flags);
1360 void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1361                   struct usb_request *request);
1362 int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1363 void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1364                struct cdns3_request *priv_req,
1365                int status);
1366 
1367 int cdns3_init_ep0(struct cdns3_device *priv_dev,
1368            struct cdns3_endpoint *priv_ep);
1369 void cdns3_ep0_config(struct cdns3_device *priv_dev);
1370 int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable);
1371 void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1372 int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1373 
1374 #endif /* __LINUX_CDNS3_GADGET */
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