ufs/host/ufs-renesas.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Renesas UFS host controller driver
0004  *
0005  * Copyright (C) 2022 Renesas Electronics Corporation
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <ufs/ufshcd.h>
0018
0019 #include "ufshcd-pltfrm.h"
0020
0021 struct ufs_renesas_priv {
0022     bool initialized;   /* The hardware needs initialization once */
0023 };
0024
0025 enum {
0026     SET_PHY_INDEX_LO = 0,
0027     SET_PHY_INDEX_HI,
0028     TIMER_INDEX,
0029     MAX_INDEX
0030 };
0031
0032 enum ufs_renesas_init_param_mode {
0033     MODE_RESTORE,
0034     MODE_SET,
0035     MODE_SAVE,
0036     MODE_POLL,
0037     MODE_WAIT,
0038     MODE_WRITE,
0039 };
0040
0041 #define PARAM_RESTORE(_reg, _index) \
0042         { .mode = MODE_RESTORE, .reg = _reg, .index = _index }
0043 #define PARAM_SET(_index, _set) \
0044         { .mode = MODE_SET, .index = _index, .u.set = _set }
0045 #define PARAM_SAVE(_reg, _mask, _index) \
0046         { .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \
0047           .index = _index }
0048 #define PARAM_POLL(_reg, _expected, _mask) \
0049         { .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \
0050           .mask = (u32)(_mask) }
0051 #define PARAM_WAIT(_delay_us) \
0052         { .mode = MODE_WAIT, .u.delay_us = _delay_us }
0053
0054 #define PARAM_WRITE(_reg, _val) \
0055         { .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
0056
0057 #define PARAM_WRITE_D0_D4(_d0, _d4) \
0058         PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
0059
0060 #define PARAM_WRITE_800_80C_POLL(_addr, _data_800)      \
0061         PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),  \
0062         PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
0063         PARAM_WRITE(0xd0, 0x0000080c),          \
0064         PARAM_POLL(0xd4, BIT(8), BIT(8))
0065
0066 #define PARAM_RESTORE_800_80C_POLL(_index)          \
0067         PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),  \
0068         PARAM_WRITE(0xd0, 0x00000800),          \
0069         PARAM_RESTORE(0xd4, _index),            \
0070         PARAM_WRITE(0xd0, 0x0000080c),          \
0071         PARAM_POLL(0xd4, BIT(8), BIT(8))
0072
0073 #define PARAM_WRITE_804_80C_POLL(_addr, _data_804)      \
0074         PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),  \
0075         PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
0076         PARAM_WRITE(0xd0, 0x0000080c),          \
0077         PARAM_POLL(0xd4, BIT(8), BIT(8))
0078
0079 #define PARAM_WRITE_828_82C_POLL(_data_828)         \
0080         PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),  \
0081         PARAM_WRITE_D0_D4(0x00000828, _data_828),   \
0082         PARAM_WRITE(0xd0, 0x0000082c),          \
0083         PARAM_POLL(0xd4, _data_828, _data_828)
0084
0085 #define PARAM_WRITE_PHY(_addr16, _data16)           \
0086         PARAM_WRITE(0xf0, 1),               \
0087         PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
0088         PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
0089         PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \
0090         PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \
0091         PARAM_WRITE_800_80C_POLL(0x1c, 0x01),       \
0092         PARAM_WRITE_828_82C_POLL(0x0f000000),       \
0093         PARAM_WRITE(0xf0, 0)
0094
0095 #define PARAM_SET_PHY(_addr16, _data16)             \
0096         PARAM_WRITE(0xf0, 1),               \
0097         PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
0098         PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
0099         PARAM_WRITE_800_80C_POLL(0x1c, 0x01),       \
0100         PARAM_WRITE_828_82C_POLL(0x0f000000),       \
0101         PARAM_WRITE_804_80C_POLL(0x1a, 0),      \
0102         PARAM_WRITE(0xd0, 0x00000808),          \
0103         PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO),   \
0104         PARAM_WRITE_804_80C_POLL(0x1b, 0),      \
0105         PARAM_WRITE(0xd0, 0x00000808),          \
0106         PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI),   \
0107         PARAM_WRITE_828_82C_POLL(0x0f000000),       \
0108         PARAM_WRITE(0xf0, 0),               \
0109         PARAM_WRITE(0xf0, 1),               \
0110         PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
0111         PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
0112         PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \
0113         PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO),   \
0114         PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
0115         PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI),   \
0116         PARAM_WRITE_800_80C_POLL(0x1c, 0x01),       \
0117         PARAM_WRITE_828_82C_POLL(0x0f000000),       \
0118         PARAM_WRITE(0xf0, 0)
0119
0120 #define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800)       \
0121         PARAM_WRITE(0xf0, _gpio),           \
0122         PARAM_WRITE_800_80C_POLL(_addr, _data_800), \
0123         PARAM_WRITE_828_82C_POLL(0x0f000000),       \
0124         PARAM_WRITE(0xf0, 0)
0125
0126 #define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \
0127         PARAM_WRITE(0xf0, _gpio),           \
0128         PARAM_WRITE_800_80C_POLL(_addr, 0),     \
0129         PARAM_WRITE(0xd0, 0x00000808),          \
0130         PARAM_POLL(0xd4, _expected, _mask),     \
0131         PARAM_WRITE(0xf0, 0)
0132
0133 struct ufs_renesas_init_param {
0134     enum ufs_renesas_init_param_mode mode;
0135     u32 reg;
0136     union {
0137         u32 expected;
0138         u32 delay_us;
0139         u32 set;
0140         u32 val;
0141     } u;
0142     u32 mask;
0143     u32 index;
0144 };
0145
0146 /* This setting is for SERIES B */
0147 static const struct ufs_renesas_init_param ufs_param[] = {
0148     PARAM_WRITE(0xc0, 0x49425308),
0149     PARAM_WRITE_D0_D4(0x00000104, 0x00000002),
0150     PARAM_WAIT(1),
0151     PARAM_WRITE_D0_D4(0x00000828, 0x00000200),
0152     PARAM_WAIT(1),
0153     PARAM_WRITE_D0_D4(0x00000828, 0x00000000),
0154     PARAM_WRITE_D0_D4(0x00000104, 0x00000001),
0155     PARAM_WRITE_D0_D4(0x00000940, 0x00000001),
0156     PARAM_WAIT(1),
0157     PARAM_WRITE_D0_D4(0x00000940, 0x00000000),
0158
0159     PARAM_WRITE(0xc0, 0x49425308),
0160     PARAM_WRITE(0xc0, 0x41584901),
0161
0162     PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),
0163     PARAM_WRITE_D0_D4(0x00000804, 0x00000000),
0164     PARAM_WRITE(0xd0, 0x0000080c),
0165     PARAM_POLL(0xd4, BIT(8), BIT(8)),
0166
0167     PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001),
0168
0169     PARAM_WRITE(0xd0, 0x00000804),
0170     PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)),
0171
0172     PARAM_WRITE(0xd0, 0x00000d00),
0173     PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX),
0174     PARAM_WRITE(0xd4, 0x00000000),
0175     PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),
0176     PARAM_WRITE_D0_D4(0x00000828, 0x08000000),
0177     PARAM_WRITE(0xd0, 0x0000082c),
0178     PARAM_POLL(0xd4, BIT(27), BIT(27)),
0179     PARAM_WRITE(0xd0, 0x00000d2c),
0180     PARAM_POLL(0xd4, BIT(0), BIT(0)),
0181
0182     /* phy setup */
0183     PARAM_INDIRECT_WRITE(1, 0x01, 0x001f),
0184     PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
0185     PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014),
0186     PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003),
0187     PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
0188     PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003),
0189     PARAM_INDIRECT_WRITE(7, 0x60, 0x0003),
0190     PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6),
0191     PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003),
0192
0193     PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)),
0194     PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)),
0195
0196     PARAM_INDIRECT_WRITE(1, 0x32, 0x0080),
0197     PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001),
0198     PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001),
0199     PARAM_INDIRECT_WRITE(0, 0x32, 0x0087),
0200
0201     PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061),
0202     PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009),
0203     PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005),
0204     PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058),
0205     PARAM_INDIRECT_WRITE(1, 0x39, 0x0027),
0206     PARAM_INDIRECT_WRITE(1, 0x47, 0x004c),
0207
0208     PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002),
0209     PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
0210
0211     PARAM_WRITE_PHY(0x0028, 0x0061),
0212     PARAM_WRITE_PHY(0x4014, 0x0061),
0213     PARAM_SET_PHY(0x401c, BIT(2)),
0214     PARAM_WRITE_PHY(0x4000, 0x0000),
0215     PARAM_WRITE_PHY(0x4001, 0x0000),
0216
0217     PARAM_WRITE_PHY(0x10ae, 0x0001),
0218     PARAM_WRITE_PHY(0x10ad, 0x0000),
0219     PARAM_WRITE_PHY(0x10af, 0x0001),
0220     PARAM_WRITE_PHY(0x10b6, 0x0001),
0221     PARAM_WRITE_PHY(0x10ae, 0x0000),
0222
0223     PARAM_WRITE_PHY(0x10ae, 0x0001),
0224     PARAM_WRITE_PHY(0x10ad, 0x0000),
0225     PARAM_WRITE_PHY(0x10af, 0x0002),
0226     PARAM_WRITE_PHY(0x10b6, 0x0001),
0227     PARAM_WRITE_PHY(0x10ae, 0x0000),
0228
0229     PARAM_WRITE_PHY(0x10ae, 0x0001),
0230     PARAM_WRITE_PHY(0x10ad, 0x0080),
0231     PARAM_WRITE_PHY(0x10af, 0x0000),
0232     PARAM_WRITE_PHY(0x10b6, 0x0001),
0233     PARAM_WRITE_PHY(0x10ae, 0x0000),
0234
0235     PARAM_WRITE_PHY(0x10ae, 0x0001),
0236     PARAM_WRITE_PHY(0x10ad, 0x0080),
0237     PARAM_WRITE_PHY(0x10af, 0x001a),
0238     PARAM_WRITE_PHY(0x10b6, 0x0001),
0239     PARAM_WRITE_PHY(0x10ae, 0x0000),
0240
0241     PARAM_INDIRECT_WRITE(7, 0x70, 0x0016),
0242     PARAM_INDIRECT_WRITE(7, 0x71, 0x0016),
0243     PARAM_INDIRECT_WRITE(7, 0x72, 0x0014),
0244     PARAM_INDIRECT_WRITE(7, 0x73, 0x0014),
0245     PARAM_INDIRECT_WRITE(7, 0x74, 0x0000),
0246     PARAM_INDIRECT_WRITE(7, 0x75, 0x0000),
0247     PARAM_INDIRECT_WRITE(7, 0x76, 0x0010),
0248     PARAM_INDIRECT_WRITE(7, 0x77, 0x0010),
0249     PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff),
0250     PARAM_INDIRECT_WRITE(7, 0x79, 0x0000),
0251
0252     PARAM_INDIRECT_WRITE(7, 0x19, 0x0007),
0253
0254     PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007),
0255
0256     PARAM_INDIRECT_WRITE(7, 0x24, 0x000c),
0257
0258     PARAM_INDIRECT_WRITE(7, 0x25, 0x000c),
0259
0260     PARAM_INDIRECT_WRITE(7, 0x62, 0x0000),
0261     PARAM_INDIRECT_WRITE(7, 0x63, 0x0000),
0262     PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
0263     PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
0264     PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004),
0265     PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
0266     PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)),
0267     PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)),
0268     /* end of phy setup */
0269
0270     PARAM_WRITE(0xf0, 0),
0271     PARAM_WRITE(0xd0, 0x00000d00),
0272     PARAM_RESTORE(0xd4, TIMER_INDEX),
0273 };
0274
0275 static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
0276 {
0277     ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
0278 }
0279
0280 static void ufs_renesas_reg_control(struct ufs_hba *hba,
0281                     const struct ufs_renesas_init_param *p)
0282 {
0283     static u32 save[MAX_INDEX];
0284     int ret;
0285     u32 val;
0286
0287     WARN_ON(p->index >= MAX_INDEX);
0288
0289     switch (p->mode) {
0290     case MODE_RESTORE:
0291         ufshcd_writel(hba, save[p->index], p->reg);
0292         break;
0293     case MODE_SET:
0294         save[p->index] |= p->u.set;
0295         break;
0296     case MODE_SAVE:
0297         save[p->index] = ufshcd_readl(hba, p->reg) & p->mask;
0298         break;
0299     case MODE_POLL:
0300         ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg,
0301                         val,
0302                         (val & p->mask) == p->u.expected,
0303                         10, 1000);
0304         if (ret)
0305             dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
0306                 __func__, ret, val, p->mask, p->u.expected);
0307         break;
0308     case MODE_WAIT:
0309         if (p->u.delay_us > 1000)
0310             mdelay(DIV_ROUND_UP(p->u.delay_us, 1000));
0311         else
0312             udelay(p->u.delay_us);
0313         break;
0314     case MODE_WRITE:
0315         ufshcd_writel(hba, p->u.val, p->reg);
0316         break;
0317     default:
0318         break;
0319     }
0320 }
0321
0322 static void ufs_renesas_pre_init(struct ufs_hba *hba)
0323 {
0324     const struct ufs_renesas_init_param *p = ufs_param;
0325     unsigned int i;
0326
0327     for (i = 0; i < ARRAY_SIZE(ufs_param); i++)
0328         ufs_renesas_reg_control(hba, &p[i]);
0329 }
0330
0331 static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
0332                      enum ufs_notify_change_status status)
0333 {
0334     struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
0335
0336     if (priv->initialized)
0337         return 0;
0338
0339     if (status == PRE_CHANGE)
0340         ufs_renesas_pre_init(hba);
0341
0342     priv->initialized = true;
0343
0344     return 0;
0345 }
0346
0347 static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on,
0348                     enum ufs_notify_change_status status)
0349 {
0350     if (on && status == PRE_CHANGE)
0351         pm_runtime_get_sync(hba->dev);
0352     else if (!on && status == POST_CHANGE)
0353         pm_runtime_put(hba->dev);
0354
0355     return 0;
0356 }
0357
0358 static int ufs_renesas_init(struct ufs_hba *hba)
0359 {
0360     struct ufs_renesas_priv *priv;
0361
0362     priv = devm_kmalloc(hba->dev, sizeof(*priv), GFP_KERNEL);
0363     if (!priv)
0364         return -ENOMEM;
0365     ufshcd_set_variant(hba, priv);
0366
0367     hba->quirks |= UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS | UFSHCD_QUIRK_HIBERN_FASTAUTO;
0368
0369     return 0;
0370 }
0371
0372 static const struct ufs_hba_variant_ops ufs_renesas_vops = {
0373     .name       = "renesas",
0374     .init       = ufs_renesas_init,
0375     .setup_clocks   = ufs_renesas_setup_clocks,
0376     .hce_enable_notify = ufs_renesas_hce_enable_notify,
0377     .dbg_register_dump = ufs_renesas_dbg_register_dump,
0378 };
0379
0380 static const struct of_device_id __maybe_unused ufs_renesas_of_match[] = {
0381     { .compatible = "renesas,r8a779f0-ufs" },
0382     { /* sentinel */ }
0383 };
0384 MODULE_DEVICE_TABLE(of, ufs_renesas_of_match);
0385
0386 static int ufs_renesas_probe(struct platform_device *pdev)
0387 {
0388     return ufshcd_pltfrm_init(pdev, &ufs_renesas_vops);
0389 }
0390
0391 static int ufs_renesas_remove(struct platform_device *pdev)
0392 {
0393     struct ufs_hba *hba = platform_get_drvdata(pdev);
0394
0395     ufshcd_remove(hba);
0396
0397     return 0;
0398 }
0399
0400 static struct platform_driver ufs_renesas_platform = {
0401     .probe  = ufs_renesas_probe,
0402     .remove = ufs_renesas_remove,
0403     .driver = {
0404         .name   = "ufshcd-renesas",
0405         .of_match_table = of_match_ptr(ufs_renesas_of_match),
0406     },
0407 };
0408 module_platform_driver(ufs_renesas_platform);
0409
0410 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
0411 MODULE_DESCRIPTION("Renesas UFS host controller driver");
0412 MODULE_LICENSE("Dual MIT/GPL");