ufs/host/ufs-qcom.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #ifndef UFS_QCOM_H_
0006 #define UFS_QCOM_H_
0007
0008 #include <linux/reset-controller.h>
0009 #include <linux/reset.h>
0010 #include <ufs/ufshcd.h>
0011
0012 #define MAX_UFS_QCOM_HOSTS  1
0013 #define MAX_U32                 (~(u32)0)
0014 #define MPHY_TX_FSM_STATE       0x41
0015 #define TX_FSM_HIBERN8          0x1
0016 #define HBRN8_POLL_TOUT_MS      100
0017 #define DEFAULT_CLK_RATE_HZ     1000000
0018 #define BUS_VECTOR_NAME_LEN     32
0019
0020 #define UFS_HW_VER_MAJOR_SHFT   (28)
0021 #define UFS_HW_VER_MAJOR_MASK   (0x000F << UFS_HW_VER_MAJOR_SHFT)
0022 #define UFS_HW_VER_MINOR_SHFT   (16)
0023 #define UFS_HW_VER_MINOR_MASK   (0x0FFF << UFS_HW_VER_MINOR_SHFT)
0024 #define UFS_HW_VER_STEP_SHFT    (0)
0025 #define UFS_HW_VER_STEP_MASK    (0xFFFF << UFS_HW_VER_STEP_SHFT)
0026
0027 /* vendor specific pre-defined parameters */
0028 #define SLOW 1
0029 #define FAST 2
0030
0031 #define UFS_QCOM_LIMIT_HS_RATE      PA_HS_MODE_B
0032
0033 /* QCOM UFS host controller vendor specific registers */
0034 enum {
0035     REG_UFS_SYS1CLK_1US                 = 0xC0,
0036     REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
0037     REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
0038     REG_UFS_PA_ERR_CODE                 = 0xCC,
0039     REG_UFS_RETRY_TIMER_REG             = 0xD0,
0040     REG_UFS_PA_LINK_STARTUP_TIMER       = 0xD8,
0041     REG_UFS_CFG1                        = 0xDC,
0042     REG_UFS_CFG2                        = 0xE0,
0043     REG_UFS_HW_VERSION                  = 0xE4,
0044
0045     UFS_TEST_BUS                = 0xE8,
0046     UFS_TEST_BUS_CTRL_0         = 0xEC,
0047     UFS_TEST_BUS_CTRL_1         = 0xF0,
0048     UFS_TEST_BUS_CTRL_2         = 0xF4,
0049     UFS_UNIPRO_CFG              = 0xF8,
0050
0051     /*
0052      * QCOM UFS host controller vendor specific registers
0053      * added in HW Version 3.0.0
0054      */
0055     UFS_AH8_CFG             = 0xFC,
0056 };
0057
0058 /* QCOM UFS host controller vendor specific debug registers */
0059 enum {
0060     UFS_DBG_RD_REG_UAWM         = 0x100,
0061     UFS_DBG_RD_REG_UARM         = 0x200,
0062     UFS_DBG_RD_REG_TXUC         = 0x300,
0063     UFS_DBG_RD_REG_RXUC         = 0x400,
0064     UFS_DBG_RD_REG_DFC          = 0x500,
0065     UFS_DBG_RD_REG_TRLUT            = 0x600,
0066     UFS_DBG_RD_REG_TMRLUT           = 0x700,
0067     UFS_UFS_DBG_RD_REG_OCSC         = 0x800,
0068
0069     UFS_UFS_DBG_RD_DESC_RAM         = 0x1500,
0070     UFS_UFS_DBG_RD_PRDT_RAM         = 0x1700,
0071     UFS_UFS_DBG_RD_RESP_RAM         = 0x1800,
0072     UFS_UFS_DBG_RD_EDTL_RAM         = 0x1900,
0073 };
0074
0075 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)  (0x000 + x)
0076 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)  (0x400 + x)
0077
0078 /* bit definitions for REG_UFS_CFG1 register */
0079 #define QUNIPRO_SEL     0x1
0080 #define UTP_DBG_RAMS_EN     0x20000
0081 #define TEST_BUS_EN     BIT(18)
0082 #define TEST_BUS_SEL        GENMASK(22, 19)
0083 #define UFS_REG_TEST_BUS_EN BIT(30)
0084
0085 /* bit definitions for REG_UFS_CFG2 register */
0086 #define UAWM_HW_CGC_EN      (1 << 0)
0087 #define UARM_HW_CGC_EN      (1 << 1)
0088 #define TXUC_HW_CGC_EN      (1 << 2)
0089 #define RXUC_HW_CGC_EN      (1 << 3)
0090 #define DFC_HW_CGC_EN       (1 << 4)
0091 #define TRLUT_HW_CGC_EN     (1 << 5)
0092 #define TMRLUT_HW_CGC_EN    (1 << 6)
0093 #define OCSC_HW_CGC_EN      (1 << 7)
0094
0095 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
0096 #define TEST_BUS_SUB_SEL_MASK   0x1F  /* All XXX_SEL fields are 5 bits wide */
0097
0098 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
0099                  TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
0100                  DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
0101                  TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
0102
0103 /* bit offset */
0104 enum {
0105     OFFSET_UFS_PHY_SOFT_RESET           = 1,
0106     OFFSET_CLK_NS_REG                   = 10,
0107 };
0108
0109 /* bit masks */
0110 enum {
0111     MASK_UFS_PHY_SOFT_RESET             = 0x2,
0112     MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
0113     MASK_CLK_NS_REG                     = 0xFFFC00,
0114 };
0115
0116 /* QCOM UFS debug print bit mask */
0117 #define UFS_QCOM_DBG_PRINT_REGS_EN  BIT(0)
0118 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN  BIT(1)
0119 #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN  BIT(2)
0120
0121 #define UFS_QCOM_DBG_PRINT_ALL  \
0122     (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
0123      UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
0124
0125 /* QUniPro Vendor specific attributes */
0126 #define PA_VS_CONFIG_REG1   0x9000
0127 #define DME_VS_CORE_CLK_CTRL    0xD002
0128 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
0129 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT        BIT(8)
0130 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK   0xFF
0131
0132 static inline void
0133 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
0134                  u8 *major, u16 *minor, u16 *step)
0135 {
0136     u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
0137
0138     *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
0139     *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
0140     *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
0141 };
0142
0143 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
0144 {
0145     ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
0146             1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
0147
0148     /*
0149      * Make sure assertion of ufs phy reset is written to
0150      * register before returning
0151      */
0152     mb();
0153 }
0154
0155 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
0156 {
0157     ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
0158             0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
0159
0160     /*
0161      * Make sure de-assertion of ufs phy reset is written to
0162      * register before returning
0163      */
0164     mb();
0165 }
0166
0167 /* Host controller hardware version: major.minor.step */
0168 struct ufs_hw_version {
0169     u16 step;
0170     u16 minor;
0171     u8 major;
0172 };
0173
0174 struct ufs_qcom_testbus {
0175     u8 select_major;
0176     u8 select_minor;
0177 };
0178
0179 struct gpio_desc;
0180
0181 struct ufs_qcom_host {
0182     /*
0183      * Set this capability if host controller supports the QUniPro mode
0184      * and if driver wants the Host controller to operate in QUniPro mode.
0185      * Note: By default this capability will be kept enabled if host
0186      * controller supports the QUniPro mode.
0187      */
0188     #define UFS_QCOM_CAP_QUNIPRO    0x1
0189
0190     /*
0191      * Set this capability if host controller can retain the secure
0192      * configuration even after UFS controller core power collapse.
0193      */
0194     #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE  0x2
0195     u32 caps;
0196
0197     struct phy *generic_phy;
0198     struct ufs_hba *hba;
0199     struct ufs_pa_layer_attr dev_req_params;
0200     struct clk *rx_l0_sync_clk;
0201     struct clk *tx_l0_sync_clk;
0202     struct clk *rx_l1_sync_clk;
0203     struct clk *tx_l1_sync_clk;
0204     bool is_lane_clks_enabled;
0205
0206     void __iomem *dev_ref_clk_ctrl_mmio;
0207     bool is_dev_ref_clk_enabled;
0208     struct ufs_hw_version hw_ver;
0209 #ifdef CONFIG_SCSI_UFS_CRYPTO
0210     void __iomem *ice_mmio;
0211 #endif
0212
0213     u32 dev_ref_clk_en_mask;
0214
0215     /* Bitmask for enabling debug prints */
0216     u32 dbg_print_en;
0217     struct ufs_qcom_testbus testbus;
0218
0219     /* Reset control of HCI */
0220     struct reset_control *core_reset;
0221     struct reset_controller_dev rcdev;
0222
0223     struct gpio_desc *device_reset;
0224 };
0225
0226 static inline u32
0227 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
0228 {
0229     if (host->hw_ver.major <= 0x02)
0230         return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
0231
0232     return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
0233 };
0234
0235 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
0236 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
0237 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
0238
0239 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
0240
0241 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
0242 {
0243     return host->caps & UFS_QCOM_CAP_QUNIPRO;
0244 }
0245
0246 /* ufs-qcom-ice.c */
0247
0248 #ifdef CONFIG_SCSI_UFS_CRYPTO
0249 int ufs_qcom_ice_init(struct ufs_qcom_host *host);
0250 int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
0251 int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
0252 int ufs_qcom_ice_program_key(struct ufs_hba *hba,
0253                  const union ufs_crypto_cfg_entry *cfg, int slot);
0254 #else
0255 static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
0256 {
0257     return 0;
0258 }
0259 static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
0260 {
0261     return 0;
0262 }
0263 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
0264 {
0265     return 0;
0266 }
0267 #define ufs_qcom_ice_program_key NULL
0268 #endif /* !CONFIG_SCSI_UFS_CRYPTO */
0269
0270 #endif /* UFS_QCOM_H_ */