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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/acpi.h>
0007 #include <linux/time.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/phy/phy.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/reset-controller.h>
0016 #include <linux/devfreq.h>
0017 
0018 #include <ufs/ufshcd.h>
0019 #include "ufshcd-pltfrm.h"
0020 #include <ufs/unipro.h>
0021 #include "ufs-qcom.h"
0022 #include <ufs/ufshci.h>
0023 #include <ufs/ufs_quirks.h>
0024 
0025 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
0026     (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
0027 
0028 enum {
0029     TSTBUS_UAWM,
0030     TSTBUS_UARM,
0031     TSTBUS_TXUC,
0032     TSTBUS_RXUC,
0033     TSTBUS_DFC,
0034     TSTBUS_TRLUT,
0035     TSTBUS_TMRLUT,
0036     TSTBUS_OCSC,
0037     TSTBUS_UTP_HCI,
0038     TSTBUS_COMBINED,
0039     TSTBUS_WRAPPER,
0040     TSTBUS_UNIPRO,
0041     TSTBUS_MAX,
0042 };
0043 
0044 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
0045 
0046 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
0047 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
0048                                u32 clk_cycles);
0049 
0050 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
0051 {
0052     return container_of(rcd, struct ufs_qcom_host, rcdev);
0053 }
0054 
0055 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
0056                        const char *prefix, void *priv)
0057 {
0058     ufshcd_dump_regs(hba, offset, len * 4, prefix);
0059 }
0060 
0061 static int ufs_qcom_host_clk_get(struct device *dev,
0062         const char *name, struct clk **clk_out, bool optional)
0063 {
0064     struct clk *clk;
0065     int err = 0;
0066 
0067     clk = devm_clk_get(dev, name);
0068     if (!IS_ERR(clk)) {
0069         *clk_out = clk;
0070         return 0;
0071     }
0072 
0073     err = PTR_ERR(clk);
0074 
0075     if (optional && err == -ENOENT) {
0076         *clk_out = NULL;
0077         return 0;
0078     }
0079 
0080     if (err != -EPROBE_DEFER)
0081         dev_err(dev, "failed to get %s err %d\n", name, err);
0082 
0083     return err;
0084 }
0085 
0086 static int ufs_qcom_host_clk_enable(struct device *dev,
0087         const char *name, struct clk *clk)
0088 {
0089     int err = 0;
0090 
0091     err = clk_prepare_enable(clk);
0092     if (err)
0093         dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
0094 
0095     return err;
0096 }
0097 
0098 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
0099 {
0100     if (!host->is_lane_clks_enabled)
0101         return;
0102 
0103     clk_disable_unprepare(host->tx_l1_sync_clk);
0104     clk_disable_unprepare(host->tx_l0_sync_clk);
0105     clk_disable_unprepare(host->rx_l1_sync_clk);
0106     clk_disable_unprepare(host->rx_l0_sync_clk);
0107 
0108     host->is_lane_clks_enabled = false;
0109 }
0110 
0111 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
0112 {
0113     int err = 0;
0114     struct device *dev = host->hba->dev;
0115 
0116     if (host->is_lane_clks_enabled)
0117         return 0;
0118 
0119     err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
0120         host->rx_l0_sync_clk);
0121     if (err)
0122         goto out;
0123 
0124     err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
0125         host->tx_l0_sync_clk);
0126     if (err)
0127         goto disable_rx_l0;
0128 
0129     err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
0130             host->rx_l1_sync_clk);
0131     if (err)
0132         goto disable_tx_l0;
0133 
0134     err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
0135             host->tx_l1_sync_clk);
0136     if (err)
0137         goto disable_rx_l1;
0138 
0139     host->is_lane_clks_enabled = true;
0140     goto out;
0141 
0142 disable_rx_l1:
0143     clk_disable_unprepare(host->rx_l1_sync_clk);
0144 disable_tx_l0:
0145     clk_disable_unprepare(host->tx_l0_sync_clk);
0146 disable_rx_l0:
0147     clk_disable_unprepare(host->rx_l0_sync_clk);
0148 out:
0149     return err;
0150 }
0151 
0152 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
0153 {
0154     int err = 0;
0155     struct device *dev = host->hba->dev;
0156 
0157     if (has_acpi_companion(dev))
0158         return 0;
0159 
0160     err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
0161                     &host->rx_l0_sync_clk, false);
0162     if (err)
0163         goto out;
0164 
0165     err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
0166                     &host->tx_l0_sync_clk, false);
0167     if (err)
0168         goto out;
0169 
0170     /* In case of single lane per direction, don't read lane1 clocks */
0171     if (host->hba->lanes_per_direction > 1) {
0172         err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
0173             &host->rx_l1_sync_clk, false);
0174         if (err)
0175             goto out;
0176 
0177         err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
0178             &host->tx_l1_sync_clk, true);
0179     }
0180 out:
0181     return err;
0182 }
0183 
0184 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
0185 {
0186     int err;
0187     u32 tx_fsm_val = 0;
0188     unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
0189 
0190     do {
0191         err = ufshcd_dme_get(hba,
0192                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
0193                     UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
0194                 &tx_fsm_val);
0195         if (err || tx_fsm_val == TX_FSM_HIBERN8)
0196             break;
0197 
0198         /* sleep for max. 200us */
0199         usleep_range(100, 200);
0200     } while (time_before(jiffies, timeout));
0201 
0202     /*
0203      * we might have scheduled out for long during polling so
0204      * check the state again.
0205      */
0206     if (time_after(jiffies, timeout))
0207         err = ufshcd_dme_get(hba,
0208                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
0209                     UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
0210                 &tx_fsm_val);
0211 
0212     if (err) {
0213         dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
0214                 __func__, err);
0215     } else if (tx_fsm_val != TX_FSM_HIBERN8) {
0216         err = tx_fsm_val;
0217         dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
0218                 __func__, err);
0219     }
0220 
0221     return err;
0222 }
0223 
0224 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
0225 {
0226     ufshcd_rmwl(host->hba, QUNIPRO_SEL,
0227            ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
0228            REG_UFS_CFG1);
0229     /* make sure above configuration is applied before we return */
0230     mb();
0231 }
0232 
0233 /*
0234  * ufs_qcom_host_reset - reset host controller and PHY
0235  */
0236 static int ufs_qcom_host_reset(struct ufs_hba *hba)
0237 {
0238     int ret = 0;
0239     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0240     bool reenable_intr = false;
0241 
0242     if (!host->core_reset) {
0243         dev_warn(hba->dev, "%s: reset control not set\n", __func__);
0244         goto out;
0245     }
0246 
0247     reenable_intr = hba->is_irq_enabled;
0248     disable_irq(hba->irq);
0249     hba->is_irq_enabled = false;
0250 
0251     ret = reset_control_assert(host->core_reset);
0252     if (ret) {
0253         dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
0254                  __func__, ret);
0255         goto out;
0256     }
0257 
0258     /*
0259      * The hardware requirement for delay between assert/deassert
0260      * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
0261      * ~125us (4/32768). To be on the safe side add 200us delay.
0262      */
0263     usleep_range(200, 210);
0264 
0265     ret = reset_control_deassert(host->core_reset);
0266     if (ret)
0267         dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
0268                  __func__, ret);
0269 
0270     usleep_range(1000, 1100);
0271 
0272     if (reenable_intr) {
0273         enable_irq(hba->irq);
0274         hba->is_irq_enabled = true;
0275     }
0276 
0277 out:
0278     return ret;
0279 }
0280 
0281 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
0282 {
0283     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0284     struct phy *phy = host->generic_phy;
0285     int ret = 0;
0286     bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
0287 
0288     /* Reset UFS Host Controller and PHY */
0289     ret = ufs_qcom_host_reset(hba);
0290     if (ret)
0291         dev_warn(hba->dev, "%s: host reset returned %d\n",
0292                   __func__, ret);
0293 
0294     if (is_rate_B)
0295         phy_set_mode(phy, PHY_MODE_UFS_HS_B);
0296 
0297     /* phy initialization - calibrate the phy */
0298     ret = phy_init(phy);
0299     if (ret) {
0300         dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
0301             __func__, ret);
0302         goto out;
0303     }
0304 
0305     /* power on phy - start serdes and phy's power and clocks */
0306     ret = phy_power_on(phy);
0307     if (ret) {
0308         dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
0309             __func__, ret);
0310         goto out_disable_phy;
0311     }
0312 
0313     ufs_qcom_select_unipro_mode(host);
0314 
0315     return 0;
0316 
0317 out_disable_phy:
0318     phy_exit(phy);
0319 out:
0320     return ret;
0321 }
0322 
0323 /*
0324  * The UTP controller has a number of internal clock gating cells (CGCs).
0325  * Internal hardware sub-modules within the UTP controller control the CGCs.
0326  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
0327  * in a specific operation, UTP controller CGCs are by default disabled and
0328  * this function enables them (after every UFS link startup) to save some power
0329  * leakage.
0330  */
0331 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
0332 {
0333     ufshcd_writel(hba,
0334         ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
0335         REG_UFS_CFG2);
0336 
0337     /* Ensure that HW clock gating is enabled before next operations */
0338     mb();
0339 }
0340 
0341 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
0342                       enum ufs_notify_change_status status)
0343 {
0344     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0345     int err = 0;
0346 
0347     switch (status) {
0348     case PRE_CHANGE:
0349         ufs_qcom_power_up_sequence(hba);
0350         /*
0351          * The PHY PLL output is the source of tx/rx lane symbol
0352          * clocks, hence, enable the lane clocks only after PHY
0353          * is initialized.
0354          */
0355         err = ufs_qcom_enable_lane_clks(host);
0356         break;
0357     case POST_CHANGE:
0358         /* check if UFS PHY moved from DISABLED to HIBERN8 */
0359         err = ufs_qcom_check_hibern8(hba);
0360         ufs_qcom_enable_hw_clk_gating(hba);
0361         ufs_qcom_ice_enable(host);
0362         break;
0363     default:
0364         dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
0365         err = -EINVAL;
0366         break;
0367     }
0368     return err;
0369 }
0370 
0371 /*
0372  * Returns zero for success and non-zero in case of a failure
0373  */
0374 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
0375                    u32 hs, u32 rate, bool update_link_startup_timer)
0376 {
0377     int ret = 0;
0378     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0379     struct ufs_clk_info *clki;
0380     u32 core_clk_period_in_ns;
0381     u32 tx_clk_cycles_per_us = 0;
0382     unsigned long core_clk_rate = 0;
0383     u32 core_clk_cycles_per_us = 0;
0384 
0385     static u32 pwm_fr_table[][2] = {
0386         {UFS_PWM_G1, 0x1},
0387         {UFS_PWM_G2, 0x1},
0388         {UFS_PWM_G3, 0x1},
0389         {UFS_PWM_G4, 0x1},
0390     };
0391 
0392     static u32 hs_fr_table_rA[][2] = {
0393         {UFS_HS_G1, 0x1F},
0394         {UFS_HS_G2, 0x3e},
0395         {UFS_HS_G3, 0x7D},
0396     };
0397 
0398     static u32 hs_fr_table_rB[][2] = {
0399         {UFS_HS_G1, 0x24},
0400         {UFS_HS_G2, 0x49},
0401         {UFS_HS_G3, 0x92},
0402     };
0403 
0404     /*
0405      * The Qunipro controller does not use following registers:
0406      * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
0407      * UFS_REG_PA_LINK_STARTUP_TIMER
0408      * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
0409      * Aggregation logic.
0410     */
0411     if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
0412         goto out;
0413 
0414     if (gear == 0) {
0415         dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
0416         goto out_error;
0417     }
0418 
0419     list_for_each_entry(clki, &hba->clk_list_head, list) {
0420         if (!strcmp(clki->name, "core_clk"))
0421             core_clk_rate = clk_get_rate(clki->clk);
0422     }
0423 
0424     /* If frequency is smaller than 1MHz, set to 1MHz */
0425     if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
0426         core_clk_rate = DEFAULT_CLK_RATE_HZ;
0427 
0428     core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
0429     if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
0430         ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
0431         /*
0432          * make sure above write gets applied before we return from
0433          * this function.
0434          */
0435         mb();
0436     }
0437 
0438     if (ufs_qcom_cap_qunipro(host))
0439         goto out;
0440 
0441     core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
0442     core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
0443     core_clk_period_in_ns &= MASK_CLK_NS_REG;
0444 
0445     switch (hs) {
0446     case FASTAUTO_MODE:
0447     case FAST_MODE:
0448         if (rate == PA_HS_MODE_A) {
0449             if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
0450                 dev_err(hba->dev,
0451                     "%s: index %d exceeds table size %zu\n",
0452                     __func__, gear,
0453                     ARRAY_SIZE(hs_fr_table_rA));
0454                 goto out_error;
0455             }
0456             tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
0457         } else if (rate == PA_HS_MODE_B) {
0458             if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
0459                 dev_err(hba->dev,
0460                     "%s: index %d exceeds table size %zu\n",
0461                     __func__, gear,
0462                     ARRAY_SIZE(hs_fr_table_rB));
0463                 goto out_error;
0464             }
0465             tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
0466         } else {
0467             dev_err(hba->dev, "%s: invalid rate = %d\n",
0468                 __func__, rate);
0469             goto out_error;
0470         }
0471         break;
0472     case SLOWAUTO_MODE:
0473     case SLOW_MODE:
0474         if (gear > ARRAY_SIZE(pwm_fr_table)) {
0475             dev_err(hba->dev,
0476                     "%s: index %d exceeds table size %zu\n",
0477                     __func__, gear,
0478                     ARRAY_SIZE(pwm_fr_table));
0479             goto out_error;
0480         }
0481         tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
0482         break;
0483     case UNCHANGED:
0484     default:
0485         dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
0486         goto out_error;
0487     }
0488 
0489     if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
0490         (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
0491         /* this register 2 fields shall be written at once */
0492         ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
0493                   REG_UFS_TX_SYMBOL_CLK_NS_US);
0494         /*
0495          * make sure above write gets applied before we return from
0496          * this function.
0497          */
0498         mb();
0499     }
0500 
0501     if (update_link_startup_timer) {
0502         ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
0503                   REG_UFS_PA_LINK_STARTUP_TIMER);
0504         /*
0505          * make sure that this configuration is applied before
0506          * we return
0507          */
0508         mb();
0509     }
0510     goto out;
0511 
0512 out_error:
0513     ret = -EINVAL;
0514 out:
0515     return ret;
0516 }
0517 
0518 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
0519                     enum ufs_notify_change_status status)
0520 {
0521     int err = 0;
0522     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0523 
0524     switch (status) {
0525     case PRE_CHANGE:
0526         if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
0527                     0, true)) {
0528             dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
0529                 __func__);
0530             err = -EINVAL;
0531             goto out;
0532         }
0533 
0534         if (ufs_qcom_cap_qunipro(host))
0535             /*
0536              * set unipro core clock cycles to 150 & clear clock
0537              * divider
0538              */
0539             err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
0540                                       150);
0541 
0542         /*
0543          * Some UFS devices (and may be host) have issues if LCC is
0544          * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
0545          * before link startup which will make sure that both host
0546          * and device TX LCC are disabled once link startup is
0547          * completed.
0548          */
0549         if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
0550             err = ufshcd_disable_host_tx_lcc(hba);
0551 
0552         break;
0553     default:
0554         break;
0555     }
0556 
0557 out:
0558     return err;
0559 }
0560 
0561 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
0562 {
0563     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0564 
0565     /* reset gpio is optional */
0566     if (!host->device_reset)
0567         return;
0568 
0569     gpiod_set_value_cansleep(host->device_reset, asserted);
0570 }
0571 
0572 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
0573     enum ufs_notify_change_status status)
0574 {
0575     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0576     struct phy *phy = host->generic_phy;
0577 
0578     if (status == PRE_CHANGE)
0579         return 0;
0580 
0581     if (ufs_qcom_is_link_off(hba)) {
0582         /*
0583          * Disable the tx/rx lane symbol clocks before PHY is
0584          * powered down as the PLL source should be disabled
0585          * after downstream clocks are disabled.
0586          */
0587         ufs_qcom_disable_lane_clks(host);
0588         phy_power_off(phy);
0589 
0590         /* reset the connected UFS device during power down */
0591         ufs_qcom_device_reset_ctrl(hba, true);
0592 
0593     } else if (!ufs_qcom_is_link_active(hba)) {
0594         ufs_qcom_disable_lane_clks(host);
0595     }
0596 
0597     return 0;
0598 }
0599 
0600 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
0601 {
0602     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0603     struct phy *phy = host->generic_phy;
0604     int err;
0605 
0606     if (ufs_qcom_is_link_off(hba)) {
0607         err = phy_power_on(phy);
0608         if (err) {
0609             dev_err(hba->dev, "%s: failed PHY power on: %d\n",
0610                 __func__, err);
0611             return err;
0612         }
0613 
0614         err = ufs_qcom_enable_lane_clks(host);
0615         if (err)
0616             return err;
0617 
0618     } else if (!ufs_qcom_is_link_active(hba)) {
0619         err = ufs_qcom_enable_lane_clks(host);
0620         if (err)
0621             return err;
0622     }
0623 
0624     return ufs_qcom_ice_resume(host);
0625 }
0626 
0627 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
0628 {
0629     if (host->dev_ref_clk_ctrl_mmio &&
0630         (enable ^ host->is_dev_ref_clk_enabled)) {
0631         u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
0632 
0633         if (enable)
0634             temp |= host->dev_ref_clk_en_mask;
0635         else
0636             temp &= ~host->dev_ref_clk_en_mask;
0637 
0638         /*
0639          * If we are here to disable this clock it might be immediately
0640          * after entering into hibern8 in which case we need to make
0641          * sure that device ref_clk is active for specific time after
0642          * hibern8 enter.
0643          */
0644         if (!enable) {
0645             unsigned long gating_wait;
0646 
0647             gating_wait = host->hba->dev_info.clk_gating_wait_us;
0648             if (!gating_wait) {
0649                 udelay(1);
0650             } else {
0651                 /*
0652                  * bRefClkGatingWaitTime defines the minimum
0653                  * time for which the reference clock is
0654                  * required by device during transition from
0655                  * HS-MODE to LS-MODE or HIBERN8 state. Give it
0656                  * more delay to be on the safe side.
0657                  */
0658                 gating_wait += 10;
0659                 usleep_range(gating_wait, gating_wait + 10);
0660             }
0661         }
0662 
0663         writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
0664 
0665         /*
0666          * Make sure the write to ref_clk reaches the destination and
0667          * not stored in a Write Buffer (WB).
0668          */
0669         readl(host->dev_ref_clk_ctrl_mmio);
0670 
0671         /*
0672          * If we call hibern8 exit after this, we need to make sure that
0673          * device ref_clk is stable for at least 1us before the hibern8
0674          * exit command.
0675          */
0676         if (enable)
0677             udelay(1);
0678 
0679         host->is_dev_ref_clk_enabled = enable;
0680     }
0681 }
0682 
0683 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
0684                 enum ufs_notify_change_status status,
0685                 struct ufs_pa_layer_attr *dev_max_params,
0686                 struct ufs_pa_layer_attr *dev_req_params)
0687 {
0688     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0689     struct ufs_dev_params ufs_qcom_cap;
0690     int ret = 0;
0691 
0692     if (!dev_req_params) {
0693         pr_err("%s: incoming dev_req_params is NULL\n", __func__);
0694         ret = -EINVAL;
0695         goto out;
0696     }
0697 
0698     switch (status) {
0699     case PRE_CHANGE:
0700         ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
0701         ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
0702 
0703         if (host->hw_ver.major == 0x1) {
0704             /*
0705              * HS-G3 operations may not reliably work on legacy QCOM
0706              * UFS host controller hardware even though capability
0707              * exchange during link startup phase may end up
0708              * negotiating maximum supported gear as G3.
0709              * Hence downgrade the maximum supported gear to HS-G2.
0710              */
0711             if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
0712                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
0713             if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
0714                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
0715         }
0716 
0717         ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
0718                            dev_max_params,
0719                            dev_req_params);
0720         if (ret) {
0721             pr_err("%s: failed to determine capabilities\n",
0722                     __func__);
0723             goto out;
0724         }
0725 
0726         /* enable the device ref clock before changing to HS mode */
0727         if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
0728             ufshcd_is_hs_mode(dev_req_params))
0729             ufs_qcom_dev_ref_clk_ctrl(host, true);
0730 
0731         if (host->hw_ver.major >= 0x4) {
0732             ufshcd_dme_configure_adapt(hba,
0733                         dev_req_params->gear_tx,
0734                         PA_INITIAL_ADAPT);
0735         }
0736         break;
0737     case POST_CHANGE:
0738         if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
0739                     dev_req_params->pwr_rx,
0740                     dev_req_params->hs_rate, false)) {
0741             dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
0742                 __func__);
0743             /*
0744              * we return error code at the end of the routine,
0745              * but continue to configure UFS_PHY_TX_LANE_ENABLE
0746              * and bus voting as usual
0747              */
0748             ret = -EINVAL;
0749         }
0750 
0751         /* cache the power mode parameters to use internally */
0752         memcpy(&host->dev_req_params,
0753                 dev_req_params, sizeof(*dev_req_params));
0754 
0755         /* disable the device ref clock if entered PWM mode */
0756         if (ufshcd_is_hs_mode(&hba->pwr_info) &&
0757             !ufshcd_is_hs_mode(dev_req_params))
0758             ufs_qcom_dev_ref_clk_ctrl(host, false);
0759         break;
0760     default:
0761         ret = -EINVAL;
0762         break;
0763     }
0764 out:
0765     return ret;
0766 }
0767 
0768 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
0769 {
0770     int err;
0771     u32 pa_vs_config_reg1;
0772 
0773     err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
0774                  &pa_vs_config_reg1);
0775     if (err)
0776         goto out;
0777 
0778     /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
0779     err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
0780                 (pa_vs_config_reg1 | (1 << 12)));
0781 
0782 out:
0783     return err;
0784 }
0785 
0786 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
0787 {
0788     int err = 0;
0789 
0790     if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
0791         err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
0792 
0793     if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
0794         hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
0795 
0796     return err;
0797 }
0798 
0799 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
0800 {
0801     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0802 
0803     if (host->hw_ver.major == 0x1)
0804         return ufshci_version(1, 1);
0805     else
0806         return ufshci_version(2, 0);
0807 }
0808 
0809 /**
0810  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
0811  * @hba: host controller instance
0812  *
0813  * QCOM UFS host controller might have some non standard behaviours (quirks)
0814  * than what is specified by UFSHCI specification. Advertise all such
0815  * quirks to standard UFS host controller driver so standard takes them into
0816  * account.
0817  */
0818 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
0819 {
0820     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0821 
0822     if (host->hw_ver.major == 0x01) {
0823         hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
0824                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
0825                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
0826 
0827         if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
0828             hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
0829 
0830         hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
0831     }
0832 
0833     if (host->hw_ver.major == 0x2) {
0834         hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
0835 
0836         if (!ufs_qcom_cap_qunipro(host))
0837             /* Legacy UniPro mode still need following quirks */
0838             hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
0839                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
0840                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
0841     }
0842 }
0843 
0844 static void ufs_qcom_set_caps(struct ufs_hba *hba)
0845 {
0846     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0847 
0848     hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
0849     hba->caps |= UFSHCD_CAP_CLK_SCALING;
0850     hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
0851     hba->caps |= UFSHCD_CAP_WB_EN;
0852     hba->caps |= UFSHCD_CAP_CRYPTO;
0853     hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
0854     hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
0855 
0856     if (host->hw_ver.major >= 0x2) {
0857         host->caps = UFS_QCOM_CAP_QUNIPRO |
0858                  UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
0859     }
0860 }
0861 
0862 /**
0863  * ufs_qcom_setup_clocks - enables/disable clocks
0864  * @hba: host controller instance
0865  * @on: If true, enable clocks else disable them.
0866  * @status: PRE_CHANGE or POST_CHANGE notify
0867  *
0868  * Returns 0 on success, non-zero on failure.
0869  */
0870 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
0871                  enum ufs_notify_change_status status)
0872 {
0873     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
0874 
0875     /*
0876      * In case ufs_qcom_init() is not yet done, simply ignore.
0877      * This ufs_qcom_setup_clocks() shall be called from
0878      * ufs_qcom_init() after init is done.
0879      */
0880     if (!host)
0881         return 0;
0882 
0883     switch (status) {
0884     case PRE_CHANGE:
0885         if (!on) {
0886             if (!ufs_qcom_is_link_active(hba)) {
0887                 /* disable device ref_clk */
0888                 ufs_qcom_dev_ref_clk_ctrl(host, false);
0889             }
0890         }
0891         break;
0892     case POST_CHANGE:
0893         if (on) {
0894             /* enable the device ref clock for HS mode*/
0895             if (ufshcd_is_hs_mode(&hba->pwr_info))
0896                 ufs_qcom_dev_ref_clk_ctrl(host, true);
0897         }
0898         break;
0899     }
0900 
0901     return 0;
0902 }
0903 
0904 static int
0905 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
0906 {
0907     struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
0908 
0909     /* Currently this code only knows about a single reset. */
0910     WARN_ON(id);
0911     ufs_qcom_assert_reset(host->hba);
0912     /* provide 1ms delay to let the reset pulse propagate. */
0913     usleep_range(1000, 1100);
0914     return 0;
0915 }
0916 
0917 static int
0918 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
0919 {
0920     struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
0921 
0922     /* Currently this code only knows about a single reset. */
0923     WARN_ON(id);
0924     ufs_qcom_deassert_reset(host->hba);
0925 
0926     /*
0927      * after reset deassertion, phy will need all ref clocks,
0928      * voltage, current to settle down before starting serdes.
0929      */
0930     usleep_range(1000, 1100);
0931     return 0;
0932 }
0933 
0934 static const struct reset_control_ops ufs_qcom_reset_ops = {
0935     .assert = ufs_qcom_reset_assert,
0936     .deassert = ufs_qcom_reset_deassert,
0937 };
0938 
0939 /**
0940  * ufs_qcom_init - bind phy with controller
0941  * @hba: host controller instance
0942  *
0943  * Binds PHY with controller and powers up PHY enabling clocks
0944  * and regulators.
0945  *
0946  * Returns -EPROBE_DEFER if binding fails, returns negative error
0947  * on phy power up failure and returns zero on success.
0948  */
0949 static int ufs_qcom_init(struct ufs_hba *hba)
0950 {
0951     int err;
0952     struct device *dev = hba->dev;
0953     struct platform_device *pdev = to_platform_device(dev);
0954     struct ufs_qcom_host *host;
0955     struct resource *res;
0956     struct ufs_clk_info *clki;
0957 
0958     host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
0959     if (!host) {
0960         err = -ENOMEM;
0961         dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
0962         goto out;
0963     }
0964 
0965     /* Make a two way bind between the qcom host and the hba */
0966     host->hba = hba;
0967     ufshcd_set_variant(hba, host);
0968 
0969     /* Setup the optional reset control of HCI */
0970     host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
0971     if (IS_ERR(host->core_reset)) {
0972         err = dev_err_probe(dev, PTR_ERR(host->core_reset),
0973                     "Failed to get reset control\n");
0974         goto out_variant_clear;
0975     }
0976 
0977     /* Fire up the reset controller. Failure here is non-fatal. */
0978     host->rcdev.of_node = dev->of_node;
0979     host->rcdev.ops = &ufs_qcom_reset_ops;
0980     host->rcdev.owner = dev->driver->owner;
0981     host->rcdev.nr_resets = 1;
0982     err = devm_reset_controller_register(dev, &host->rcdev);
0983     if (err) {
0984         dev_warn(dev, "Failed to register reset controller\n");
0985         err = 0;
0986     }
0987 
0988     if (!has_acpi_companion(dev)) {
0989         host->generic_phy = devm_phy_get(dev, "ufsphy");
0990         if (IS_ERR(host->generic_phy)) {
0991             err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
0992             goto out_variant_clear;
0993         }
0994     }
0995 
0996     host->device_reset = devm_gpiod_get_optional(dev, "reset",
0997                              GPIOD_OUT_HIGH);
0998     if (IS_ERR(host->device_reset)) {
0999         err = PTR_ERR(host->device_reset);
1000         if (err != -EPROBE_DEFER)
1001             dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1002         goto out_variant_clear;
1003     }
1004 
1005     ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1006         &host->hw_ver.minor, &host->hw_ver.step);
1007 
1008     /*
1009      * for newer controllers, device reference clock control bit has
1010      * moved inside UFS controller register address space itself.
1011      */
1012     if (host->hw_ver.major >= 0x02) {
1013         host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1014         host->dev_ref_clk_en_mask = BIT(26);
1015     } else {
1016         /* "dev_ref_clk_ctrl_mem" is optional resource */
1017         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1018                            "dev_ref_clk_ctrl_mem");
1019         if (res) {
1020             host->dev_ref_clk_ctrl_mmio =
1021                     devm_ioremap_resource(dev, res);
1022             if (IS_ERR(host->dev_ref_clk_ctrl_mmio))
1023                 host->dev_ref_clk_ctrl_mmio = NULL;
1024             host->dev_ref_clk_en_mask = BIT(5);
1025         }
1026     }
1027 
1028     list_for_each_entry(clki, &hba->clk_list_head, list) {
1029         if (!strcmp(clki->name, "core_clk_unipro"))
1030             clki->keep_link_active = true;
1031     }
1032 
1033     err = ufs_qcom_init_lane_clks(host);
1034     if (err)
1035         goto out_variant_clear;
1036 
1037     ufs_qcom_set_caps(hba);
1038     ufs_qcom_advertise_quirks(hba);
1039 
1040     err = ufs_qcom_ice_init(host);
1041     if (err)
1042         goto out_variant_clear;
1043 
1044     ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1045 
1046     if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1047         ufs_qcom_hosts[hba->dev->id] = host;
1048 
1049     host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1050     ufs_qcom_get_default_testbus_cfg(host);
1051     err = ufs_qcom_testbus_config(host);
1052     if (err) {
1053         dev_warn(dev, "%s: failed to configure the testbus %d\n",
1054                 __func__, err);
1055         err = 0;
1056     }
1057 
1058     goto out;
1059 
1060 out_variant_clear:
1061     ufshcd_set_variant(hba, NULL);
1062 out:
1063     return err;
1064 }
1065 
1066 static void ufs_qcom_exit(struct ufs_hba *hba)
1067 {
1068     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1069 
1070     ufs_qcom_disable_lane_clks(host);
1071     phy_power_off(host->generic_phy);
1072     phy_exit(host->generic_phy);
1073 }
1074 
1075 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1076                                u32 clk_cycles)
1077 {
1078     int err;
1079     u32 core_clk_ctrl_reg;
1080 
1081     if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1082         return -EINVAL;
1083 
1084     err = ufshcd_dme_get(hba,
1085                 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1086                 &core_clk_ctrl_reg);
1087     if (err)
1088         goto out;
1089 
1090     core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1091     core_clk_ctrl_reg |= clk_cycles;
1092 
1093     /* Clear CORE_CLK_DIV_EN */
1094     core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1095 
1096     err = ufshcd_dme_set(hba,
1097                 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1098                 core_clk_ctrl_reg);
1099 out:
1100     return err;
1101 }
1102 
1103 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1104 {
1105     /* nothing to do as of now */
1106     return 0;
1107 }
1108 
1109 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1110 {
1111     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1112 
1113     if (!ufs_qcom_cap_qunipro(host))
1114         return 0;
1115 
1116     /* set unipro core clock cycles to 150 and clear clock divider */
1117     return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1118 }
1119 
1120 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1121 {
1122     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1123     int err;
1124     u32 core_clk_ctrl_reg;
1125 
1126     if (!ufs_qcom_cap_qunipro(host))
1127         return 0;
1128 
1129     err = ufshcd_dme_get(hba,
1130                 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1131                 &core_clk_ctrl_reg);
1132 
1133     /* make sure CORE_CLK_DIV_EN is cleared */
1134     if (!err &&
1135         (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1136         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1137         err = ufshcd_dme_set(hba,
1138                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1139                     core_clk_ctrl_reg);
1140     }
1141 
1142     return err;
1143 }
1144 
1145 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1146 {
1147     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1148 
1149     if (!ufs_qcom_cap_qunipro(host))
1150         return 0;
1151 
1152     /* set unipro core clock cycles to 75 and clear clock divider */
1153     return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1154 }
1155 
1156 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1157         bool scale_up, enum ufs_notify_change_status status)
1158 {
1159     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1160     struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1161     int err = 0;
1162 
1163     if (status == PRE_CHANGE) {
1164         err = ufshcd_uic_hibern8_enter(hba);
1165         if (err)
1166             return err;
1167         if (scale_up)
1168             err = ufs_qcom_clk_scale_up_pre_change(hba);
1169         else
1170             err = ufs_qcom_clk_scale_down_pre_change(hba);
1171         if (err)
1172             ufshcd_uic_hibern8_exit(hba);
1173 
1174     } else {
1175         if (scale_up)
1176             err = ufs_qcom_clk_scale_up_post_change(hba);
1177         else
1178             err = ufs_qcom_clk_scale_down_post_change(hba);
1179 
1180 
1181         if (err || !dev_req_params) {
1182             ufshcd_uic_hibern8_exit(hba);
1183             goto out;
1184         }
1185 
1186         ufs_qcom_cfg_timers(hba,
1187                     dev_req_params->gear_rx,
1188                     dev_req_params->pwr_rx,
1189                     dev_req_params->hs_rate,
1190                     false);
1191         ufshcd_uic_hibern8_exit(hba);
1192     }
1193 
1194 out:
1195     return err;
1196 }
1197 
1198 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1199         void *priv, void (*print_fn)(struct ufs_hba *hba,
1200         int offset, int num_regs, const char *str, void *priv))
1201 {
1202     u32 reg;
1203     struct ufs_qcom_host *host;
1204 
1205     if (unlikely(!hba)) {
1206         pr_err("%s: hba is NULL\n", __func__);
1207         return;
1208     }
1209     if (unlikely(!print_fn)) {
1210         dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1211         return;
1212     }
1213 
1214     host = ufshcd_get_variant(hba);
1215     if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1216         return;
1217 
1218     reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1219     print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1220 
1221     reg = ufshcd_readl(hba, REG_UFS_CFG1);
1222     reg |= UTP_DBG_RAMS_EN;
1223     ufshcd_writel(hba, reg, REG_UFS_CFG1);
1224 
1225     reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1226     print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1227 
1228     reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1229     print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1230 
1231     reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1232     print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1233 
1234     /* clear bit 17 - UTP_DBG_RAMS_EN */
1235     ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1236 
1237     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1238     print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1239 
1240     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1241     print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1242 
1243     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1244     print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1245 
1246     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1247     print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1248 
1249     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1250     print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1251 
1252     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1253     print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1254 
1255     reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1256     print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1257 }
1258 
1259 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1260 {
1261     if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1262         ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1263                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1264         ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1265     } else {
1266         ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1267         ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1268     }
1269 }
1270 
1271 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1272 {
1273     /* provide a legal default configuration */
1274     host->testbus.select_major = TSTBUS_UNIPRO;
1275     host->testbus.select_minor = 37;
1276 }
1277 
1278 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1279 {
1280     if (host->testbus.select_major >= TSTBUS_MAX) {
1281         dev_err(host->hba->dev,
1282             "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1283             __func__, host->testbus.select_major);
1284         return false;
1285     }
1286 
1287     return true;
1288 }
1289 
1290 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1291 {
1292     int reg;
1293     int offset;
1294     u32 mask = TEST_BUS_SUB_SEL_MASK;
1295 
1296     if (!host)
1297         return -EINVAL;
1298 
1299     if (!ufs_qcom_testbus_cfg_is_ok(host))
1300         return -EPERM;
1301 
1302     switch (host->testbus.select_major) {
1303     case TSTBUS_UAWM:
1304         reg = UFS_TEST_BUS_CTRL_0;
1305         offset = 24;
1306         break;
1307     case TSTBUS_UARM:
1308         reg = UFS_TEST_BUS_CTRL_0;
1309         offset = 16;
1310         break;
1311     case TSTBUS_TXUC:
1312         reg = UFS_TEST_BUS_CTRL_0;
1313         offset = 8;
1314         break;
1315     case TSTBUS_RXUC:
1316         reg = UFS_TEST_BUS_CTRL_0;
1317         offset = 0;
1318         break;
1319     case TSTBUS_DFC:
1320         reg = UFS_TEST_BUS_CTRL_1;
1321         offset = 24;
1322         break;
1323     case TSTBUS_TRLUT:
1324         reg = UFS_TEST_BUS_CTRL_1;
1325         offset = 16;
1326         break;
1327     case TSTBUS_TMRLUT:
1328         reg = UFS_TEST_BUS_CTRL_1;
1329         offset = 8;
1330         break;
1331     case TSTBUS_OCSC:
1332         reg = UFS_TEST_BUS_CTRL_1;
1333         offset = 0;
1334         break;
1335     case TSTBUS_WRAPPER:
1336         reg = UFS_TEST_BUS_CTRL_2;
1337         offset = 16;
1338         break;
1339     case TSTBUS_COMBINED:
1340         reg = UFS_TEST_BUS_CTRL_2;
1341         offset = 8;
1342         break;
1343     case TSTBUS_UTP_HCI:
1344         reg = UFS_TEST_BUS_CTRL_2;
1345         offset = 0;
1346         break;
1347     case TSTBUS_UNIPRO:
1348         reg = UFS_UNIPRO_CFG;
1349         offset = 20;
1350         mask = 0xFFF;
1351         break;
1352     /*
1353      * No need for a default case, since
1354      * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1355      * is legal
1356      */
1357     }
1358     mask <<= offset;
1359     ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1360             (u32)host->testbus.select_major << 19,
1361             REG_UFS_CFG1);
1362     ufshcd_rmwl(host->hba, mask,
1363             (u32)host->testbus.select_minor << offset,
1364             reg);
1365     ufs_qcom_enable_test_bus(host);
1366     /*
1367      * Make sure the test bus configuration is
1368      * committed before returning.
1369      */
1370     mb();
1371 
1372     return 0;
1373 }
1374 
1375 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1376 {
1377     ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1378              "HCI Vendor Specific Registers ");
1379 
1380     ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1381 }
1382 
1383 /**
1384  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1385  * @hba: per-adapter instance
1386  *
1387  * Toggles the (optional) reset line to reset the attached device.
1388  */
1389 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1390 {
1391     struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1392 
1393     /* reset gpio is optional */
1394     if (!host->device_reset)
1395         return -EOPNOTSUPP;
1396 
1397     /*
1398      * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1399      * be on the safe side.
1400      */
1401     ufs_qcom_device_reset_ctrl(hba, true);
1402     usleep_range(10, 15);
1403 
1404     ufs_qcom_device_reset_ctrl(hba, false);
1405     usleep_range(10, 15);
1406 
1407     return 0;
1408 }
1409 
1410 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1411 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1412                     struct devfreq_dev_profile *p,
1413                     struct devfreq_simple_ondemand_data *d)
1414 {
1415     p->polling_ms = 60;
1416     d->upthreshold = 70;
1417     d->downdifferential = 5;
1418 }
1419 #else
1420 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1421         struct devfreq_dev_profile *p,
1422         struct devfreq_simple_ondemand_data *data)
1423 {
1424 }
1425 #endif
1426 
1427 /*
1428  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1429  *
1430  * The variant operations configure the necessary controller and PHY
1431  * handshake during initialization.
1432  */
1433 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1434     .name                   = "qcom",
1435     .init                   = ufs_qcom_init,
1436     .exit                   = ufs_qcom_exit,
1437     .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1438     .clk_scale_notify   = ufs_qcom_clk_scale_notify,
1439     .setup_clocks           = ufs_qcom_setup_clocks,
1440     .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1441     .link_startup_notify    = ufs_qcom_link_startup_notify,
1442     .pwr_change_notify  = ufs_qcom_pwr_change_notify,
1443     .apply_dev_quirks   = ufs_qcom_apply_dev_quirks,
1444     .suspend        = ufs_qcom_suspend,
1445     .resume         = ufs_qcom_resume,
1446     .dbg_register_dump  = ufs_qcom_dump_dbg_regs,
1447     .device_reset       = ufs_qcom_device_reset,
1448     .config_scaling_param = ufs_qcom_config_scaling_param,
1449     .program_key        = ufs_qcom_ice_program_key,
1450 };
1451 
1452 /**
1453  * ufs_qcom_probe - probe routine of the driver
1454  * @pdev: pointer to Platform device handle
1455  *
1456  * Return zero for success and non-zero for failure
1457  */
1458 static int ufs_qcom_probe(struct platform_device *pdev)
1459 {
1460     int err;
1461     struct device *dev = &pdev->dev;
1462 
1463     /* Perform generic probe */
1464     err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1465     if (err)
1466         dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1467 
1468     return err;
1469 }
1470 
1471 /**
1472  * ufs_qcom_remove - set driver_data of the device to NULL
1473  * @pdev: pointer to platform device handle
1474  *
1475  * Always returns 0
1476  */
1477 static int ufs_qcom_remove(struct platform_device *pdev)
1478 {
1479     struct ufs_hba *hba =  platform_get_drvdata(pdev);
1480 
1481     pm_runtime_get_sync(&(pdev)->dev);
1482     ufshcd_remove(hba);
1483     return 0;
1484 }
1485 
1486 static const struct of_device_id ufs_qcom_of_match[] = {
1487     { .compatible = "qcom,ufshc"},
1488     {},
1489 };
1490 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1491 
1492 #ifdef CONFIG_ACPI
1493 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1494     { "QCOM24A5" },
1495     { },
1496 };
1497 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1498 #endif
1499 
1500 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1501     SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1502     SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1503     .prepare     = ufshcd_suspend_prepare,
1504     .complete    = ufshcd_resume_complete,
1505 };
1506 
1507 static struct platform_driver ufs_qcom_pltform = {
1508     .probe  = ufs_qcom_probe,
1509     .remove = ufs_qcom_remove,
1510     .shutdown = ufshcd_pltfrm_shutdown,
1511     .driver = {
1512         .name   = "ufshcd-qcom",
1513         .pm = &ufs_qcom_pm_ops,
1514         .of_match_table = of_match_ptr(ufs_qcom_of_match),
1515         .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1516     },
1517 };
1518 module_platform_driver(ufs_qcom_pltform);
1519 
1520 MODULE_LICENSE("GPL v2");
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