ufs/host/ufs-qcom-ice.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Qualcomm ICE (Inline Crypto Engine) support.
0004  *
0005  * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
0006  * Copyright 2019 Google LLC
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/qcom_scm.h>
0012
0013 #include "ufs-qcom.h"
0014
0015 #define AES_256_XTS_KEY_SIZE            64
0016
0017 /* QCOM ICE registers */
0018
0019 #define QCOM_ICE_REG_CONTROL            0x0000
0020 #define QCOM_ICE_REG_RESET          0x0004
0021 #define QCOM_ICE_REG_VERSION            0x0008
0022 #define QCOM_ICE_REG_FUSE_SETTING       0x0010
0023 #define QCOM_ICE_REG_PARAMETERS_1       0x0014
0024 #define QCOM_ICE_REG_PARAMETERS_2       0x0018
0025 #define QCOM_ICE_REG_PARAMETERS_3       0x001C
0026 #define QCOM_ICE_REG_PARAMETERS_4       0x0020
0027 #define QCOM_ICE_REG_PARAMETERS_5       0x0024
0028
0029 /* QCOM ICE v3.X only */
0030 #define QCOM_ICE_GENERAL_ERR_STTS       0x0040
0031 #define QCOM_ICE_INVALID_CCFG_ERR_STTS      0x0030
0032 #define QCOM_ICE_GENERAL_ERR_MASK       0x0044
0033
0034 /* QCOM ICE v2.X only */
0035 #define QCOM_ICE_REG_NON_SEC_IRQ_STTS       0x0040
0036 #define QCOM_ICE_REG_NON_SEC_IRQ_MASK       0x0044
0037
0038 #define QCOM_ICE_REG_NON_SEC_IRQ_CLR        0x0048
0039 #define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME1    0x0050
0040 #define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME2    0x0054
0041 #define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME1    0x0058
0042 #define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME2    0x005C
0043 #define QCOM_ICE_REG_STREAM1_BIST_ERROR_VEC 0x0060
0044 #define QCOM_ICE_REG_STREAM2_BIST_ERROR_VEC 0x0064
0045 #define QCOM_ICE_REG_STREAM1_BIST_FINISH_VEC    0x0068
0046 #define QCOM_ICE_REG_STREAM2_BIST_FINISH_VEC    0x006C
0047 #define QCOM_ICE_REG_BIST_STATUS        0x0070
0048 #define QCOM_ICE_REG_BYPASS_STATUS      0x0074
0049 #define QCOM_ICE_REG_ADVANCED_CONTROL       0x1000
0050 #define QCOM_ICE_REG_ENDIAN_SWAP        0x1004
0051 #define QCOM_ICE_REG_TEST_BUS_CONTROL       0x1010
0052 #define QCOM_ICE_REG_TEST_BUS_REG       0x1014
0053
0054 /* BIST ("built-in self-test"?) status flags */
0055 #define QCOM_ICE_BIST_STATUS_MASK       0xF0000000
0056
0057 #define QCOM_ICE_FUSE_SETTING_MASK      0x1
0058 #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
0059 #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
0060
0061 #define qcom_ice_writel(host, val, reg) \
0062     writel((val), (host)->ice_mmio + (reg))
0063 #define qcom_ice_readl(host, reg)   \
0064     readl((host)->ice_mmio + (reg))
0065
0066 static bool qcom_ice_supported(struct ufs_qcom_host *host)
0067 {
0068     struct device *dev = host->hba->dev;
0069     u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION);
0070     int major = regval >> 24;
0071     int minor = (regval >> 16) & 0xFF;
0072     int step = regval & 0xFFFF;
0073
0074     /* For now this driver only supports ICE version 3. */
0075     if (major != 3) {
0076         dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
0077              major, minor, step);
0078         return false;
0079     }
0080
0081     dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
0082          major, minor, step);
0083
0084     /* If fuses are blown, ICE might not work in the standard way. */
0085     regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING);
0086     if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
0087               QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
0088               QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
0089         dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
0090         return false;
0091     }
0092     return true;
0093 }
0094
0095 int ufs_qcom_ice_init(struct ufs_qcom_host *host)
0096 {
0097     struct ufs_hba *hba = host->hba;
0098     struct device *dev = hba->dev;
0099     struct platform_device *pdev = to_platform_device(dev);
0100     struct resource *res;
0101     int err;
0102
0103     if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) &
0104           MASK_CRYPTO_SUPPORT))
0105         return 0;
0106
0107     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice");
0108     if (!res) {
0109         dev_warn(dev, "ICE registers not found\n");
0110         goto disable;
0111     }
0112
0113     if (!qcom_scm_ice_available()) {
0114         dev_warn(dev, "ICE SCM interface not found\n");
0115         goto disable;
0116     }
0117
0118     host->ice_mmio = devm_ioremap_resource(dev, res);
0119     if (IS_ERR(host->ice_mmio)) {
0120         err = PTR_ERR(host->ice_mmio);
0121         dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
0122         return err;
0123     }
0124
0125     if (!qcom_ice_supported(host))
0126         goto disable;
0127
0128     return 0;
0129
0130 disable:
0131     dev_warn(dev, "Disabling inline encryption support\n");
0132     hba->caps &= ~UFSHCD_CAP_CRYPTO;
0133     return 0;
0134 }
0135
0136 static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host)
0137 {
0138     u32 regval;
0139
0140     regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
0141     /*
0142      * Enable low power mode sequence
0143      * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
0144      */
0145     regval |= 0x7000;
0146     qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
0147 }
0148
0149 static void qcom_ice_optimization_enable(struct ufs_qcom_host *host)
0150 {
0151     u32 regval;
0152
0153     /* ICE Optimizations Enable Sequence */
0154     regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
0155     regval |= 0xD807100;
0156     /* ICE HPG requires delay before writing */
0157     udelay(5);
0158     qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
0159     udelay(5);
0160 }
0161
0162 int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
0163 {
0164     if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
0165         return 0;
0166     qcom_ice_low_power_mode_enable(host);
0167     qcom_ice_optimization_enable(host);
0168     return ufs_qcom_ice_resume(host);
0169 }
0170
0171 /* Poll until all BIST bits are reset */
0172 static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host)
0173 {
0174     int count;
0175     u32 reg;
0176
0177     for (count = 0; count < 100; count++) {
0178         reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS);
0179         if (!(reg & QCOM_ICE_BIST_STATUS_MASK))
0180             break;
0181         udelay(50);
0182     }
0183     if (reg)
0184         return -ETIMEDOUT;
0185     return 0;
0186 }
0187
0188 int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
0189 {
0190     int err;
0191
0192     if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
0193         return 0;
0194
0195     err = qcom_ice_wait_bist_status(host);
0196     if (err) {
0197         dev_err(host->hba->dev, "BIST status error (%d)\n", err);
0198         return err;
0199     }
0200     return 0;
0201 }
0202
0203 /*
0204  * Program a key into a QC ICE keyslot, or evict a keyslot.  QC ICE requires
0205  * vendor-specific SCM calls for this; it doesn't support the standard way.
0206  */
0207 int ufs_qcom_ice_program_key(struct ufs_hba *hba,
0208                  const union ufs_crypto_cfg_entry *cfg, int slot)
0209 {
0210     union ufs_crypto_cap_entry cap;
0211     union {
0212         u8 bytes[AES_256_XTS_KEY_SIZE];
0213         u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
0214     } key;
0215     int i;
0216     int err;
0217
0218     if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE))
0219         return qcom_scm_ice_invalidate_key(slot);
0220
0221     /* Only AES-256-XTS has been tested so far. */
0222     cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
0223     if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
0224         cap.key_size != UFS_CRYPTO_KEY_SIZE_256) {
0225         dev_err_ratelimited(hba->dev,
0226                     "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
0227                     cap.algorithm_id, cap.key_size);
0228         return -EINVAL;
0229     }
0230
0231     memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
0232
0233     /*
0234      * The SCM call byte-swaps the 32-bit words of the key.  So we have to
0235      * do the same, in order for the final key be correct.
0236      */
0237     for (i = 0; i < ARRAY_SIZE(key.words); i++)
0238         __cpu_to_be32s(&key.words[i]);
0239
0240     err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
0241                    QCOM_SCM_ICE_CIPHER_AES_256_XTS,
0242                    cfg->data_unit_size);
0243     memzero_explicit(&key, sizeof(key));
0244     return err;
0245 }