ufs/host/ufs-mediatek.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2019 MediaTek Inc.
0004  */
0005
0006 #ifndef _UFS_MEDIATEK_H
0007 #define _UFS_MEDIATEK_H
0008
0009 #include <linux/bitops.h>
0010 #include <linux/pm_qos.h>
0011 #include <linux/soc/mediatek/mtk_sip_svc.h>
0012
0013 /*
0014  * Vendor specific UFSHCI Registers
0015  */
0016 #define REG_UFS_XOUFS_CTRL          0x140
0017 #define REG_UFS_REFCLK_CTRL         0x144
0018 #define REG_UFS_EXTREG              0x2100
0019 #define REG_UFS_MPHYCTRL            0x2200
0020 #define REG_UFS_MTK_IP_VER          0x2240
0021 #define REG_UFS_REJECT_MON          0x22AC
0022 #define REG_UFS_DEBUG_SEL           0x22C0
0023 #define REG_UFS_PROBE               0x22C8
0024 #define REG_UFS_DEBUG_SEL_B0        0x22D0
0025 #define REG_UFS_DEBUG_SEL_B1        0x22D4
0026 #define REG_UFS_DEBUG_SEL_B2        0x22D8
0027 #define REG_UFS_DEBUG_SEL_B3        0x22DC
0028
0029 /*
0030  * Ref-clk control
0031  *
0032  * Values for register REG_UFS_REFCLK_CTRL
0033  */
0034 #define REFCLK_RELEASE              0x0
0035 #define REFCLK_REQUEST              BIT(0)
0036 #define REFCLK_ACK                  BIT(1)
0037
0038 #define REFCLK_REQ_TIMEOUT_US       3000
0039 #define REFCLK_DEFAULT_WAIT_US      32
0040
0041 /*
0042  * Other attributes
0043  */
0044 #define VS_DEBUGCLOCKENABLE         0xD0A1
0045 #define VS_SAVEPOWERCONTROL         0xD0A6
0046 #define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
0047
0048 /*
0049  * Vendor specific link state
0050  */
0051 enum {
0052     VS_LINK_DISABLED            = 0,
0053     VS_LINK_DOWN                = 1,
0054     VS_LINK_UP                  = 2,
0055     VS_LINK_HIBERN8             = 3,
0056     VS_LINK_LOST                = 4,
0057     VS_LINK_CFG                 = 5,
0058 };
0059
0060 /*
0061  * Vendor specific host controller state
0062  */
0063 enum {
0064     VS_HCE_RESET                = 0,
0065     VS_HCE_BASE                 = 1,
0066     VS_HCE_OOCPR_WAIT           = 2,
0067     VS_HCE_DME_RESET            = 3,
0068     VS_HCE_MIDDLE               = 4,
0069     VS_HCE_DME_ENABLE           = 5,
0070     VS_HCE_DEFAULTS             = 6,
0071     VS_HIB_IDLEEN               = 7,
0072     VS_HIB_ENTER                = 8,
0073     VS_HIB_ENTER_CONF           = 9,
0074     VS_HIB_MIDDLE               = 10,
0075     VS_HIB_WAITTIMER            = 11,
0076     VS_HIB_EXIT_CONF            = 12,
0077     VS_HIB_EXIT                 = 13,
0078 };
0079
0080 /*
0081  * SiP commands
0082  */
0083 #define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
0084 #define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
0085 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
0086 #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
0087 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
0088 #define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
0089 #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
0090 #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
0091
0092 /*
0093  * VS_DEBUGCLOCKENABLE
0094  */
0095 enum {
0096     TX_SYMBOL_CLK_REQ_FORCE = 5,
0097 };
0098
0099 /*
0100  * VS_SAVEPOWERCONTROL
0101  */
0102 enum {
0103     RX_SYMBOL_CLK_GATE_EN   = 0,
0104     SYS_CLK_GATE_EN         = 2,
0105     TX_CLK_GATE_EN          = 3,
0106 };
0107
0108 /*
0109  * Host capability
0110  */
0111 enum ufs_mtk_host_caps {
0112     UFS_MTK_CAP_BOOST_CRYPT_ENGINE         = 1 << 0,
0113     UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
0114     UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
0115     UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
0116     UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
0117 };
0118
0119 struct ufs_mtk_crypt_cfg {
0120     struct regulator *reg_vcore;
0121     struct clk *clk_crypt_perf;
0122     struct clk *clk_crypt_mux;
0123     struct clk *clk_crypt_lp;
0124     int vcore_volt;
0125 };
0126
0127 struct ufs_mtk_hw_ver {
0128     u8 step;
0129     u8 minor;
0130     u8 major;
0131 };
0132
0133 struct ufs_mtk_host {
0134     struct phy *mphy;
0135     struct pm_qos_request pm_qos_req;
0136     struct regulator *reg_va09;
0137     struct reset_control *hci_reset;
0138     struct reset_control *unipro_reset;
0139     struct reset_control *crypto_reset;
0140     struct ufs_hba *hba;
0141     struct ufs_mtk_crypt_cfg *crypt;
0142     struct ufs_mtk_hw_ver hw_ver;
0143     enum ufs_mtk_host_caps caps;
0144     bool mphy_powered_on;
0145     bool pm_qos_init;
0146     bool unipro_lpm;
0147     bool ref_clk_enabled;
0148     u16 ref_clk_ungating_wait_us;
0149     u16 ref_clk_gating_wait_us;
0150     u32 ip_ver;
0151 };
0152
0153 /*
0154  * Multi-VCC by Numbering
0155  */
0156 enum ufs_mtk_vcc_num {
0157     UFS_VCC_NONE = 0,
0158     UFS_VCC_1,
0159     UFS_VCC_2,
0160     UFS_VCC_MAX
0161 };
0162
0163 /*
0164  * Host Power Control options
0165  */
0166 enum {
0167     HOST_PWR_HCI = 0,
0168     HOST_PWR_MPHY
0169 };
0170
0171 /*
0172  * SMC call wrapper function
0173  */
0174 struct ufs_mtk_smc_arg {
0175     unsigned long cmd;
0176     struct arm_smccc_res *res;
0177     unsigned long v1;
0178     unsigned long v2;
0179     unsigned long v3;
0180     unsigned long v4;
0181     unsigned long v5;
0182     unsigned long v6;
0183     unsigned long v7;
0184 };
0185
0186 static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
0187 {
0188     arm_smccc_smc(MTK_SIP_UFS_CONTROL,
0189               s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
0190 }
0191
0192 #define ufs_mtk_smc(...) \
0193     _ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
0194
0195 /*
0196  * SMC call interface
0197  */
0198 #define ufs_mtk_va09_pwr_ctrl(res, on) \
0199     ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
0200
0201 #define ufs_mtk_crypto_ctrl(res, enable) \
0202     ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
0203
0204 #define ufs_mtk_ref_clk_notify(on, stage, res) \
0205     ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
0206
0207 #define ufs_mtk_device_reset_ctrl(high, res) \
0208     ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
0209
0210 #define ufs_mtk_host_pwr_ctrl(opt, on, res) \
0211     ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
0212
0213 #define ufs_mtk_get_vcc_num(res) \
0214     ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
0215
0216 #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
0217     ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
0218
0219 #endif /* !_UFS_MEDIATEK_H */