ufs/host/ufs-hisi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2017, HiSilicon. All rights reserved.
0004  */
0005
0006 #ifndef UFS_HISI_H_
0007 #define UFS_HISI_H_
0008
0009 #define HBRN8_POLL_TOUT_MS  1000
0010
0011 /*
0012  * ufs sysctrl specific define
0013  */
0014 #define PSW_POWER_CTRL  (0x04)
0015 #define PHY_ISO_EN  (0x08)
0016 #define HC_LP_CTRL  (0x0C)
0017 #define PHY_CLK_CTRL    (0x10)
0018 #define PSW_CLK_CTRL    (0x14)
0019 #define CLOCK_GATE_BYPASS   (0x18)
0020 #define RESET_CTRL_EN   (0x1C)
0021 #define UFS_SYSCTRL (0x5C)
0022 #define UFS_DEVICE_RESET_CTRL   (0x60)
0023
0024 #define BIT_UFS_PSW_ISO_CTRL        (1 << 16)
0025 #define BIT_UFS_PSW_MTCMOS_EN       (1 << 0)
0026 #define BIT_UFS_REFCLK_ISO_EN       (1 << 16)
0027 #define BIT_UFS_PHY_ISO_CTRL        (1 << 0)
0028 #define BIT_SYSCTRL_LP_ISOL_EN      (1 << 16)
0029 #define BIT_SYSCTRL_PWR_READY       (1 << 8)
0030 #define BIT_SYSCTRL_REF_CLOCK_EN    (1 << 24)
0031 #define MASK_SYSCTRL_REF_CLOCK_SEL  (0x3 << 8)
0032 #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF)
0033 #define UFS_FREQ_CFG_CLK                (0x39)
0034 #define BIT_SYSCTRL_PSW_CLK_EN      (1 << 4)
0035 #define MASK_UFS_CLK_GATE_BYPASS    (0x3F)
0036 #define BIT_SYSCTRL_LP_RESET_N      (1 << 0)
0037 #define BIT_UFS_REFCLK_SRC_SEl      (1 << 0)
0038 #define MASK_UFS_SYSCRTL_BYPASS     (0x3F << 16)
0039 #define MASK_UFS_DEVICE_RESET       (0x1 << 16)
0040 #define BIT_UFS_DEVICE_RESET        (0x1)
0041
0042 /*
0043  * M-TX Configuration Attributes for Hixxxx
0044  */
0045 #define MPHY_TX_FSM_STATE   0x41
0046 #define TX_FSM_HIBERN8  0x1
0047
0048 /*
0049  * Hixxxx UFS HC specific Registers
0050  */
0051 enum {
0052     UFS_REG_OCPTHRTL = 0xc0,
0053     UFS_REG_OOCPR    = 0xc4,
0054
0055     UFS_REG_CDACFG   = 0xd0,
0056     UFS_REG_CDATX1   = 0xd4,
0057     UFS_REG_CDATX2   = 0xd8,
0058     UFS_REG_CDARX1   = 0xdc,
0059     UFS_REG_CDARX2   = 0xe0,
0060     UFS_REG_CDASTA   = 0xe4,
0061
0062     UFS_REG_LBMCFG   = 0xf0,
0063     UFS_REG_LBMSTA   = 0xf4,
0064     UFS_REG_UFSMODE  = 0xf8,
0065
0066     UFS_REG_HCLKDIV  = 0xfc,
0067 };
0068
0069 /* AHIT - Auto-Hibernate Idle Timer */
0070 #define UFS_AHIT_AH8ITV_MASK    0x3FF
0071
0072 /* REG UFS_REG_OCPTHRTL definition */
0073 #define UFS_HCLKDIV_NORMAL_VALUE    0xE4
0074
0075 /* vendor specific pre-defined parameters */
0076 #define SLOW    1
0077 #define FAST    2
0078
0079 #define UFS_HISI_CAP_RESERVED       BIT(0)
0080 #define UFS_HISI_CAP_PHY10nm        BIT(1)
0081
0082 struct ufs_hisi_host {
0083     struct ufs_hba *hba;
0084     void __iomem *ufs_sys_ctrl;
0085
0086     struct reset_control    *rst;
0087
0088     uint64_t caps;
0089
0090     bool in_suspend;
0091 };
0092
0093 #define ufs_sys_ctrl_writel(host, val, reg)                                    \
0094     writel((val), (host)->ufs_sys_ctrl + (reg))
0095 #define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg))
0096 #define ufs_sys_ctrl_set_bits(host, mask, reg)                                 \
0097     ufs_sys_ctrl_writel(                                                   \
0098         (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg))
0099 #define ufs_sys_ctrl_clr_bits(host, mask, reg)                                 \
0100     ufs_sys_ctrl_writel((host),                                            \
0101                 ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
0102                 (reg))
0103
0104 #endif /* UFS_HISI_H_ */