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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * HiSilicon Hixxxx UFS Driver
0004  *
0005  * Copyright (c) 2016-2017 Linaro Ltd.
0006  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
0007  */
0008 
0009 #include <linux/time.h>
0010 #include <linux/delay.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/reset.h>
0017 
0018 #include <ufs/ufshcd.h>
0019 #include "ufshcd-pltfrm.h"
0020 #include <ufs/unipro.h>
0021 #include "ufs-hisi.h"
0022 #include <ufs/ufshci.h>
0023 #include <ufs/ufs_quirks.h>
0024 
0025 static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
0026 {
0027     int err = 0;
0028     u32 tx_fsm_val_0 = 0;
0029     u32 tx_fsm_val_1 = 0;
0030     unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
0031 
0032     do {
0033         err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
0034                       &tx_fsm_val_0);
0035         err |= ufshcd_dme_get(hba,
0036             UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
0037         if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
0038             tx_fsm_val_1 == TX_FSM_HIBERN8))
0039             break;
0040 
0041         /* sleep for max. 200us */
0042         usleep_range(100, 200);
0043     } while (time_before(jiffies, timeout));
0044 
0045     /*
0046      * we might have scheduled out for long during polling so
0047      * check the state again.
0048      */
0049     if (time_after(jiffies, timeout)) {
0050         err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
0051                      &tx_fsm_val_0);
0052         err |= ufshcd_dme_get(hba,
0053          UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
0054     }
0055 
0056     if (err) {
0057         dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
0058             __func__, err);
0059     } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
0060              tx_fsm_val_1 != TX_FSM_HIBERN8) {
0061         err = -1;
0062         dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
0063             __func__, tx_fsm_val_0, tx_fsm_val_1);
0064     }
0065 
0066     return err;
0067 }
0068 
0069 static void ufs_hisi_clk_init(struct ufs_hba *hba)
0070 {
0071     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0072 
0073     ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
0074     if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
0075         mdelay(1);
0076     /* use abb clk */
0077     ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
0078     ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
0079     /* open mphy ref clk */
0080     ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
0081 }
0082 
0083 static void ufs_hisi_soc_init(struct ufs_hba *hba)
0084 {
0085     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0086     u32 reg;
0087 
0088     if (!IS_ERR(host->rst))
0089         reset_control_assert(host->rst);
0090 
0091     /* HC_PSW powerup */
0092     ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL);
0093     udelay(10);
0094     /* notify PWR ready */
0095     ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL);
0096     ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,
0097         UFS_DEVICE_RESET_CTRL);
0098 
0099     reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL);
0100     reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK;
0101     /* set cfg clk freq */
0102     ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL);
0103     /* set ref clk freq */
0104     ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL);
0105     /* bypass ufs clk gate */
0106     ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS,
0107                          CLOCK_GATE_BYPASS);
0108     ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL);
0109 
0110     /* open psw clk */
0111     ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL);
0112     /* disable ufshc iso */
0113     ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL);
0114     /* disable phy iso */
0115     ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN);
0116     /* notice iso disable */
0117     ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL);
0118 
0119     /* disable lp_reset_n */
0120     ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN);
0121     mdelay(1);
0122 
0123     ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET,
0124         UFS_DEVICE_RESET_CTRL);
0125 
0126     msleep(20);
0127 
0128     /*
0129      * enable the fix of linereset recovery,
0130      * and enable rx_reset/tx_rest beat
0131      * enable ref_clk_en override(bit5) &
0132      * override value = 1(bit4), with mask
0133      */
0134     ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);
0135 
0136     if (!IS_ERR(host->rst))
0137         reset_control_deassert(host->rst);
0138 }
0139 
0140 static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
0141 {
0142     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0143     int err;
0144     uint32_t value;
0145     uint32_t reg;
0146 
0147     /* Unipro VS_mphy_disable */
0148     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);
0149     /* PA_HSSeries */
0150     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);
0151     /* MPHY CBRATESEL */
0152     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);
0153     /* MPHY CBOVRCTRL2 */
0154     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
0155     /* MPHY CBOVRCTRL3 */
0156     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
0157 
0158     if (host->caps & UFS_HISI_CAP_PHY10nm) {
0159         /* MPHY CBOVRCTRL4 */
0160         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
0161         /* MPHY CBOVRCTRL5 */
0162         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
0163     }
0164 
0165     /* Unipro VS_MphyCfgUpdt */
0166     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
0167     /* MPHY RXOVRCTRL4 rx0 */
0168     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);
0169     /* MPHY RXOVRCTRL4 rx1 */
0170     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);
0171     /* MPHY RXOVRCTRL5 rx0 */
0172     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);
0173     /* MPHY RXOVRCTRL5 rx1 */
0174     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);
0175     /* MPHY RXSQCONTROL rx0 */
0176     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);
0177     /* MPHY RXSQCONTROL rx1 */
0178     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);
0179     /* Unipro VS_MphyCfgUpdt */
0180     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
0181 
0182     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
0183     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
0184 
0185     if (host->caps & UFS_HISI_CAP_PHY10nm) {
0186         /* RX_Hibern8Time_Capability*/
0187         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
0188         /* RX_Hibern8Time_Capability*/
0189         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
0190         /* RX_Min_ActivateTime */
0191         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
0192         /* RX_Min_ActivateTime*/
0193         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
0194     } else {
0195         /* Tactive RX */
0196         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
0197         /* Tactive RX */
0198         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
0199     }
0200 
0201     /* Gear3 Synclength */
0202     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
0203     /* Gear3 Synclength */
0204     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);
0205     /* Gear2 Synclength */
0206     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);
0207     /* Gear2 Synclength */
0208     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);
0209     /* Gear1 Synclength */
0210     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);
0211     /* Gear1 Synclength */
0212     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);
0213     /* Thibernate Tx */
0214     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);
0215     /* Thibernate Tx */
0216     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);
0217 
0218     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
0219     /* Unipro VS_mphy_disable */
0220     ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);
0221     if (value != 0x1)
0222         dev_info(hba->dev,
0223             "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);
0224 
0225     /* Unipro VS_mphy_disable */
0226     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
0227     err = ufs_hisi_check_hibern8(hba);
0228     if (err)
0229         dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
0230 
0231     if (!(host->caps & UFS_HISI_CAP_PHY10nm))
0232         ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
0233 
0234     /* disable auto H8 */
0235     reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
0236     reg = reg & (~UFS_AHIT_AH8ITV_MASK);
0237     ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
0238 
0239     /* Unipro PA_Local_TX_LCC_Enable */
0240     ufshcd_disable_host_tx_lcc(hba);
0241     /* close Unipro VS_Mk2ExtnSupport */
0242     ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);
0243     ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);
0244     if (value != 0) {
0245         /* Ensure close success */
0246         dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n");
0247     }
0248 
0249     return err;
0250 }
0251 
0252 static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
0253 {
0254     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0255 
0256     /* Unipro DL_AFC0CreditThreshold */
0257     ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);
0258     /* Unipro DL_TC0OutAckThreshold */
0259     ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);
0260     /* Unipro DL_TC0TXFCThreshold */
0261     ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);
0262 
0263     /* not bypass ufs clk gate */
0264     ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS,
0265                         CLOCK_GATE_BYPASS);
0266     ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS,
0267                         UFS_SYSCTRL);
0268 
0269     /* select received symbol cnt */
0270     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);
0271      /* reset counter0 and enable */
0272     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);
0273 
0274     return 0;
0275 }
0276 
0277 static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
0278                       enum ufs_notify_change_status status)
0279 {
0280     int err = 0;
0281 
0282     switch (status) {
0283     case PRE_CHANGE:
0284         err = ufs_hisi_link_startup_pre_change(hba);
0285         break;
0286     case POST_CHANGE:
0287         err = ufs_hisi_link_startup_post_change(hba);
0288         break;
0289     default:
0290         break;
0291     }
0292 
0293     return err;
0294 }
0295 
0296 static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
0297 {
0298     ufshcd_init_pwr_dev_param(hisi_param);
0299 }
0300 
0301 static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
0302 {
0303     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0304 
0305     if (host->caps & UFS_HISI_CAP_PHY10nm) {
0306         /*
0307          * Boston platform need to set SaveConfigTime to 0x13,
0308          * and change sync length to maximum value
0309          */
0310         /* VS_DebugSaveConfigTime */
0311         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
0312         /* g1 sync length */
0313         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
0314         /* g2 sync length */
0315         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
0316         /* g3 sync length */
0317         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
0318         /* PA_Hibern8Time */
0319         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
0320         /* PA_Tactivate */
0321         ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
0322         ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
0323     }
0324 
0325     if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
0326         pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
0327         /* VS_DebugSaveConfigTime */
0328         ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);
0329         /* sync length */
0330         ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);
0331     }
0332 
0333     /* update */
0334     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);
0335     /* PA_TxSkip */
0336     ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);
0337     /*PA_PWRModeUserData0 = 8191, default is 0*/
0338     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);
0339     /*PA_PWRModeUserData1 = 65535, default is 0*/
0340     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);
0341     /*PA_PWRModeUserData2 = 32767, default is 0*/
0342     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);
0343     /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/
0344     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);
0345     /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/
0346     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);
0347     /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/
0348     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);
0349     /*PA_PWRModeUserData3 = 8191, default is 0*/
0350     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);
0351     /*PA_PWRModeUserData4 = 65535, default is 0*/
0352     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);
0353     /*PA_PWRModeUserData5 = 32767, default is 0*/
0354     ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);
0355     /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/
0356     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);
0357     /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/
0358     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);
0359     /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/
0360     ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
0361 }
0362 
0363 static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
0364                        enum ufs_notify_change_status status,
0365                        struct ufs_pa_layer_attr *dev_max_params,
0366                        struct ufs_pa_layer_attr *dev_req_params)
0367 {
0368     struct ufs_dev_params ufs_hisi_cap;
0369     int ret = 0;
0370 
0371     if (!dev_req_params) {
0372         dev_err(hba->dev,
0373                 "%s: incoming dev_req_params is NULL\n", __func__);
0374         ret = -EINVAL;
0375         goto out;
0376     }
0377 
0378     switch (status) {
0379     case PRE_CHANGE:
0380         ufs_hisi_set_dev_cap(&ufs_hisi_cap);
0381         ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
0382                            dev_max_params, dev_req_params);
0383         if (ret) {
0384             dev_err(hba->dev,
0385                 "%s: failed to determine capabilities\n", __func__);
0386             goto out;
0387         }
0388 
0389         ufs_hisi_pwr_change_pre_change(hba);
0390         break;
0391     case POST_CHANGE:
0392         break;
0393     default:
0394         ret = -EINVAL;
0395         break;
0396     }
0397 out:
0398     return ret;
0399 }
0400 
0401 static int ufs_hisi_suspend_prepare(struct device *dev)
0402 {
0403     /* RPM and SPM are different. Refer ufs_hisi_suspend() */
0404     return __ufshcd_suspend_prepare(dev, false);
0405 }
0406 
0407 static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
0408     enum ufs_notify_change_status status)
0409 {
0410     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0411 
0412     if (status == PRE_CHANGE)
0413         return 0;
0414 
0415     if (pm_op == UFS_RUNTIME_PM)
0416         return 0;
0417 
0418     if (host->in_suspend) {
0419         WARN_ON(1);
0420         return 0;
0421     }
0422 
0423     ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
0424     udelay(10);
0425     /* set ref_dig_clk override of PHY PCS to 0 */
0426     ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);
0427 
0428     host->in_suspend = true;
0429 
0430     return 0;
0431 }
0432 
0433 static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
0434 {
0435     struct ufs_hisi_host *host = ufshcd_get_variant(hba);
0436 
0437     if (!host->in_suspend)
0438         return 0;
0439 
0440     /* set ref_dig_clk override of PHY PCS to 1 */
0441     ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);
0442     udelay(10);
0443     ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
0444 
0445     host->in_suspend = false;
0446     return 0;
0447 }
0448 
0449 static int ufs_hisi_get_resource(struct ufs_hisi_host *host)
0450 {
0451     struct device *dev = host->hba->dev;
0452     struct platform_device *pdev = to_platform_device(dev);
0453 
0454     /* get resource of ufs sys ctrl */
0455     host->ufs_sys_ctrl = devm_platform_ioremap_resource(pdev, 1);
0456     return PTR_ERR_OR_ZERO(host->ufs_sys_ctrl);
0457 }
0458 
0459 static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba)
0460 {
0461     hba->rpm_lvl = UFS_PM_LVL_1;
0462     hba->spm_lvl = UFS_PM_LVL_3;
0463 }
0464 
0465 /**
0466  * ufs_hisi_init_common
0467  * @hba: host controller instance
0468  */
0469 static int ufs_hisi_init_common(struct ufs_hba *hba)
0470 {
0471     int err = 0;
0472     struct device *dev = hba->dev;
0473     struct ufs_hisi_host *host;
0474 
0475     host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
0476     if (!host)
0477         return -ENOMEM;
0478 
0479     host->hba = hba;
0480     ufshcd_set_variant(hba, host);
0481 
0482     host->rst = devm_reset_control_get(dev, "rst");
0483     if (IS_ERR(host->rst)) {
0484         dev_err(dev, "%s: failed to get reset control\n", __func__);
0485         err = PTR_ERR(host->rst);
0486         goto error;
0487     }
0488 
0489     ufs_hisi_set_pm_lvl(hba);
0490 
0491     err = ufs_hisi_get_resource(host);
0492     if (err)
0493         goto error;
0494 
0495     return 0;
0496 
0497 error:
0498     ufshcd_set_variant(hba, NULL);
0499     return err;
0500 }
0501 
0502 static int ufs_hi3660_init(struct ufs_hba *hba)
0503 {
0504     int ret = 0;
0505     struct device *dev = hba->dev;
0506 
0507     ret = ufs_hisi_init_common(hba);
0508     if (ret) {
0509         dev_err(dev, "%s: ufs common init fail\n", __func__);
0510         return ret;
0511     }
0512 
0513     ufs_hisi_clk_init(hba);
0514 
0515     ufs_hisi_soc_init(hba);
0516 
0517     return 0;
0518 }
0519 
0520 static int ufs_hi3670_init(struct ufs_hba *hba)
0521 {
0522     int ret = 0;
0523     struct device *dev = hba->dev;
0524     struct ufs_hisi_host *host;
0525 
0526     ret = ufs_hisi_init_common(hba);
0527     if (ret) {
0528         dev_err(dev, "%s: ufs common init fail\n", __func__);
0529         return ret;
0530     }
0531 
0532     ufs_hisi_clk_init(hba);
0533 
0534     ufs_hisi_soc_init(hba);
0535 
0536     /* Add cap for 10nm PHY variant on HI3670 SoC */
0537     host = ufshcd_get_variant(hba);
0538     host->caps |= UFS_HISI_CAP_PHY10nm;
0539 
0540     return 0;
0541 }
0542 
0543 static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
0544     .name = "hi3660",
0545     .init = ufs_hi3660_init,
0546     .link_startup_notify = ufs_hisi_link_startup_notify,
0547     .pwr_change_notify = ufs_hisi_pwr_change_notify,
0548     .suspend = ufs_hisi_suspend,
0549     .resume = ufs_hisi_resume,
0550 };
0551 
0552 static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
0553     .name = "hi3670",
0554     .init = ufs_hi3670_init,
0555     .link_startup_notify = ufs_hisi_link_startup_notify,
0556     .pwr_change_notify = ufs_hisi_pwr_change_notify,
0557     .suspend = ufs_hisi_suspend,
0558     .resume = ufs_hisi_resume,
0559 };
0560 
0561 static const struct of_device_id ufs_hisi_of_match[] = {
0562     { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
0563     { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
0564     {},
0565 };
0566 
0567 MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
0568 
0569 static int ufs_hisi_probe(struct platform_device *pdev)
0570 {
0571     const struct of_device_id *of_id;
0572 
0573     of_id = of_match_node(ufs_hisi_of_match, pdev->dev.of_node);
0574 
0575     return ufshcd_pltfrm_init(pdev, of_id->data);
0576 }
0577 
0578 static int ufs_hisi_remove(struct platform_device *pdev)
0579 {
0580     struct ufs_hba *hba =  platform_get_drvdata(pdev);
0581 
0582     ufshcd_remove(hba);
0583     return 0;
0584 }
0585 
0586 static const struct dev_pm_ops ufs_hisi_pm_ops = {
0587     SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
0588     SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
0589     .prepare     = ufs_hisi_suspend_prepare,
0590     .complete    = ufshcd_resume_complete,
0591 };
0592 
0593 static struct platform_driver ufs_hisi_pltform = {
0594     .probe  = ufs_hisi_probe,
0595     .remove = ufs_hisi_remove,
0596     .shutdown = ufshcd_pltfrm_shutdown,
0597     .driver = {
0598         .name   = "ufshcd-hisi",
0599         .pm = &ufs_hisi_pm_ops,
0600         .of_match_table = of_match_ptr(ufs_hisi_of_match),
0601     },
0602 };
0603 module_platform_driver(ufs_hisi_pltform);
0604 
0605 MODULE_LICENSE("GPL");
0606 MODULE_ALIAS("platform:ufshcd-hisi");
0607 MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver");
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