ufs/host/ufs-exynos.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * UFS Host Controller driver for Exynos specific extensions
0004  *
0005  * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
0006  *
0007  */
0008
0009 #ifndef _UFS_EXYNOS_H_
0010 #define _UFS_EXYNOS_H_
0011
0012 /*
0013  * UNIPRO registers
0014  */
0015 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE     0x150
0016
0017 /*
0018  * MIBs for PA debug registers
0019  */
0020 #define PA_DBG_CLK_PERIOD   0x9514
0021 #define PA_DBG_TXPHY_CFGUPDT    0x9518
0022 #define PA_DBG_RXPHY_CFGUPDT    0x9519
0023 #define PA_DBG_MODE     0x9529
0024 #define PA_DBG_SKIP_RESET_PHY   0x9539
0025 #define PA_DBG_AUTOMODE_THLD    0x9536
0026 #define PA_DBG_OV_TM        0x9540
0027 #define PA_DBG_SKIP_LINE_RESET  0x9541
0028 #define PA_DBG_LINE_RESET_REQ   0x9543
0029 #define PA_DBG_OPTION_SUITE 0x9564
0030 #define PA_DBG_OPTION_SUITE_DYN 0x9565
0031
0032 /*
0033  * MIBs for Transport Layer debug registers
0034  */
0035 #define T_DBG_SKIP_INIT_HIBERN8_EXIT    0xc001
0036
0037 /*
0038  * Exynos MPHY attributes
0039  */
0040 #define TX_LINERESET_N_VAL  0x0277
0041 #define TX_LINERESET_N(v)   (((v) >> 10) & 0xFF)
0042 #define TX_LINERESET_P_VAL  0x027D
0043 #define TX_LINERESET_P(v)   (((v) >> 12) & 0xFF)
0044 #define TX_OV_SLEEP_CNT_TIMER   0x028E
0045 #define TX_OV_H8_ENTER_EN   (1 << 7)
0046 #define TX_OV_SLEEP_CNT(v)  (((v) >> 5) & 0x7F)
0047 #define TX_HIGH_Z_CNT_11_08 0x028C
0048 #define TX_HIGH_Z_CNT_H(v)  (((v) >> 8) & 0xF)
0049 #define TX_HIGH_Z_CNT_07_00 0x028D
0050 #define TX_HIGH_Z_CNT_L(v)  ((v) & 0xFF)
0051 #define TX_BASE_NVAL_07_00  0x0293
0052 #define TX_BASE_NVAL_L(v)   ((v) & 0xFF)
0053 #define TX_BASE_NVAL_15_08  0x0294
0054 #define TX_BASE_NVAL_H(v)   (((v) >> 8) & 0xFF)
0055 #define TX_GRAN_NVAL_07_00  0x0295
0056 #define TX_GRAN_NVAL_L(v)   ((v) & 0xFF)
0057 #define TX_GRAN_NVAL_10_08  0x0296
0058 #define TX_GRAN_NVAL_H(v)   (((v) >> 8) & 0x3)
0059
0060 #define VND_TX_CLK_PRD      0xAA
0061 #define VND_TX_CLK_PRD_EN   0xA9
0062 #define VND_TX_LINERESET_PVALUE0    0xAD
0063 #define VND_TX_LINERESET_PVALUE1    0xAC
0064 #define VND_TX_LINERESET_PVALUE2    0xAB
0065
0066 #define TX_LINE_RESET_TIME  3200
0067
0068 #define VND_RX_CLK_PRD      0x12
0069 #define VND_RX_CLK_PRD_EN   0x11
0070 #define VND_RX_LINERESET_VALUE0 0x1D
0071 #define VND_RX_LINERESET_VALUE1 0x1C
0072 #define VND_RX_LINERESET_VALUE2 0x1B
0073
0074 #define RX_LINE_RESET_TIME  1000
0075
0076 #define RX_FILLER_ENABLE    0x0316
0077 #define RX_FILLER_EN        (1 << 1)
0078 #define RX_LINERESET_VAL    0x0317
0079 #define RX_LINERESET(v) (((v) >> 12) & 0xFF)
0080 #define RX_LCC_IGNORE       0x0318
0081 #define RX_SYNC_MASK_LENGTH 0x0321
0082 #define RX_HIBERN8_WAIT_VAL_BIT_20_16   0x0331
0083 #define RX_HIBERN8_WAIT_VAL_BIT_15_08   0x0332
0084 #define RX_HIBERN8_WAIT_VAL_BIT_07_00   0x0333
0085 #define RX_OV_SLEEP_CNT_TIMER   0x0340
0086 #define RX_OV_SLEEP_CNT(v)  (((v) >> 6) & 0x1F)
0087 #define RX_OV_STALL_CNT_TIMER   0x0341
0088 #define RX_OV_STALL_CNT(v)  (((v) >> 4) & 0xFF)
0089 #define RX_BASE_NVAL_07_00  0x0355
0090 #define RX_BASE_NVAL_L(v)   ((v) & 0xFF)
0091 #define RX_BASE_NVAL_15_08  0x0354
0092 #define RX_BASE_NVAL_H(v)   (((v) >> 8) & 0xFF)
0093 #define RX_GRAN_NVAL_07_00  0x0353
0094 #define RX_GRAN_NVAL_L(v)   ((v) & 0xFF)
0095 #define RX_GRAN_NVAL_10_08  0x0352
0096 #define RX_GRAN_NVAL_H(v)   (((v) >> 8) & 0x3)
0097
0098 #define CMN_PWM_CLK_CTRL    0x0402
0099 #define PWM_CLK_CTRL_MASK   0x3
0100
0101 #define IATOVAL_NSEC        20000   /* unit: ns */
0102 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
0103
0104 struct exynos_ufs;
0105
0106 /* vendor specific pre-defined parameters */
0107 #define SLOW 1
0108 #define FAST 2
0109
0110 #define RX_ADV_FINE_GRAN_SUP_EN 0x1
0111 #define RX_ADV_FINE_GRAN_STEP_VAL   0x3
0112 #define RX_ADV_MIN_ACTV_TIME_CAP    0x9
0113
0114 #define PA_GRANULARITY_VAL  0x6
0115 #define PA_TACTIVATE_VAL    0x3
0116 #define PA_HIBERN8TIME_VAL  0x20
0117
0118 #define PCLK_AVAIL_MIN  70000000
0119 #define PCLK_AVAIL_MAX  167000000
0120
0121 struct exynos_ufs_uic_attr {
0122     /* TX Attributes */
0123     unsigned int tx_trailingclks;
0124     unsigned int tx_dif_p_nsec;
0125     unsigned int tx_dif_n_nsec;
0126     unsigned int tx_high_z_cnt_nsec;
0127     unsigned int tx_base_unit_nsec;
0128     unsigned int tx_gran_unit_nsec;
0129     unsigned int tx_sleep_cnt;
0130     unsigned int tx_min_activatetime;
0131     /* RX Attributes */
0132     unsigned int rx_filler_enable;
0133     unsigned int rx_dif_p_nsec;
0134     unsigned int rx_hibern8_wait_nsec;
0135     unsigned int rx_base_unit_nsec;
0136     unsigned int rx_gran_unit_nsec;
0137     unsigned int rx_sleep_cnt;
0138     unsigned int rx_stall_cnt;
0139     unsigned int rx_hs_g1_sync_len_cap;
0140     unsigned int rx_hs_g2_sync_len_cap;
0141     unsigned int rx_hs_g3_sync_len_cap;
0142     unsigned int rx_hs_g1_prep_sync_len_cap;
0143     unsigned int rx_hs_g2_prep_sync_len_cap;
0144     unsigned int rx_hs_g3_prep_sync_len_cap;
0145     /* Common Attributes */
0146     unsigned int cmn_pwm_clk_ctrl;
0147     /* Internal Attributes */
0148     unsigned int pa_dbg_option_suite;
0149     /* Changeable Attributes */
0150     unsigned int rx_adv_fine_gran_sup_en;
0151     unsigned int rx_adv_fine_gran_step;
0152     unsigned int rx_min_actv_time_cap;
0153     unsigned int rx_hibern8_time_cap;
0154     unsigned int rx_adv_min_actv_time_cap;
0155     unsigned int rx_adv_hibern8_time_cap;
0156     unsigned int pa_granularity;
0157     unsigned int pa_tactivate;
0158     unsigned int pa_hibern8time;
0159 };
0160
0161 struct exynos_ufs_drv_data {
0162     const struct ufs_hba_variant_ops *vops;
0163     struct exynos_ufs_uic_attr *uic_attr;
0164     unsigned int quirks;
0165     unsigned int opts;
0166     /* SoC's specific operations */
0167     int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
0168     int (*pre_link)(struct exynos_ufs *ufs);
0169     int (*post_link)(struct exynos_ufs *ufs);
0170     int (*pre_pwr_change)(struct exynos_ufs *ufs,
0171                 struct ufs_pa_layer_attr *pwr);
0172     int (*post_pwr_change)(struct exynos_ufs *ufs,
0173                 struct ufs_pa_layer_attr *pwr);
0174     int (*pre_hce_enable)(struct exynos_ufs *ufs);
0175     int (*post_hce_enable)(struct exynos_ufs *ufs);
0176 };
0177
0178 struct ufs_phy_time_cfg {
0179     u32 tx_linereset_p;
0180     u32 tx_linereset_n;
0181     u32 tx_high_z_cnt;
0182     u32 tx_base_n_val;
0183     u32 tx_gran_n_val;
0184     u32 tx_sleep_cnt;
0185     u32 rx_linereset;
0186     u32 rx_hibern8_wait;
0187     u32 rx_base_n_val;
0188     u32 rx_gran_n_val;
0189     u32 rx_sleep_cnt;
0190     u32 rx_stall_cnt;
0191 };
0192
0193 struct exynos_ufs {
0194     struct ufs_hba *hba;
0195     struct phy *phy;
0196     void __iomem *reg_hci;
0197     void __iomem *reg_unipro;
0198     void __iomem *reg_ufsp;
0199     struct clk *clk_hci_core;
0200     struct clk *clk_unipro_main;
0201     struct clk *clk_apb;
0202     u32 pclk_rate;
0203     u32 pclk_div;
0204     u32 pclk_avail_min;
0205     u32 pclk_avail_max;
0206     unsigned long mclk_rate;
0207     int avail_ln_rx;
0208     int avail_ln_tx;
0209     int rx_sel_idx;
0210     struct ufs_pa_layer_attr dev_req_params;
0211     struct ufs_phy_time_cfg t_cfg;
0212     ktime_t entry_hibern8_t;
0213     const struct exynos_ufs_drv_data *drv_data;
0214     struct regmap *sysreg;
0215     u32 shareability_reg_offset;
0216
0217     u32 opts;
0218 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL     BIT(0)
0219 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB    BIT(1)
0220 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
0221 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX    BIT(3)
0222 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
0223 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
0224 };
0225
0226 #define for_each_ufs_rx_lane(ufs, i) \
0227     for (i = (ufs)->rx_sel_idx; \
0228         i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
0229 #define for_each_ufs_tx_lane(ufs, i) \
0230     for (i = 0; i < (ufs)->avail_ln_tx; i++)
0231
0232 #define EXYNOS_UFS_MMIO_FUNC(name)                    \
0233 static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
0234 {                                     \
0235     writel(val, ufs->reg_##name + reg);               \
0236 }                                     \
0237                                       \
0238 static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg)       \
0239 {                                     \
0240     return readl(ufs->reg_##name + reg);                  \
0241 }
0242
0243 EXYNOS_UFS_MMIO_FUNC(hci);
0244 EXYNOS_UFS_MMIO_FUNC(unipro);
0245 EXYNOS_UFS_MMIO_FUNC(ufsp);
0246 #undef EXYNOS_UFS_MMIO_FUNC
0247
0248 long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
0249
0250 static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
0251 {
0252     ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true);
0253 }
0254
0255 static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
0256 {
0257     ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false);
0258 }
0259
0260 static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
0261 {
0262     ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true);
0263 }
0264
0265 static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
0266 {
0267     ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false);
0268 }
0269
0270 #endif /* _UFS_EXYNOS_H_ */