ufs/core/ufshcd-crypto.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2019 Google LLC
0004  */
0005
0006 #include <ufs/ufshcd.h>
0007 #include "ufshcd-crypto.h"
0008
0009 /* Blk-crypto modes supported by UFS crypto */
0010 static const struct ufs_crypto_alg_entry {
0011     enum ufs_crypto_alg ufs_alg;
0012     enum ufs_crypto_key_size ufs_key_size;
0013 } ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
0014     [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
0015         .ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
0016         .ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
0017     },
0018 };
0019
0020 static int ufshcd_program_key(struct ufs_hba *hba,
0021                   const union ufs_crypto_cfg_entry *cfg, int slot)
0022 {
0023     int i;
0024     u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);
0025     int err = 0;
0026
0027     ufshcd_hold(hba, false);
0028
0029     if (hba->vops && hba->vops->program_key) {
0030         err = hba->vops->program_key(hba, cfg, slot);
0031         goto out;
0032     }
0033
0034     /* Ensure that CFGE is cleared before programming the key */
0035     ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
0036     for (i = 0; i < 16; i++) {
0037         ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
0038                   slot_offset + i * sizeof(cfg->reg_val[0]));
0039     }
0040     /* Write dword 17 */
0041     ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
0042               slot_offset + 17 * sizeof(cfg->reg_val[0]));
0043     /* Dword 16 must be written last */
0044     ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
0045               slot_offset + 16 * sizeof(cfg->reg_val[0]));
0046 out:
0047     ufshcd_release(hba);
0048     return err;
0049 }
0050
0051 static int ufshcd_crypto_keyslot_program(struct blk_crypto_profile *profile,
0052                      const struct blk_crypto_key *key,
0053                      unsigned int slot)
0054 {
0055     struct ufs_hba *hba =
0056         container_of(profile, struct ufs_hba, crypto_profile);
0057     const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
0058     const struct ufs_crypto_alg_entry *alg =
0059             &ufs_crypto_algs[key->crypto_cfg.crypto_mode];
0060     u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
0061     int i;
0062     int cap_idx = -1;
0063     union ufs_crypto_cfg_entry cfg = {};
0064     int err;
0065
0066     BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
0067     for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
0068         if (ccap_array[i].algorithm_id == alg->ufs_alg &&
0069             ccap_array[i].key_size == alg->ufs_key_size &&
0070             (ccap_array[i].sdus_mask & data_unit_mask)) {
0071             cap_idx = i;
0072             break;
0073         }
0074     }
0075
0076     if (WARN_ON(cap_idx < 0))
0077         return -EOPNOTSUPP;
0078
0079     cfg.data_unit_size = data_unit_mask;
0080     cfg.crypto_cap_idx = cap_idx;
0081     cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;
0082
0083     if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
0084         /* In XTS mode, the blk_crypto_key's size is already doubled */
0085         memcpy(cfg.crypto_key, key->raw, key->size/2);
0086         memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
0087                key->raw + key->size/2, key->size/2);
0088     } else {
0089         memcpy(cfg.crypto_key, key->raw, key->size);
0090     }
0091
0092     err = ufshcd_program_key(hba, &cfg, slot);
0093
0094     memzero_explicit(&cfg, sizeof(cfg));
0095     return err;
0096 }
0097
0098 static int ufshcd_clear_keyslot(struct ufs_hba *hba, int slot)
0099 {
0100     /*
0101      * Clear the crypto cfg on the device. Clearing CFGE
0102      * might not be sufficient, so just clear the entire cfg.
0103      */
0104     union ufs_crypto_cfg_entry cfg = {};
0105
0106     return ufshcd_program_key(hba, &cfg, slot);
0107 }
0108
0109 static int ufshcd_crypto_keyslot_evict(struct blk_crypto_profile *profile,
0110                        const struct blk_crypto_key *key,
0111                        unsigned int slot)
0112 {
0113     struct ufs_hba *hba =
0114         container_of(profile, struct ufs_hba, crypto_profile);
0115
0116     return ufshcd_clear_keyslot(hba, slot);
0117 }
0118
0119 bool ufshcd_crypto_enable(struct ufs_hba *hba)
0120 {
0121     if (!(hba->caps & UFSHCD_CAP_CRYPTO))
0122         return false;
0123
0124     /* Reset might clear all keys, so reprogram all the keys. */
0125     blk_crypto_reprogram_all_keys(&hba->crypto_profile);
0126     return true;
0127 }
0128
0129 static const struct blk_crypto_ll_ops ufshcd_crypto_ops = {
0130     .keyslot_program    = ufshcd_crypto_keyslot_program,
0131     .keyslot_evict      = ufshcd_crypto_keyslot_evict,
0132 };
0133
0134 static enum blk_crypto_mode_num
0135 ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
0136 {
0137     int i;
0138
0139     for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
0140         BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
0141         if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
0142             ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
0143             return i;
0144         }
0145     }
0146     return BLK_ENCRYPTION_MODE_INVALID;
0147 }
0148
0149 /**
0150  * ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
0151  *                   fields in hba
0152  * @hba: Per adapter instance
0153  *
0154  * Return: 0 if crypto was initialized or is not supported, else a -errno value.
0155  */
0156 int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
0157 {
0158     int cap_idx;
0159     int err = 0;
0160     enum blk_crypto_mode_num blk_mode_num;
0161
0162     /*
0163      * Don't use crypto if either the hardware doesn't advertise the
0164      * standard crypto capability bit *or* if the vendor specific driver
0165      * hasn't advertised that crypto is supported.
0166      */
0167     if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) ||
0168         !(hba->caps & UFSHCD_CAP_CRYPTO))
0169         goto out;
0170
0171     hba->crypto_capabilities.reg_val =
0172             cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
0173     hba->crypto_cfg_register =
0174         (u32)hba->crypto_capabilities.config_array_ptr * 0x100;
0175     hba->crypto_cap_array =
0176         devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
0177                  sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
0178     if (!hba->crypto_cap_array) {
0179         err = -ENOMEM;
0180         goto out;
0181     }
0182
0183     /* The actual number of configurations supported is (CFGC+1) */
0184     err = devm_blk_crypto_profile_init(
0185             hba->dev, &hba->crypto_profile,
0186             hba->crypto_capabilities.config_count + 1);
0187     if (err)
0188         goto out;
0189
0190     hba->crypto_profile.ll_ops = ufshcd_crypto_ops;
0191     /* UFS only supports 8 bytes for any DUN */
0192     hba->crypto_profile.max_dun_bytes_supported = 8;
0193     hba->crypto_profile.dev = hba->dev;
0194
0195     /*
0196      * Cache all the UFS crypto capabilities and advertise the supported
0197      * crypto modes and data unit sizes to the block layer.
0198      */
0199     for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
0200          cap_idx++) {
0201         hba->crypto_cap_array[cap_idx].reg_val =
0202             cpu_to_le32(ufshcd_readl(hba,
0203                          REG_UFS_CRYPTOCAP +
0204                          cap_idx * sizeof(__le32)));
0205         blk_mode_num = ufshcd_find_blk_crypto_mode(
0206                         hba->crypto_cap_array[cap_idx]);
0207         if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
0208             hba->crypto_profile.modes_supported[blk_mode_num] |=
0209                 hba->crypto_cap_array[cap_idx].sdus_mask * 512;
0210     }
0211
0212     return 0;
0213
0214 out:
0215     /* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
0216     hba->caps &= ~UFSHCD_CAP_CRYPTO;
0217     return err;
0218 }
0219
0220 /**
0221  * ufshcd_init_crypto - Initialize crypto hardware
0222  * @hba: Per adapter instance
0223  */
0224 void ufshcd_init_crypto(struct ufs_hba *hba)
0225 {
0226     int slot;
0227
0228     if (!(hba->caps & UFSHCD_CAP_CRYPTO))
0229         return;
0230
0231     /* Clear all keyslots - the number of keyslots is (CFGC + 1) */
0232     for (slot = 0; slot < hba->crypto_capabilities.config_count + 1; slot++)
0233         ufshcd_clear_keyslot(hba, slot);
0234 }
0235
0236 void ufshcd_crypto_register(struct ufs_hba *hba, struct request_queue *q)
0237 {
0238     if (hba->caps & UFSHCD_CAP_CRYPTO)
0239         blk_crypto_register(&hba->crypto_profile, q);
0240 }