tty/serial/zs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * zs.h: Definitions for the DECstation Z85C30 serial driver.
0004  *
0005  * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
0006  * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
0007  *
0008  * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
0009  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0010  * Copyright (C) 2004, 2005, 2007  Maciej W. Rozycki
0011  */
0012 #ifndef _SERIAL_ZS_H
0013 #define _SERIAL_ZS_H
0014
0015 #ifdef __KERNEL__
0016
0017 #define ZS_NUM_REGS 16
0018
0019 /*
0020  * This is our internal structure for each serial port's state.
0021  */
0022 struct zs_port {
0023     struct zs_scc   *scc;           /* Containing SCC.  */
0024     struct uart_port port;          /* Underlying UART.  */
0025
0026     int     clk_mode;       /* May be 1, 16, 32, or 64.  */
0027
0028     unsigned int    tty_break;      /* Set on BREAK condition.  */
0029     int     tx_stopped;     /* Output is suspended.  */
0030
0031     unsigned int    mctrl;          /* State of modem lines.  */
0032     u8      brk;            /* BREAK state from RR0.  */
0033
0034     u8      regs[ZS_NUM_REGS];  /* Channel write registers.  */
0035 };
0036
0037 /*
0038  * Per-SCC state for locking and the interrupt handler.
0039  */
0040 struct zs_scc {
0041     struct zs_port  zport[2];
0042     spinlock_t  zlock;
0043     atomic_t    irq_guard;
0044     int     initialised;
0045 };
0046
0047 #endif /* __KERNEL__ */
0048
0049 /*
0050  * Conversion routines to/from brg time constants from/to bits per second.
0051  */
0052 #define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
0053 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
0054
0055 /*
0056  * The Zilog register set.
0057  */
0058
0059 /* Write Register 0 (Command) */
0060 #define R0      0   /* Register selects */
0061 #define R1      1
0062 #define R2      2
0063 #define R3      3
0064 #define R4      4
0065 #define R5      5
0066 #define R6      6
0067 #define R7      7
0068 #define R8      8
0069 #define R9      9
0070 #define R10     10
0071 #define R11     11
0072 #define R12     12
0073 #define R13     13
0074 #define R14     14
0075 #define R15     15
0076
0077 #define NULLCODE    0   /* Null Code */
0078 #define POINT_HIGH  0x8 /* Select upper half of registers */
0079 #define RES_EXT_INT 0x10    /* Reset Ext. Status Interrupts */
0080 #define SEND_ABORT  0x18    /* HDLC Abort */
0081 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
0082 #define RES_Tx_P    0x28    /* Reset TxINT Pending */
0083 #define ERR_RES     0x30    /* Error Reset */
0084 #define RES_H_IUS   0x38    /* Reset highest IUS */
0085
0086 #define RES_Rx_CRC  0x40    /* Reset Rx CRC Checker */
0087 #define RES_Tx_CRC  0x80    /* Reset Tx CRC Checker */
0088 #define RES_EOM_L   0xC0    /* Reset EOM latch */
0089
0090 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
0091 #define EXT_INT_ENAB    0x1 /* Ext Int Enable */
0092 #define TxINT_ENAB  0x2 /* Tx Int Enable */
0093 #define PAR_SPEC    0x4 /* Parity is special condition */
0094
0095 #define RxINT_DISAB 0   /* Rx Int Disable */
0096 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
0097 #define RxINT_ALL   0x10    /* Int on all Rx Characters or error */
0098 #define RxINT_ERR   0x18    /* Int on error only */
0099 #define RxINT_MASK  0x18
0100
0101 #define WT_RDY_RT   0x20    /* Wait/Ready on R/T */
0102 #define WT_FN_RDYFN 0x40    /* Wait/FN/Ready FN */
0103 #define WT_RDY_ENAB 0x80    /* Wait/Ready Enable */
0104
0105 /* Write Register 2 (Interrupt Vector) */
0106
0107 /* Write Register 3 (Receive Parameters and Control) */
0108 #define RxENABLE    0x1 /* Rx Enable */
0109 #define SYNC_L_INH  0x2 /* Sync Character Load Inhibit */
0110 #define ADD_SM      0x4 /* Address Search Mode (SDLC) */
0111 #define RxCRC_ENAB  0x8 /* Rx CRC Enable */
0112 #define ENT_HM      0x10    /* Enter Hunt Mode */
0113 #define AUTO_ENAB   0x20    /* Auto Enables */
0114 #define Rx5     0x0 /* Rx 5 Bits/Character */
0115 #define Rx7     0x40    /* Rx 7 Bits/Character */
0116 #define Rx6     0x80    /* Rx 6 Bits/Character */
0117 #define Rx8     0xc0    /* Rx 8 Bits/Character */
0118 #define RxNBITS_MASK    0xc0
0119
0120 /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
0121 #define PAR_ENA     0x1 /* Parity Enable */
0122 #define PAR_EVEN    0x2 /* Parity Even/Odd* */
0123
0124 #define SYNC_ENAB   0   /* Sync Modes Enable */
0125 #define SB1     0x4 /* 1 stop bit/char */
0126 #define SB15        0x8 /* 1.5 stop bits/char */
0127 #define SB2     0xc /* 2 stop bits/char */
0128 #define SB_MASK     0xc
0129
0130 #define MONSYNC     0   /* 8 Bit Sync character */
0131 #define BISYNC      0x10    /* 16 bit sync character */
0132 #define SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
0133 #define EXTSYNC     0x30    /* External Sync Mode */
0134
0135 #define X1CLK       0x0 /* x1 clock mode */
0136 #define X16CLK      0x40    /* x16 clock mode */
0137 #define X32CLK      0x80    /* x32 clock mode */
0138 #define X64CLK      0xc0    /* x64 clock mode */
0139 #define XCLK_MASK   0xc0
0140
0141 /* Write Register 5 (Transmit Parameters and Controls) */
0142 #define TxCRC_ENAB  0x1 /* Tx CRC Enable */
0143 #define RTS     0x2 /* RTS */
0144 #define SDLC_CRC    0x4 /* SDLC/CRC-16 */
0145 #define TxENAB      0x8 /* Tx Enable */
0146 #define SND_BRK     0x10    /* Send Break */
0147 #define Tx5     0x0 /* Tx 5 bits (or less)/character */
0148 #define Tx7     0x20    /* Tx 7 bits/character */
0149 #define Tx6     0x40    /* Tx 6 bits/character */
0150 #define Tx8     0x60    /* Tx 8 bits/character */
0151 #define TxNBITS_MASK    0x60
0152 #define DTR     0x80    /* DTR */
0153
0154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
0155
0156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
0157
0158 /* Write Register 8 (Transmit Buffer) */
0159
0160 /* Write Register 9 (Master Interrupt Control) */
0161 #define VIS     1   /* Vector Includes Status */
0162 #define NV      2   /* No Vector */
0163 #define DLC     4   /* Disable Lower Chain */
0164 #define MIE     8   /* Master Interrupt Enable */
0165 #define STATHI      0x10    /* Status high */
0166 #define SOFTACK     0x20    /* Software Interrupt Acknowledge */
0167 #define NORESET     0   /* No reset on write to R9 */
0168 #define CHRB        0x40    /* Reset channel B */
0169 #define CHRA        0x80    /* Reset channel A */
0170 #define FHWRES      0xc0    /* Force hardware reset */
0171
0172 /* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
0173 #define BIT6        1   /* 6 bit/8bit sync */
0174 #define LOOPMODE    2   /* SDLC Loop mode */
0175 #define ABUNDER     4   /* Abort/flag on SDLC xmit underrun */
0176 #define MARKIDLE    8   /* Mark/flag on idle */
0177 #define GAOP        0x10    /* Go active on poll */
0178 #define NRZ     0   /* NRZ mode */
0179 #define NRZI        0x20    /* NRZI mode */
0180 #define FM1     0x40    /* FM1 (transition = 1) */
0181 #define FM0     0x60    /* FM0 (transition = 0) */
0182 #define CRCPS       0x80    /* CRC Preset I/O */
0183
0184 /* Write Register 11 (Clock Mode Control) */
0185 #define TRxCXT      0   /* TRxC = Xtal output */
0186 #define TRxCTC      1   /* TRxC = Transmit clock */
0187 #define TRxCBR      2   /* TRxC = BR Generator Output */
0188 #define TRxCDP      3   /* TRxC = DPLL output */
0189 #define TRxCOI      4   /* TRxC O/I */
0190 #define TCRTxCP     0   /* Transmit clock = RTxC pin */
0191 #define TCTRxCP     8   /* Transmit clock = TRxC pin */
0192 #define TCBR        0x10    /* Transmit clock = BR Generator output */
0193 #define TCDPLL      0x18    /* Transmit clock = DPLL output */
0194 #define RCRTxCP     0   /* Receive clock = RTxC pin */
0195 #define RCTRxCP     0x20    /* Receive clock = TRxC pin */
0196 #define RCBR        0x40    /* Receive clock = BR Generator output */
0197 #define RCDPLL      0x60    /* Receive clock = DPLL output */
0198 #define RTxCX       0x80    /* RTxC Xtal/No Xtal */
0199
0200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
0201
0202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
0203
0204 /* Write Register 14 (Miscellaneous Control Bits) */
0205 #define BRENABL     1   /* Baud rate generator enable */
0206 #define BRSRC       2   /* Baud rate generator source */
0207 #define DTRREQ      4   /* DTR/Request function */
0208 #define AUTOECHO    8   /* Auto Echo */
0209 #define LOOPBAK     0x10    /* Local loopback */
0210 #define SEARCH      0x20    /* Enter search mode */
0211 #define RMC     0x40    /* Reset missing clock */
0212 #define DISDPLL     0x60    /* Disable DPLL */
0213 #define SSBR        0x80    /* Set DPLL source = BR generator */
0214 #define SSRTxC      0xa0    /* Set DPLL source = RTxC */
0215 #define SFMM        0xc0    /* Set FM mode */
0216 #define SNRZI       0xe0    /* Set NRZI mode */
0217
0218 /* Write Register 15 (External/Status Interrupt Control) */
0219 #define WR7P_EN     1   /* WR7 Prime SDLC Feature Enable */
0220 #define ZCIE        2   /* Zero count IE */
0221 #define DCDIE       8   /* DCD IE */
0222 #define SYNCIE      0x10    /* Sync/hunt IE */
0223 #define CTSIE       0x20    /* CTS IE */
0224 #define TxUIE       0x40    /* Tx Underrun/EOM IE */
0225 #define BRKIE       0x80    /* Break/Abort IE */
0226
0227
0228 /* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
0229 #define Rx_CH_AV    0x1 /* Rx Character Available */
0230 #define ZCOUNT      0x2 /* Zero count */
0231 #define Tx_BUF_EMP  0x4 /* Tx Buffer empty */
0232 #define DCD     0x8 /* DCD */
0233 #define SYNC_HUNT   0x10    /* Sync/hunt */
0234 #define CTS     0x20    /* CTS */
0235 #define TxEOM       0x40    /* Tx underrun */
0236 #define BRK_ABRT    0x80    /* Break/Abort */
0237
0238 /* Read Register 1 (Special Receive Condition Status) */
0239 #define ALL_SNT     0x1 /* All sent */
0240 /* Residue Data for 8 Rx bits/char programmed */
0241 #define RES3        0x8 /* 0/3 */
0242 #define RES4        0x4 /* 0/4 */
0243 #define RES5        0xc /* 0/5 */
0244 #define RES6        0x2 /* 0/6 */
0245 #define RES7        0xa /* 0/7 */
0246 #define RES8        0x6 /* 0/8 */
0247 #define RES18       0xe /* 1/8 */
0248 #define RES28       0x0 /* 2/8 */
0249 /* Special Rx Condition Interrupts */
0250 #define PAR_ERR     0x10    /* Parity Error */
0251 #define Rx_OVR      0x20    /* Rx Overrun Error */
0252 #define FRM_ERR     0x40    /* CRC/Framing Error */
0253 #define END_FR      0x80    /* End of Frame (SDLC) */
0254
0255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
0256
0257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
0258
0259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
0260 #define CHBEXT      0x1 /* Channel B Ext/Stat IP */
0261 #define CHBTxIP     0x2 /* Channel B Tx IP */
0262 #define CHBRxIP     0x4 /* Channel B Rx IP */
0263 #define CHAEXT      0x8 /* Channel A Ext/Stat IP */
0264 #define CHATxIP     0x10    /* Channel A Tx IP */
0265 #define CHARxIP     0x20    /* Channel A Rx IP */
0266
0267 /* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
0268
0269 /* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
0270
0271 /* Read Register 8 (Receive Data) */
0272
0273 /* Read Register 10 (Miscellaneous Status Bits) */
0274 #define ONLOOP      2   /* On loop */
0275 #define LOOPSEND    0x10    /* Loop sending */
0276 #define CLK2MIS     0x40    /* Two clocks missing */
0277 #define CLK1MIS     0x80    /* One clock missing */
0278
0279 /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
0280
0281 /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
0282
0283 /* Read Register 15 (External/Status Interrupt Control (WR15)) */
0284
0285 #endif /* _SERIAL_ZS_H */