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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * zs.c: Serial port driver for IOASIC DECstations.
0004  *
0005  * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
0006  * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
0007  *
0008  * DECstation changes
0009  * Copyright (C) 1998-2000 Harald Koerfgen
0010  * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
0011  *
0012  * For the rest of the code the original Copyright applies:
0013  * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
0014  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0015  *
0016  *
0017  * Note: for IOASIC systems the wiring is as follows:
0018  *
0019  * mouse/keyboard:
0020  * DIN-7 MJ-4  signal        SCC
0021  * 2     1     TxD       <-  A.TxD
0022  * 3     4     RxD       ->  A.RxD
0023  *
0024  * EIA-232/EIA-423:
0025  * DB-25 MMJ-6 signal        SCC
0026  * 2     2     TxD       <-  B.TxD
0027  * 3     5     RxD       ->  B.RxD
0028  * 4           RTS       <- ~A.RTS
0029  * 5           CTS       -> ~B.CTS
0030  * 6     6     DSR       -> ~A.SYNC
0031  * 8           CD        -> ~B.DCD
0032  * 12          DSRS(DCE) -> ~A.CTS  (*)
0033  * 15          TxC       ->  B.TxC
0034  * 17          RxC       ->  B.RxC
0035  * 20    1     DTR       <- ~A.DTR
0036  * 22          RI        -> ~A.DCD
0037  * 23          DSRS(DTE) <- ~B.RTS
0038  *
0039  * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
0040  *     is shared with DSRS(DTE) at pin 23.
0041  *
0042  * As you can immediately notice the wiring of the RTS, DTR and DSR signals
0043  * is a bit odd.  This makes the handling of port B unnecessarily
0044  * complicated and prevents the use of some automatic modes of operation.
0045  */
0046 
0047 #include <linux/bug.h>
0048 #include <linux/console.h>
0049 #include <linux/delay.h>
0050 #include <linux/errno.h>
0051 #include <linux/init.h>
0052 #include <linux/interrupt.h>
0053 #include <linux/io.h>
0054 #include <linux/ioport.h>
0055 #include <linux/irqflags.h>
0056 #include <linux/kernel.h>
0057 #include <linux/module.h>
0058 #include <linux/major.h>
0059 #include <linux/serial.h>
0060 #include <linux/serial_core.h>
0061 #include <linux/spinlock.h>
0062 #include <linux/sysrq.h>
0063 #include <linux/tty.h>
0064 #include <linux/tty_flip.h>
0065 #include <linux/types.h>
0066 
0067 #include <linux/atomic.h>
0068 
0069 #include <asm/dec/interrupts.h>
0070 #include <asm/dec/ioasic_addrs.h>
0071 #include <asm/dec/system.h>
0072 
0073 #include "zs.h"
0074 
0075 
0076 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
0077 MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
0078 MODULE_LICENSE("GPL");
0079 
0080 
0081 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
0082 static char zs_version[] __initdata = "0.10";
0083 
0084 /*
0085  * It would be nice to dynamically allocate everything that
0086  * depends on ZS_NUM_SCCS, so we could support any number of
0087  * Z85C30s, but for now...
0088  */
0089 #define ZS_NUM_SCCS 2       /* Max # of ZS chips supported.  */
0090 #define ZS_NUM_CHAN 2       /* 2 channels per chip.  */
0091 #define ZS_CHAN_A   0       /* Index of the channel A.  */
0092 #define ZS_CHAN_B   1       /* Index of the channel B.  */
0093 #define ZS_CHAN_IO_SIZE 8       /* IOMEM space size.  */
0094 #define ZS_CHAN_IO_STRIDE 4     /* Register alignment.  */
0095 #define ZS_CHAN_IO_OFFSET 1     /* The SCC resides on the high byte
0096                        of the 16-bit IOBUS.  */
0097 #define ZS_CLOCK        7372800     /* Z85C30 PCLK input clock rate.  */
0098 
0099 #define to_zport(uport) container_of(uport, struct zs_port, port)
0100 
0101 struct zs_parms {
0102     resource_size_t scc[ZS_NUM_SCCS];
0103     int irq[ZS_NUM_SCCS];
0104 };
0105 
0106 static struct zs_scc zs_sccs[ZS_NUM_SCCS];
0107 
0108 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
0109     0,              /* write 0 */
0110     PAR_SPEC,           /* write 1 */
0111     0,              /* write 2 */
0112     0,              /* write 3 */
0113     X16CLK | SB1,           /* write 4 */
0114     0,              /* write 5 */
0115     0, 0, 0,            /* write 6, 7, 8 */
0116     MIE | DLC | NV,         /* write 9 */
0117     NRZ,                /* write 10 */
0118     TCBR | RCBR,            /* write 11 */
0119     0, 0,               /* BRG time constant, write 12 + 13 */
0120     BRSRC | BRENABL,        /* write 14 */
0121     0,              /* write 15 */
0122 };
0123 
0124 /*
0125  * Debugging.
0126  */
0127 #undef ZS_DEBUG_REGS
0128 
0129 
0130 /*
0131  * Reading and writing Z85C30 registers.
0132  */
0133 static void recovery_delay(void)
0134 {
0135     udelay(2);
0136 }
0137 
0138 static u8 read_zsreg(struct zs_port *zport, int reg)
0139 {
0140     void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
0141     u8 retval;
0142 
0143     if (reg != 0) {
0144         writeb(reg & 0xf, control);
0145         fast_iob();
0146         recovery_delay();
0147     }
0148     retval = readb(control);
0149     recovery_delay();
0150     return retval;
0151 }
0152 
0153 static void write_zsreg(struct zs_port *zport, int reg, u8 value)
0154 {
0155     void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
0156 
0157     if (reg != 0) {
0158         writeb(reg & 0xf, control);
0159         fast_iob(); recovery_delay();
0160     }
0161     writeb(value, control);
0162     fast_iob();
0163     recovery_delay();
0164     return;
0165 }
0166 
0167 static u8 read_zsdata(struct zs_port *zport)
0168 {
0169     void __iomem *data = zport->port.membase +
0170                  ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
0171     u8 retval;
0172 
0173     retval = readb(data);
0174     recovery_delay();
0175     return retval;
0176 }
0177 
0178 static void write_zsdata(struct zs_port *zport, u8 value)
0179 {
0180     void __iomem *data = zport->port.membase +
0181                  ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
0182 
0183     writeb(value, data);
0184     fast_iob();
0185     recovery_delay();
0186     return;
0187 }
0188 
0189 #ifdef ZS_DEBUG_REGS
0190 void zs_dump(void)
0191 {
0192     struct zs_port *zport;
0193     int i, j;
0194 
0195     for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
0196         zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
0197 
0198         if (!zport->scc)
0199             continue;
0200 
0201         for (j = 0; j < 16; j++)
0202             printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
0203         printk("\n");
0204         for (j = 0; j < 16; j++)
0205             printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
0206         printk("\n\n");
0207     }
0208 }
0209 #endif
0210 
0211 
0212 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
0213 {
0214     if (irq)
0215         spin_lock_irq(lock);
0216     else
0217         spin_lock(lock);
0218 }
0219 
0220 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
0221 {
0222     if (irq)
0223         spin_unlock_irq(lock);
0224     else
0225         spin_unlock(lock);
0226 }
0227 
0228 static int zs_receive_drain(struct zs_port *zport)
0229 {
0230     int loops = 10000;
0231 
0232     while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
0233         read_zsdata(zport);
0234     return loops;
0235 }
0236 
0237 static int zs_transmit_drain(struct zs_port *zport, int irq)
0238 {
0239     struct zs_scc *scc = zport->scc;
0240     int loops = 10000;
0241 
0242     while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
0243         zs_spin_unlock_cond_irq(&scc->zlock, irq);
0244         udelay(2);
0245         zs_spin_lock_cond_irq(&scc->zlock, irq);
0246     }
0247     return loops;
0248 }
0249 
0250 static int zs_line_drain(struct zs_port *zport, int irq)
0251 {
0252     struct zs_scc *scc = zport->scc;
0253     int loops = 10000;
0254 
0255     while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
0256         zs_spin_unlock_cond_irq(&scc->zlock, irq);
0257         udelay(2);
0258         zs_spin_lock_cond_irq(&scc->zlock, irq);
0259     }
0260     return loops;
0261 }
0262 
0263 
0264 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
0265 {
0266     /* Let the current transmission finish.  */
0267     zs_line_drain(zport, irq);
0268     /* Load 'em up.  */
0269     write_zsreg(zport, R3, regs[3] & ~RxENABLE);
0270     write_zsreg(zport, R5, regs[5] & ~TxENAB);
0271     write_zsreg(zport, R4, regs[4]);
0272     write_zsreg(zport, R9, regs[9]);
0273     write_zsreg(zport, R1, regs[1]);
0274     write_zsreg(zport, R2, regs[2]);
0275     write_zsreg(zport, R10, regs[10]);
0276     write_zsreg(zport, R14, regs[14] & ~BRENABL);
0277     write_zsreg(zport, R11, regs[11]);
0278     write_zsreg(zport, R12, regs[12]);
0279     write_zsreg(zport, R13, regs[13]);
0280     write_zsreg(zport, R14, regs[14]);
0281     write_zsreg(zport, R15, regs[15]);
0282     if (regs[3] & RxENABLE)
0283         write_zsreg(zport, R3, regs[3]);
0284     if (regs[5] & TxENAB)
0285         write_zsreg(zport, R5, regs[5]);
0286     return;
0287 }
0288 
0289 
0290 /*
0291  * Status handling routines.
0292  */
0293 
0294 /*
0295  * zs_tx_empty() -- get the transmitter empty status
0296  *
0297  * Purpose: Let user call ioctl() to get info when the UART physically
0298  *      is emptied.  On bus types like RS485, the transmitter must
0299  *      release the bus after transmitting.  This must be done when
0300  *      the transmit shift register is empty, not be done when the
0301  *      transmit holding register is empty.  This functionality
0302  *      allows an RS485 driver to be written in user space.
0303  */
0304 static unsigned int zs_tx_empty(struct uart_port *uport)
0305 {
0306     struct zs_port *zport = to_zport(uport);
0307     struct zs_scc *scc = zport->scc;
0308     unsigned long flags;
0309     u8 status;
0310 
0311     spin_lock_irqsave(&scc->zlock, flags);
0312     status = read_zsreg(zport, R1);
0313     spin_unlock_irqrestore(&scc->zlock, flags);
0314 
0315     return status & ALL_SNT ? TIOCSER_TEMT : 0;
0316 }
0317 
0318 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
0319                     struct zs_port *zport_b)
0320 {
0321     u8 status_a, status_b;
0322     unsigned int mctrl;
0323 
0324     status_a = read_zsreg(zport_a, R0);
0325     status_b = read_zsreg(zport_b, R0);
0326 
0327     mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
0328         ((status_b & DCD) ? TIOCM_CAR : 0) |
0329         ((status_a & DCD) ? TIOCM_RNG : 0) |
0330         ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
0331 
0332     return mctrl;
0333 }
0334 
0335 static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
0336 {
0337     struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
0338 
0339     return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
0340 }
0341 
0342 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
0343 {
0344     struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
0345     unsigned int mmask, mctrl, delta;
0346     u8 mask_a, mask_b;
0347 
0348     if (zport == zport_a)
0349         return 0;
0350 
0351     mask_a = zport_a->regs[15];
0352     mask_b = zport->regs[15];
0353 
0354     mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
0355         ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
0356         ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
0357         ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
0358 
0359     mctrl = zport->mctrl;
0360     if (mmask) {
0361         mctrl &= ~mmask;
0362         mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
0363     }
0364 
0365     delta = mctrl ^ zport->mctrl;
0366     if (delta)
0367         zport->mctrl = mctrl;
0368 
0369     return delta;
0370 }
0371 
0372 static unsigned int zs_get_mctrl(struct uart_port *uport)
0373 {
0374     struct zs_port *zport = to_zport(uport);
0375     struct zs_scc *scc = zport->scc;
0376     unsigned int mctrl;
0377 
0378     spin_lock(&scc->zlock);
0379     mctrl = zs_raw_get_mctrl(zport);
0380     spin_unlock(&scc->zlock);
0381 
0382     return mctrl;
0383 }
0384 
0385 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
0386 {
0387     struct zs_port *zport = to_zport(uport);
0388     struct zs_scc *scc = zport->scc;
0389     struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
0390     u8 oldloop, newloop;
0391 
0392     spin_lock(&scc->zlock);
0393     if (zport != zport_a) {
0394         if (mctrl & TIOCM_DTR)
0395             zport_a->regs[5] |= DTR;
0396         else
0397             zport_a->regs[5] &= ~DTR;
0398         if (mctrl & TIOCM_RTS)
0399             zport_a->regs[5] |= RTS;
0400         else
0401             zport_a->regs[5] &= ~RTS;
0402         write_zsreg(zport_a, R5, zport_a->regs[5]);
0403     }
0404 
0405     /* Rarely modified, so don't poke at hardware unless necessary. */
0406     oldloop = zport->regs[14];
0407     newloop = oldloop;
0408     if (mctrl & TIOCM_LOOP)
0409         newloop |= LOOPBAK;
0410     else
0411         newloop &= ~LOOPBAK;
0412     if (newloop != oldloop) {
0413         zport->regs[14] = newloop;
0414         write_zsreg(zport, R14, zport->regs[14]);
0415     }
0416     spin_unlock(&scc->zlock);
0417 }
0418 
0419 static void zs_raw_stop_tx(struct zs_port *zport)
0420 {
0421     write_zsreg(zport, R0, RES_Tx_P);
0422     zport->tx_stopped = 1;
0423 }
0424 
0425 static void zs_stop_tx(struct uart_port *uport)
0426 {
0427     struct zs_port *zport = to_zport(uport);
0428     struct zs_scc *scc = zport->scc;
0429 
0430     spin_lock(&scc->zlock);
0431     zs_raw_stop_tx(zport);
0432     spin_unlock(&scc->zlock);
0433 }
0434 
0435 static void zs_raw_transmit_chars(struct zs_port *);
0436 
0437 static void zs_start_tx(struct uart_port *uport)
0438 {
0439     struct zs_port *zport = to_zport(uport);
0440     struct zs_scc *scc = zport->scc;
0441 
0442     spin_lock(&scc->zlock);
0443     if (zport->tx_stopped) {
0444         zs_transmit_drain(zport, 0);
0445         zport->tx_stopped = 0;
0446         zs_raw_transmit_chars(zport);
0447     }
0448     spin_unlock(&scc->zlock);
0449 }
0450 
0451 static void zs_stop_rx(struct uart_port *uport)
0452 {
0453     struct zs_port *zport = to_zport(uport);
0454     struct zs_scc *scc = zport->scc;
0455     struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
0456 
0457     spin_lock(&scc->zlock);
0458     zport->regs[15] &= ~BRKIE;
0459     zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
0460     zport->regs[1] |= RxINT_DISAB;
0461 
0462     if (zport != zport_a) {
0463         /* A-side DCD tracks RI and SYNC tracks DSR.  */
0464         zport_a->regs[15] &= ~(DCDIE | SYNCIE);
0465         write_zsreg(zport_a, R15, zport_a->regs[15]);
0466         if (!(zport_a->regs[15] & BRKIE)) {
0467             zport_a->regs[1] &= ~EXT_INT_ENAB;
0468             write_zsreg(zport_a, R1, zport_a->regs[1]);
0469         }
0470 
0471         /* This-side DCD tracks DCD and CTS tracks CTS.  */
0472         zport->regs[15] &= ~(DCDIE | CTSIE);
0473         zport->regs[1] &= ~EXT_INT_ENAB;
0474     } else {
0475         /* DCD tracks RI and SYNC tracks DSR for the B side.  */
0476         if (!(zport->regs[15] & (DCDIE | SYNCIE)))
0477             zport->regs[1] &= ~EXT_INT_ENAB;
0478     }
0479 
0480     write_zsreg(zport, R15, zport->regs[15]);
0481     write_zsreg(zport, R1, zport->regs[1]);
0482     spin_unlock(&scc->zlock);
0483 }
0484 
0485 static void zs_enable_ms(struct uart_port *uport)
0486 {
0487     struct zs_port *zport = to_zport(uport);
0488     struct zs_scc *scc = zport->scc;
0489     struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
0490 
0491     if (zport == zport_a)
0492         return;
0493 
0494     spin_lock(&scc->zlock);
0495 
0496     /* Clear Ext interrupts if not being handled already.  */
0497     if (!(zport_a->regs[1] & EXT_INT_ENAB))
0498         write_zsreg(zport_a, R0, RES_EXT_INT);
0499 
0500     /* A-side DCD tracks RI and SYNC tracks DSR.  */
0501     zport_a->regs[1] |= EXT_INT_ENAB;
0502     zport_a->regs[15] |= DCDIE | SYNCIE;
0503 
0504     /* This-side DCD tracks DCD and CTS tracks CTS.  */
0505     zport->regs[15] |= DCDIE | CTSIE;
0506 
0507     zs_raw_xor_mctrl(zport);
0508 
0509     write_zsreg(zport_a, R1, zport_a->regs[1]);
0510     write_zsreg(zport_a, R15, zport_a->regs[15]);
0511     write_zsreg(zport, R15, zport->regs[15]);
0512     spin_unlock(&scc->zlock);
0513 }
0514 
0515 static void zs_break_ctl(struct uart_port *uport, int break_state)
0516 {
0517     struct zs_port *zport = to_zport(uport);
0518     struct zs_scc *scc = zport->scc;
0519     unsigned long flags;
0520 
0521     spin_lock_irqsave(&scc->zlock, flags);
0522     if (break_state == -1)
0523         zport->regs[5] |= SND_BRK;
0524     else
0525         zport->regs[5] &= ~SND_BRK;
0526     write_zsreg(zport, R5, zport->regs[5]);
0527     spin_unlock_irqrestore(&scc->zlock, flags);
0528 }
0529 
0530 
0531 /*
0532  * Interrupt handling routines.
0533  */
0534 #define Rx_BRK 0x0100           /* BREAK event software flag.  */
0535 #define Rx_SYS 0x0200           /* SysRq event software flag.  */
0536 
0537 static void zs_receive_chars(struct zs_port *zport)
0538 {
0539     struct uart_port *uport = &zport->port;
0540     struct zs_scc *scc = zport->scc;
0541     struct uart_icount *icount;
0542     unsigned int avail, status, ch, flag;
0543     int count;
0544 
0545     for (count = 16; count; count--) {
0546         spin_lock(&scc->zlock);
0547         avail = read_zsreg(zport, R0) & Rx_CH_AV;
0548         spin_unlock(&scc->zlock);
0549         if (!avail)
0550             break;
0551 
0552         spin_lock(&scc->zlock);
0553         status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
0554         ch = read_zsdata(zport);
0555         spin_unlock(&scc->zlock);
0556 
0557         flag = TTY_NORMAL;
0558 
0559         icount = &uport->icount;
0560         icount->rx++;
0561 
0562         /* Handle the null char got when BREAK is removed.  */
0563         if (!ch)
0564             status |= zport->tty_break;
0565         if (unlikely(status &
0566                  (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
0567             zport->tty_break = 0;
0568 
0569             /* Reset the error indication.  */
0570             if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
0571                 spin_lock(&scc->zlock);
0572                 write_zsreg(zport, R0, ERR_RES);
0573                 spin_unlock(&scc->zlock);
0574             }
0575 
0576             if (status & (Rx_SYS | Rx_BRK)) {
0577                 icount->brk++;
0578                 /* SysRq discards the null char.  */
0579                 if (status & Rx_SYS)
0580                     continue;
0581             } else if (status & FRM_ERR)
0582                 icount->frame++;
0583             else if (status & PAR_ERR)
0584                 icount->parity++;
0585             if (status & Rx_OVR)
0586                 icount->overrun++;
0587 
0588             status &= uport->read_status_mask;
0589             if (status & Rx_BRK)
0590                 flag = TTY_BREAK;
0591             else if (status & FRM_ERR)
0592                 flag = TTY_FRAME;
0593             else if (status & PAR_ERR)
0594                 flag = TTY_PARITY;
0595         }
0596 
0597         if (uart_handle_sysrq_char(uport, ch))
0598             continue;
0599 
0600         uart_insert_char(uport, status, Rx_OVR, ch, flag);
0601     }
0602 
0603     tty_flip_buffer_push(&uport->state->port);
0604 }
0605 
0606 static void zs_raw_transmit_chars(struct zs_port *zport)
0607 {
0608     struct circ_buf *xmit = &zport->port.state->xmit;
0609 
0610     /* XON/XOFF chars.  */
0611     if (zport->port.x_char) {
0612         write_zsdata(zport, zport->port.x_char);
0613         zport->port.icount.tx++;
0614         zport->port.x_char = 0;
0615         return;
0616     }
0617 
0618     /* If nothing to do or stopped or hardware stopped.  */
0619     if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
0620         zs_raw_stop_tx(zport);
0621         return;
0622     }
0623 
0624     /* Send char.  */
0625     write_zsdata(zport, xmit->buf[xmit->tail]);
0626     xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0627     zport->port.icount.tx++;
0628 
0629     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0630         uart_write_wakeup(&zport->port);
0631 
0632     /* Are we are done?  */
0633     if (uart_circ_empty(xmit))
0634         zs_raw_stop_tx(zport);
0635 }
0636 
0637 static void zs_transmit_chars(struct zs_port *zport)
0638 {
0639     struct zs_scc *scc = zport->scc;
0640 
0641     spin_lock(&scc->zlock);
0642     zs_raw_transmit_chars(zport);
0643     spin_unlock(&scc->zlock);
0644 }
0645 
0646 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
0647 {
0648     struct uart_port *uport = &zport->port;
0649     struct zs_scc *scc = zport->scc;
0650     unsigned int delta;
0651     u8 status, brk;
0652 
0653     spin_lock(&scc->zlock);
0654 
0655     /* Get status from Read Register 0.  */
0656     status = read_zsreg(zport, R0);
0657 
0658     if (zport->regs[15] & BRKIE) {
0659         brk = status & BRK_ABRT;
0660         if (brk && !zport->brk) {
0661             spin_unlock(&scc->zlock);
0662             if (uart_handle_break(uport))
0663                 zport->tty_break = Rx_SYS;
0664             else
0665                 zport->tty_break = Rx_BRK;
0666             spin_lock(&scc->zlock);
0667         }
0668         zport->brk = brk;
0669     }
0670 
0671     if (zport != zport_a) {
0672         delta = zs_raw_xor_mctrl(zport);
0673         spin_unlock(&scc->zlock);
0674 
0675         if (delta & TIOCM_CTS)
0676             uart_handle_cts_change(uport,
0677                            zport->mctrl & TIOCM_CTS);
0678         if (delta & TIOCM_CAR)
0679             uart_handle_dcd_change(uport,
0680                            zport->mctrl & TIOCM_CAR);
0681         if (delta & TIOCM_RNG)
0682             uport->icount.dsr++;
0683         if (delta & TIOCM_DSR)
0684             uport->icount.rng++;
0685 
0686         if (delta)
0687             wake_up_interruptible(&uport->state->port.delta_msr_wait);
0688 
0689         spin_lock(&scc->zlock);
0690     }
0691 
0692     /* Clear the status condition...  */
0693     write_zsreg(zport, R0, RES_EXT_INT);
0694 
0695     spin_unlock(&scc->zlock);
0696 }
0697 
0698 /*
0699  * This is the Z85C30 driver's generic interrupt routine.
0700  */
0701 static irqreturn_t zs_interrupt(int irq, void *dev_id)
0702 {
0703     struct zs_scc *scc = dev_id;
0704     struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
0705     struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
0706     irqreturn_t status = IRQ_NONE;
0707     u8 zs_intreg;
0708     int count;
0709 
0710     /*
0711      * NOTE: The read register 3, which holds the irq status,
0712      *       does so for both channels on each chip.  Although
0713      *       the status value itself must be read from the A
0714      *       channel and is only valid when read from channel A.
0715      *       Yes... broken hardware...
0716      */
0717     for (count = 16; count; count--) {
0718         spin_lock(&scc->zlock);
0719         zs_intreg = read_zsreg(zport_a, R3);
0720         spin_unlock(&scc->zlock);
0721         if (!zs_intreg)
0722             break;
0723 
0724         /*
0725          * We do not like losing characters, so we prioritise
0726          * interrupt sources a little bit differently than
0727          * the SCC would, was it allowed to.
0728          */
0729         if (zs_intreg & CHBRxIP)
0730             zs_receive_chars(zport_b);
0731         if (zs_intreg & CHARxIP)
0732             zs_receive_chars(zport_a);
0733         if (zs_intreg & CHBEXT)
0734             zs_status_handle(zport_b, zport_a);
0735         if (zs_intreg & CHAEXT)
0736             zs_status_handle(zport_a, zport_a);
0737         if (zs_intreg & CHBTxIP)
0738             zs_transmit_chars(zport_b);
0739         if (zs_intreg & CHATxIP)
0740             zs_transmit_chars(zport_a);
0741 
0742         status = IRQ_HANDLED;
0743     }
0744 
0745     return status;
0746 }
0747 
0748 
0749 /*
0750  * Finally, routines used to initialize the serial port.
0751  */
0752 static int zs_startup(struct uart_port *uport)
0753 {
0754     struct zs_port *zport = to_zport(uport);
0755     struct zs_scc *scc = zport->scc;
0756     unsigned long flags;
0757     int irq_guard;
0758     int ret;
0759 
0760     irq_guard = atomic_add_return(1, &scc->irq_guard);
0761     if (irq_guard == 1) {
0762         ret = request_irq(zport->port.irq, zs_interrupt,
0763                   IRQF_SHARED, "scc", scc);
0764         if (ret) {
0765             atomic_add(-1, &scc->irq_guard);
0766             printk(KERN_ERR "zs: can't get irq %d\n",
0767                    zport->port.irq);
0768             return ret;
0769         }
0770     }
0771 
0772     spin_lock_irqsave(&scc->zlock, flags);
0773 
0774     /* Clear the receive FIFO.  */
0775     zs_receive_drain(zport);
0776 
0777     /* Clear the interrupt registers.  */
0778     write_zsreg(zport, R0, ERR_RES);
0779     write_zsreg(zport, R0, RES_Tx_P);
0780     /* But Ext only if not being handled already.  */
0781     if (!(zport->regs[1] & EXT_INT_ENAB))
0782         write_zsreg(zport, R0, RES_EXT_INT);
0783 
0784     /* Finally, enable sequencing and interrupts.  */
0785     zport->regs[1] &= ~RxINT_MASK;
0786     zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
0787     zport->regs[3] |= RxENABLE;
0788     zport->regs[15] |= BRKIE;
0789     write_zsreg(zport, R1, zport->regs[1]);
0790     write_zsreg(zport, R3, zport->regs[3]);
0791     write_zsreg(zport, R5, zport->regs[5]);
0792     write_zsreg(zport, R15, zport->regs[15]);
0793 
0794     /* Record the current state of RR0.  */
0795     zport->mctrl = zs_raw_get_mctrl(zport);
0796     zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
0797 
0798     zport->tx_stopped = 1;
0799 
0800     spin_unlock_irqrestore(&scc->zlock, flags);
0801 
0802     return 0;
0803 }
0804 
0805 static void zs_shutdown(struct uart_port *uport)
0806 {
0807     struct zs_port *zport = to_zport(uport);
0808     struct zs_scc *scc = zport->scc;
0809     unsigned long flags;
0810     int irq_guard;
0811 
0812     spin_lock_irqsave(&scc->zlock, flags);
0813 
0814     zport->regs[3] &= ~RxENABLE;
0815     write_zsreg(zport, R5, zport->regs[5]);
0816     write_zsreg(zport, R3, zport->regs[3]);
0817 
0818     spin_unlock_irqrestore(&scc->zlock, flags);
0819 
0820     irq_guard = atomic_add_return(-1, &scc->irq_guard);
0821     if (!irq_guard)
0822         free_irq(zport->port.irq, scc);
0823 }
0824 
0825 
0826 static void zs_reset(struct zs_port *zport)
0827 {
0828     struct zs_scc *scc = zport->scc;
0829     int irq;
0830     unsigned long flags;
0831 
0832     spin_lock_irqsave(&scc->zlock, flags);
0833     irq = !irqs_disabled_flags(flags);
0834     if (!scc->initialised) {
0835         /* Reset the pointer first, just in case...  */
0836         read_zsreg(zport, R0);
0837         /* And let the current transmission finish.  */
0838         zs_line_drain(zport, irq);
0839         write_zsreg(zport, R9, FHWRES);
0840         udelay(10);
0841         write_zsreg(zport, R9, 0);
0842         scc->initialised = 1;
0843     }
0844     load_zsregs(zport, zport->regs, irq);
0845     spin_unlock_irqrestore(&scc->zlock, flags);
0846 }
0847 
0848 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
0849                struct ktermios *old_termios)
0850 {
0851     struct zs_port *zport = to_zport(uport);
0852     struct zs_scc *scc = zport->scc;
0853     struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
0854     int irq;
0855     unsigned int baud, brg;
0856     unsigned long flags;
0857 
0858     spin_lock_irqsave(&scc->zlock, flags);
0859     irq = !irqs_disabled_flags(flags);
0860 
0861     /* Byte size.  */
0862     zport->regs[3] &= ~RxNBITS_MASK;
0863     zport->regs[5] &= ~TxNBITS_MASK;
0864     switch (termios->c_cflag & CSIZE) {
0865     case CS5:
0866         zport->regs[3] |= Rx5;
0867         zport->regs[5] |= Tx5;
0868         break;
0869     case CS6:
0870         zport->regs[3] |= Rx6;
0871         zport->regs[5] |= Tx6;
0872         break;
0873     case CS7:
0874         zport->regs[3] |= Rx7;
0875         zport->regs[5] |= Tx7;
0876         break;
0877     case CS8:
0878     default:
0879         zport->regs[3] |= Rx8;
0880         zport->regs[5] |= Tx8;
0881         break;
0882     }
0883 
0884     /* Parity and stop bits.  */
0885     zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
0886     if (termios->c_cflag & CSTOPB)
0887         zport->regs[4] |= SB2;
0888     else
0889         zport->regs[4] |= SB1;
0890     if (termios->c_cflag & PARENB)
0891         zport->regs[4] |= PAR_ENA;
0892     if (!(termios->c_cflag & PARODD))
0893         zport->regs[4] |= PAR_EVEN;
0894     switch (zport->clk_mode) {
0895     case 64:
0896         zport->regs[4] |= X64CLK;
0897         break;
0898     case 32:
0899         zport->regs[4] |= X32CLK;
0900         break;
0901     case 16:
0902         zport->regs[4] |= X16CLK;
0903         break;
0904     case 1:
0905         zport->regs[4] |= X1CLK;
0906         break;
0907     default:
0908         BUG();
0909     }
0910 
0911     baud = uart_get_baud_rate(uport, termios, old_termios, 0,
0912                   uport->uartclk / zport->clk_mode / 4);
0913 
0914     brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
0915     zport->regs[12] = brg & 0xff;
0916     zport->regs[13] = (brg >> 8) & 0xff;
0917 
0918     uart_update_timeout(uport, termios->c_cflag, baud);
0919 
0920     uport->read_status_mask = Rx_OVR;
0921     if (termios->c_iflag & INPCK)
0922         uport->read_status_mask |= FRM_ERR | PAR_ERR;
0923     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0924         uport->read_status_mask |= Rx_BRK;
0925 
0926     uport->ignore_status_mask = 0;
0927     if (termios->c_iflag & IGNPAR)
0928         uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
0929     if (termios->c_iflag & IGNBRK) {
0930         uport->ignore_status_mask |= Rx_BRK;
0931         if (termios->c_iflag & IGNPAR)
0932             uport->ignore_status_mask |= Rx_OVR;
0933     }
0934 
0935     if (termios->c_cflag & CREAD)
0936         zport->regs[3] |= RxENABLE;
0937     else
0938         zport->regs[3] &= ~RxENABLE;
0939 
0940     if (zport != zport_a) {
0941         if (!(termios->c_cflag & CLOCAL)) {
0942             zport->regs[15] |= DCDIE;
0943         } else
0944             zport->regs[15] &= ~DCDIE;
0945         if (termios->c_cflag & CRTSCTS) {
0946             zport->regs[15] |= CTSIE;
0947         } else
0948             zport->regs[15] &= ~CTSIE;
0949         zs_raw_xor_mctrl(zport);
0950     }
0951 
0952     /* Load up the new values.  */
0953     load_zsregs(zport, zport->regs, irq);
0954 
0955     spin_unlock_irqrestore(&scc->zlock, flags);
0956 }
0957 
0958 /*
0959  * Hack alert!
0960  * Required solely so that the initial PROM-based console
0961  * works undisturbed in parallel with this one.
0962  */
0963 static void zs_pm(struct uart_port *uport, unsigned int state,
0964           unsigned int oldstate)
0965 {
0966     struct zs_port *zport = to_zport(uport);
0967 
0968     if (state < 3)
0969         zport->regs[5] |= TxENAB;
0970     else
0971         zport->regs[5] &= ~TxENAB;
0972     write_zsreg(zport, R5, zport->regs[5]);
0973 }
0974 
0975 
0976 static const char *zs_type(struct uart_port *uport)
0977 {
0978     return "Z85C30 SCC";
0979 }
0980 
0981 static void zs_release_port(struct uart_port *uport)
0982 {
0983     iounmap(uport->membase);
0984     uport->membase = NULL;
0985     release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
0986 }
0987 
0988 static int zs_map_port(struct uart_port *uport)
0989 {
0990     if (!uport->membase)
0991         uport->membase = ioremap(uport->mapbase,
0992                          ZS_CHAN_IO_SIZE);
0993     if (!uport->membase) {
0994         printk(KERN_ERR "zs: Cannot map MMIO\n");
0995         return -ENOMEM;
0996     }
0997     return 0;
0998 }
0999 
1000 static int zs_request_port(struct uart_port *uport)
1001 {
1002     int ret;
1003 
1004     if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
1005         printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
1006         return -EBUSY;
1007     }
1008     ret = zs_map_port(uport);
1009     if (ret) {
1010         release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
1011         return ret;
1012     }
1013     return 0;
1014 }
1015 
1016 static void zs_config_port(struct uart_port *uport, int flags)
1017 {
1018     struct zs_port *zport = to_zport(uport);
1019 
1020     if (flags & UART_CONFIG_TYPE) {
1021         if (zs_request_port(uport))
1022             return;
1023 
1024         uport->type = PORT_ZS;
1025 
1026         zs_reset(zport);
1027     }
1028 }
1029 
1030 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1031 {
1032     struct zs_port *zport = to_zport(uport);
1033     int ret = 0;
1034 
1035     if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1036         ret = -EINVAL;
1037     if (ser->irq != uport->irq)
1038         ret = -EINVAL;
1039     if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1040         ret = -EINVAL;
1041     return ret;
1042 }
1043 
1044 
1045 static const struct uart_ops zs_ops = {
1046     .tx_empty   = zs_tx_empty,
1047     .set_mctrl  = zs_set_mctrl,
1048     .get_mctrl  = zs_get_mctrl,
1049     .stop_tx    = zs_stop_tx,
1050     .start_tx   = zs_start_tx,
1051     .stop_rx    = zs_stop_rx,
1052     .enable_ms  = zs_enable_ms,
1053     .break_ctl  = zs_break_ctl,
1054     .startup    = zs_startup,
1055     .shutdown   = zs_shutdown,
1056     .set_termios    = zs_set_termios,
1057     .pm     = zs_pm,
1058     .type       = zs_type,
1059     .release_port   = zs_release_port,
1060     .request_port   = zs_request_port,
1061     .config_port    = zs_config_port,
1062     .verify_port    = zs_verify_port,
1063 };
1064 
1065 /*
1066  * Initialize Z85C30 port structures.
1067  */
1068 static int __init zs_probe_sccs(void)
1069 {
1070     static int probed;
1071     struct zs_parms zs_parms;
1072     int chip, side, irq;
1073     int n_chips = 0;
1074     int i;
1075 
1076     if (probed)
1077         return 0;
1078 
1079     irq = dec_interrupt[DEC_IRQ_SCC0];
1080     if (irq >= 0) {
1081         zs_parms.scc[n_chips] = IOASIC_SCC0;
1082         zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1083         n_chips++;
1084     }
1085     irq = dec_interrupt[DEC_IRQ_SCC1];
1086     if (irq >= 0) {
1087         zs_parms.scc[n_chips] = IOASIC_SCC1;
1088         zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1089         n_chips++;
1090     }
1091     if (!n_chips)
1092         return -ENXIO;
1093 
1094     probed = 1;
1095 
1096     for (chip = 0; chip < n_chips; chip++) {
1097         spin_lock_init(&zs_sccs[chip].zlock);
1098         for (side = 0; side < ZS_NUM_CHAN; side++) {
1099             struct zs_port *zport = &zs_sccs[chip].zport[side];
1100             struct uart_port *uport = &zport->port;
1101 
1102             zport->scc  = &zs_sccs[chip];
1103             zport->clk_mode = 16;
1104 
1105             uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);
1106             uport->irq  = zs_parms.irq[chip];
1107             uport->uartclk  = ZS_CLOCK;
1108             uport->fifosize = 1;
1109             uport->iotype   = UPIO_MEM;
1110             uport->flags    = UPF_BOOT_AUTOCONF;
1111             uport->ops  = &zs_ops;
1112             uport->line = chip * ZS_NUM_CHAN + side;
1113             uport->mapbase  = dec_kn_slot_base +
1114                       zs_parms.scc[chip] +
1115                       (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1116 
1117             for (i = 0; i < ZS_NUM_REGS; i++)
1118                 zport->regs[i] = zs_init_regs[i];
1119         }
1120     }
1121 
1122     return 0;
1123 }
1124 
1125 
1126 #ifdef CONFIG_SERIAL_ZS_CONSOLE
1127 static void zs_console_putchar(struct uart_port *uport, unsigned char ch)
1128 {
1129     struct zs_port *zport = to_zport(uport);
1130     struct zs_scc *scc = zport->scc;
1131     int irq;
1132     unsigned long flags;
1133 
1134     spin_lock_irqsave(&scc->zlock, flags);
1135     irq = !irqs_disabled_flags(flags);
1136     if (zs_transmit_drain(zport, irq))
1137         write_zsdata(zport, ch);
1138     spin_unlock_irqrestore(&scc->zlock, flags);
1139 }
1140 
1141 /*
1142  * Print a string to the serial port trying not to disturb
1143  * any possible real use of the port...
1144  */
1145 static void zs_console_write(struct console *co, const char *s,
1146                  unsigned int count)
1147 {
1148     int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1149     struct zs_port *zport = &zs_sccs[chip].zport[side];
1150     struct zs_scc *scc = zport->scc;
1151     unsigned long flags;
1152     u8 txint, txenb;
1153     int irq;
1154 
1155     /* Disable transmit interrupts and enable the transmitter. */
1156     spin_lock_irqsave(&scc->zlock, flags);
1157     txint = zport->regs[1];
1158     txenb = zport->regs[5];
1159     if (txint & TxINT_ENAB) {
1160         zport->regs[1] = txint & ~TxINT_ENAB;
1161         write_zsreg(zport, R1, zport->regs[1]);
1162     }
1163     if (!(txenb & TxENAB)) {
1164         zport->regs[5] = txenb | TxENAB;
1165         write_zsreg(zport, R5, zport->regs[5]);
1166     }
1167     spin_unlock_irqrestore(&scc->zlock, flags);
1168 
1169     uart_console_write(&zport->port, s, count, zs_console_putchar);
1170 
1171     /* Restore transmit interrupts and the transmitter enable. */
1172     spin_lock_irqsave(&scc->zlock, flags);
1173     irq = !irqs_disabled_flags(flags);
1174     zs_line_drain(zport, irq);
1175     if (!(txenb & TxENAB)) {
1176         zport->regs[5] &= ~TxENAB;
1177         write_zsreg(zport, R5, zport->regs[5]);
1178     }
1179     if (txint & TxINT_ENAB) {
1180         zport->regs[1] |= TxINT_ENAB;
1181         write_zsreg(zport, R1, zport->regs[1]);
1182 
1183         /* Resume any transmission as the TxIP bit won't be set.  */
1184         if (!zport->tx_stopped)
1185             zs_raw_transmit_chars(zport);
1186     }
1187     spin_unlock_irqrestore(&scc->zlock, flags);
1188 }
1189 
1190 /*
1191  * Setup serial console baud/bits/parity.  We do two things here:
1192  * - construct a cflag setting for the first uart_open()
1193  * - initialise the serial port
1194  * Return non-zero if we didn't find a serial port.
1195  */
1196 static int __init zs_console_setup(struct console *co, char *options)
1197 {
1198     int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1199     struct zs_port *zport = &zs_sccs[chip].zport[side];
1200     struct uart_port *uport = &zport->port;
1201     int baud = 9600;
1202     int bits = 8;
1203     int parity = 'n';
1204     int flow = 'n';
1205     int ret;
1206 
1207     ret = zs_map_port(uport);
1208     if (ret)
1209         return ret;
1210 
1211     zs_reset(zport);
1212     zs_pm(uport, 0, -1);
1213 
1214     if (options)
1215         uart_parse_options(options, &baud, &parity, &bits, &flow);
1216     return uart_set_options(uport, co, baud, parity, bits, flow);
1217 }
1218 
1219 static struct uart_driver zs_reg;
1220 static struct console zs_console = {
1221     .name   = "ttyS",
1222     .write  = zs_console_write,
1223     .device = uart_console_device,
1224     .setup  = zs_console_setup,
1225     .flags  = CON_PRINTBUFFER,
1226     .index  = -1,
1227     .data   = &zs_reg,
1228 };
1229 
1230 /*
1231  *  Register console.
1232  */
1233 static int __init zs_serial_console_init(void)
1234 {
1235     int ret;
1236 
1237     ret = zs_probe_sccs();
1238     if (ret)
1239         return ret;
1240     register_console(&zs_console);
1241 
1242     return 0;
1243 }
1244 
1245 console_initcall(zs_serial_console_init);
1246 
1247 #define SERIAL_ZS_CONSOLE   &zs_console
1248 #else
1249 #define SERIAL_ZS_CONSOLE   NULL
1250 #endif /* CONFIG_SERIAL_ZS_CONSOLE */
1251 
1252 static struct uart_driver zs_reg = {
1253     .owner          = THIS_MODULE,
1254     .driver_name        = "serial",
1255     .dev_name       = "ttyS",
1256     .major          = TTY_MAJOR,
1257     .minor          = 64,
1258     .nr         = ZS_NUM_SCCS * ZS_NUM_CHAN,
1259     .cons           = SERIAL_ZS_CONSOLE,
1260 };
1261 
1262 /* zs_init inits the driver. */
1263 static int __init zs_init(void)
1264 {
1265     int i, ret;
1266 
1267     pr_info("%s%s\n", zs_name, zs_version);
1268 
1269     /* Find out how many Z85C30 SCCs we have.  */
1270     ret = zs_probe_sccs();
1271     if (ret)
1272         return ret;
1273 
1274     ret = uart_register_driver(&zs_reg);
1275     if (ret)
1276         return ret;
1277 
1278     for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1279         struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1280         struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1281         struct uart_port *uport = &zport->port;
1282 
1283         if (zport->scc)
1284             uart_add_one_port(&zs_reg, uport);
1285     }
1286 
1287     return 0;
1288 }
1289 
1290 static void __exit zs_exit(void)
1291 {
1292     int i;
1293 
1294     for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1295         struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1296         struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1297         struct uart_port *uport = &zport->port;
1298 
1299         if (zport->scc)
1300             uart_remove_one_port(&zs_reg, uport);
1301     }
1302 
1303     uart_unregister_driver(&zs_reg);
1304 }
1305 
1306 module_init(zs_init);
1307 module_exit(zs_exit);
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