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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
0004  *
0005  * Based on msm_serial.c, which is:
0006  * Copyright (C) 2007 Google, Inc.
0007  * Author: Robert Love <rlove@google.com>
0008  */
0009 
0010 #include <linux/hrtimer.h>
0011 #include <linux/delay.h>
0012 #include <linux/io.h>
0013 #include <linux/ioport.h>
0014 #include <linux/irq.h>
0015 #include <linux/init.h>
0016 #include <linux/console.h>
0017 #include <linux/tty.h>
0018 #include <linux/tty_flip.h>
0019 #include <linux/serial_core.h>
0020 #include <linux/serial.h>
0021 #include <linux/slab.h>
0022 #include <linux/clk.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/err.h>
0026 
0027 /*
0028  * UART Register offsets
0029  */
0030 
0031 #define VT8500_URTDR        0x0000  /* Transmit data */
0032 #define VT8500_URRDR        0x0004  /* Receive data */
0033 #define VT8500_URDIV        0x0008  /* Clock/Baud rate divisor */
0034 #define VT8500_URLCR        0x000C  /* Line control */
0035 #define VT8500_URICR        0x0010  /* IrDA control */
0036 #define VT8500_URIER        0x0014  /* Interrupt enable */
0037 #define VT8500_URISR        0x0018  /* Interrupt status */
0038 #define VT8500_URUSR        0x001c  /* UART status */
0039 #define VT8500_URFCR        0x0020  /* FIFO control */
0040 #define VT8500_URFIDX       0x0024  /* FIFO index */
0041 #define VT8500_URBKR        0x0028  /* Break signal count */
0042 #define VT8500_URTOD        0x002c  /* Time out divisor */
0043 #define VT8500_TXFIFO       0x1000  /* Transmit FIFO (16x8) */
0044 #define VT8500_RXFIFO       0x1020  /* Receive FIFO (16x10) */
0045 
0046 /*
0047  * Interrupt enable and status bits
0048  */
0049 
0050 #define TXDE    (1 << 0)    /* Tx Data empty */
0051 #define RXDF    (1 << 1)    /* Rx Data full */
0052 #define TXFAE   (1 << 2)    /* Tx FIFO almost empty */
0053 #define TXFE    (1 << 3)    /* Tx FIFO empty */
0054 #define RXFAF   (1 << 4)    /* Rx FIFO almost full */
0055 #define RXFF    (1 << 5)    /* Rx FIFO full */
0056 #define TXUDR   (1 << 6)    /* Tx underrun */
0057 #define RXOVER  (1 << 7)    /* Rx overrun */
0058 #define PER (1 << 8)    /* Parity error */
0059 #define FER (1 << 9)    /* Frame error */
0060 #define TCTS    (1 << 10)   /* Toggle of CTS */
0061 #define RXTOUT  (1 << 11)   /* Rx timeout */
0062 #define BKDONE  (1 << 12)   /* Break signal done */
0063 #define ERR (1 << 13)   /* AHB error response */
0064 
0065 #define RX_FIFO_INTS    (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
0066 #define TX_FIFO_INTS    (TXFAE | TXFE | TXUDR)
0067 
0068 /*
0069  * Line control bits
0070  */
0071 
0072 #define VT8500_TXEN (1 << 0)    /* Enable transmit logic */
0073 #define VT8500_RXEN (1 << 1)    /* Enable receive logic */
0074 #define VT8500_CS8  (1 << 2)    /* 8-bit data length (vs. 7-bit) */
0075 #define VT8500_CSTOPB   (1 << 3)    /* 2 stop bits (vs. 1) */
0076 #define VT8500_PARENB   (1 << 4)    /* Enable parity */
0077 #define VT8500_PARODD   (1 << 5)    /* Odd parity (vs. even) */
0078 #define VT8500_RTS  (1 << 6)    /* Ready to send */
0079 #define VT8500_LOOPBK   (1 << 7)    /* Enable internal loopback */
0080 #define VT8500_DMA  (1 << 8)    /* Enable DMA mode (needs FIFO) */
0081 #define VT8500_BREAK    (1 << 9)    /* Initiate break signal */
0082 #define VT8500_PSLVERR  (1 << 10)   /* APB error upon empty RX FIFO read */
0083 #define VT8500_SWRTSCTS (1 << 11)   /* Software-controlled RTS/CTS */
0084 
0085 /*
0086  * Capability flags (driver-internal)
0087  */
0088 
0089 #define VT8500_HAS_SWRTSCTS_SWITCH  (1 << 1)
0090 
0091 #define VT8500_RECOMMENDED_CLK      12000000
0092 #define VT8500_OVERSAMPLING_DIVISOR 13
0093 #define VT8500_MAX_PORTS    6
0094 
0095 struct vt8500_port {
0096     struct uart_port    uart;
0097     char            name[16];
0098     struct clk      *clk;
0099     unsigned int        clk_predivisor;
0100     unsigned int        ier;
0101     unsigned int        vt8500_uart_flags;
0102 };
0103 
0104 /*
0105  * we use this variable to keep track of which ports
0106  * have been allocated as we can't use pdev->id in
0107  * devicetree
0108  */
0109 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
0110 
0111 static inline void vt8500_write(struct uart_port *port, unsigned int val,
0112                  unsigned int off)
0113 {
0114     writel(val, port->membase + off);
0115 }
0116 
0117 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
0118 {
0119     return readl(port->membase + off);
0120 }
0121 
0122 static void vt8500_stop_tx(struct uart_port *port)
0123 {
0124     struct vt8500_port *vt8500_port = container_of(port,
0125                                struct vt8500_port,
0126                                uart);
0127 
0128     vt8500_port->ier &= ~TX_FIFO_INTS;
0129     vt8500_write(port, vt8500_port->ier, VT8500_URIER);
0130 }
0131 
0132 static void vt8500_stop_rx(struct uart_port *port)
0133 {
0134     struct vt8500_port *vt8500_port = container_of(port,
0135                                struct vt8500_port,
0136                                uart);
0137 
0138     vt8500_port->ier &= ~RX_FIFO_INTS;
0139     vt8500_write(port, vt8500_port->ier, VT8500_URIER);
0140 }
0141 
0142 static void vt8500_enable_ms(struct uart_port *port)
0143 {
0144     struct vt8500_port *vt8500_port = container_of(port,
0145                                struct vt8500_port,
0146                                uart);
0147 
0148     vt8500_port->ier |= TCTS;
0149     vt8500_write(port, vt8500_port->ier, VT8500_URIER);
0150 }
0151 
0152 static void handle_rx(struct uart_port *port)
0153 {
0154     struct tty_port *tport = &port->state->port;
0155 
0156     /*
0157      * Handle overrun
0158      */
0159     if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
0160         port->icount.overrun++;
0161         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0162     }
0163 
0164     /* and now the main RX loop */
0165     while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
0166         unsigned int c;
0167         char flag = TTY_NORMAL;
0168 
0169         c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
0170 
0171         /* Mask conditions we're ignorning. */
0172         c &= ~port->read_status_mask;
0173 
0174         if (c & FER) {
0175             port->icount.frame++;
0176             flag = TTY_FRAME;
0177         } else if (c & PER) {
0178             port->icount.parity++;
0179             flag = TTY_PARITY;
0180         }
0181         port->icount.rx++;
0182 
0183         if (!uart_handle_sysrq_char(port, c))
0184             tty_insert_flip_char(tport, c, flag);
0185     }
0186 
0187     tty_flip_buffer_push(tport);
0188 }
0189 
0190 static void handle_tx(struct uart_port *port)
0191 {
0192     struct circ_buf *xmit = &port->state->xmit;
0193 
0194     if (port->x_char) {
0195         writeb(port->x_char, port->membase + VT8500_TXFIFO);
0196         port->icount.tx++;
0197         port->x_char = 0;
0198     }
0199     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0200         vt8500_stop_tx(port);
0201         return;
0202     }
0203 
0204     while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
0205         if (uart_circ_empty(xmit))
0206             break;
0207 
0208         writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
0209 
0210         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0211         port->icount.tx++;
0212     }
0213 
0214     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0215         uart_write_wakeup(port);
0216 
0217     if (uart_circ_empty(xmit))
0218         vt8500_stop_tx(port);
0219 }
0220 
0221 static void vt8500_start_tx(struct uart_port *port)
0222 {
0223     struct vt8500_port *vt8500_port = container_of(port,
0224                                struct vt8500_port,
0225                                uart);
0226 
0227     vt8500_port->ier &= ~TX_FIFO_INTS;
0228     vt8500_write(port, vt8500_port->ier, VT8500_URIER);
0229     handle_tx(port);
0230     vt8500_port->ier |= TX_FIFO_INTS;
0231     vt8500_write(port, vt8500_port->ier, VT8500_URIER);
0232 }
0233 
0234 static void handle_delta_cts(struct uart_port *port)
0235 {
0236     port->icount.cts++;
0237     wake_up_interruptible(&port->state->port.delta_msr_wait);
0238 }
0239 
0240 static irqreturn_t vt8500_irq(int irq, void *dev_id)
0241 {
0242     struct uart_port *port = dev_id;
0243     unsigned long isr;
0244 
0245     spin_lock(&port->lock);
0246     isr = vt8500_read(port, VT8500_URISR);
0247 
0248     /* Acknowledge active status bits */
0249     vt8500_write(port, isr, VT8500_URISR);
0250 
0251     if (isr & RX_FIFO_INTS)
0252         handle_rx(port);
0253     if (isr & TX_FIFO_INTS)
0254         handle_tx(port);
0255     if (isr & TCTS)
0256         handle_delta_cts(port);
0257 
0258     spin_unlock(&port->lock);
0259 
0260     return IRQ_HANDLED;
0261 }
0262 
0263 static unsigned int vt8500_tx_empty(struct uart_port *port)
0264 {
0265     return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
0266                         TIOCSER_TEMT : 0;
0267 }
0268 
0269 static unsigned int vt8500_get_mctrl(struct uart_port *port)
0270 {
0271     unsigned int usr;
0272 
0273     usr = vt8500_read(port, VT8500_URUSR);
0274     if (usr & (1 << 4))
0275         return TIOCM_CTS;
0276     else
0277         return 0;
0278 }
0279 
0280 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
0281 {
0282     unsigned int lcr = vt8500_read(port, VT8500_URLCR);
0283 
0284     if (mctrl & TIOCM_RTS)
0285         lcr |= VT8500_RTS;
0286     else
0287         lcr &= ~VT8500_RTS;
0288 
0289     vt8500_write(port, lcr, VT8500_URLCR);
0290 }
0291 
0292 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
0293 {
0294     if (break_ctl)
0295         vt8500_write(port,
0296                  vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
0297                  VT8500_URLCR);
0298 }
0299 
0300 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
0301 {
0302     struct vt8500_port *vt8500_port =
0303             container_of(port, struct vt8500_port, uart);
0304     unsigned long div;
0305     unsigned int loops = 1000;
0306 
0307     div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
0308     div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
0309 
0310     /* Effective baud rate */
0311     baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
0312 
0313     while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
0314         cpu_relax();
0315 
0316     vt8500_write(port, div, VT8500_URDIV);
0317 
0318     /* Break signal timing depends on baud rate, update accordingly */
0319     vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
0320 
0321     return baud;
0322 }
0323 
0324 static int vt8500_startup(struct uart_port *port)
0325 {
0326     struct vt8500_port *vt8500_port =
0327             container_of(port, struct vt8500_port, uart);
0328     int ret;
0329 
0330     snprintf(vt8500_port->name, sizeof(vt8500_port->name),
0331          "vt8500_serial%d", port->line);
0332 
0333     ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
0334               vt8500_port->name, port);
0335     if (unlikely(ret))
0336         return ret;
0337 
0338     vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
0339 
0340     return 0;
0341 }
0342 
0343 static void vt8500_shutdown(struct uart_port *port)
0344 {
0345     struct vt8500_port *vt8500_port =
0346             container_of(port, struct vt8500_port, uart);
0347 
0348     vt8500_port->ier = 0;
0349 
0350     /* disable interrupts and FIFOs */
0351     vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
0352     vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
0353     free_irq(port->irq, port);
0354 }
0355 
0356 static void vt8500_set_termios(struct uart_port *port,
0357                    struct ktermios *termios,
0358                    struct ktermios *old)
0359 {
0360     struct vt8500_port *vt8500_port =
0361             container_of(port, struct vt8500_port, uart);
0362     unsigned long flags;
0363     unsigned int baud, lcr;
0364     unsigned int loops = 1000;
0365 
0366     spin_lock_irqsave(&port->lock, flags);
0367 
0368     /* calculate and set baud rate */
0369     baud = uart_get_baud_rate(port, termios, old, 900, 921600);
0370     baud = vt8500_set_baud_rate(port, baud);
0371     if (tty_termios_baud_rate(termios))
0372         tty_termios_encode_baud_rate(termios, baud, baud);
0373 
0374     /* calculate parity */
0375     lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
0376     lcr &= ~(VT8500_PARENB | VT8500_PARODD);
0377     if (termios->c_cflag & PARENB) {
0378         lcr |= VT8500_PARENB;
0379         termios->c_cflag &= ~CMSPAR;
0380         if (termios->c_cflag & PARODD)
0381             lcr |= VT8500_PARODD;
0382     }
0383 
0384     /* calculate bits per char */
0385     lcr &= ~VT8500_CS8;
0386     switch (termios->c_cflag & CSIZE) {
0387     case CS7:
0388         break;
0389     case CS8:
0390     default:
0391         lcr |= VT8500_CS8;
0392         termios->c_cflag &= ~CSIZE;
0393         termios->c_cflag |= CS8;
0394         break;
0395     }
0396 
0397     /* calculate stop bits */
0398     lcr &= ~VT8500_CSTOPB;
0399     if (termios->c_cflag & CSTOPB)
0400         lcr |= VT8500_CSTOPB;
0401 
0402     lcr &= ~VT8500_SWRTSCTS;
0403     if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
0404         lcr |= VT8500_SWRTSCTS;
0405 
0406     /* set parity, bits per char, and stop bit */
0407     vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
0408 
0409     /* Configure status bits to ignore based on termio flags. */
0410     port->read_status_mask = 0;
0411     if (termios->c_iflag & IGNPAR)
0412         port->read_status_mask = FER | PER;
0413 
0414     uart_update_timeout(port, termios->c_cflag, baud);
0415 
0416     /* Reset FIFOs */
0417     vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
0418     while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
0419                             && --loops)
0420         cpu_relax();
0421 
0422     /* Every possible FIFO-related interrupt */
0423     vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
0424 
0425     /*
0426      * CTS flow control
0427      */
0428     if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
0429         vt8500_port->ier |= TCTS;
0430 
0431     vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
0432     vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
0433 
0434     spin_unlock_irqrestore(&port->lock, flags);
0435 }
0436 
0437 static const char *vt8500_type(struct uart_port *port)
0438 {
0439     struct vt8500_port *vt8500_port =
0440             container_of(port, struct vt8500_port, uart);
0441     return vt8500_port->name;
0442 }
0443 
0444 static void vt8500_release_port(struct uart_port *port)
0445 {
0446 }
0447 
0448 static int vt8500_request_port(struct uart_port *port)
0449 {
0450     return 0;
0451 }
0452 
0453 static void vt8500_config_port(struct uart_port *port, int flags)
0454 {
0455     port->type = PORT_VT8500;
0456 }
0457 
0458 static int vt8500_verify_port(struct uart_port *port,
0459                   struct serial_struct *ser)
0460 {
0461     if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
0462         return -EINVAL;
0463     if (unlikely(port->irq != ser->irq))
0464         return -EINVAL;
0465     return 0;
0466 }
0467 
0468 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
0469 static struct uart_driver vt8500_uart_driver;
0470 
0471 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
0472 
0473 static void wait_for_xmitr(struct uart_port *port)
0474 {
0475     unsigned int status, tmout = 10000;
0476 
0477     /* Wait up to 10ms for the character(s) to be sent. */
0478     do {
0479         status = vt8500_read(port, VT8500_URFIDX);
0480 
0481         if (--tmout == 0)
0482             break;
0483         udelay(1);
0484     } while (status & 0x10);
0485 }
0486 
0487 static void vt8500_console_putchar(struct uart_port *port, unsigned char c)
0488 {
0489     wait_for_xmitr(port);
0490     writeb(c, port->membase + VT8500_TXFIFO);
0491 }
0492 
0493 static void vt8500_console_write(struct console *co, const char *s,
0494                   unsigned int count)
0495 {
0496     struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
0497     unsigned long ier;
0498 
0499     BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
0500 
0501     ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
0502     vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
0503 
0504     uart_console_write(&vt8500_port->uart, s, count,
0505                vt8500_console_putchar);
0506 
0507     /*
0508      *  Finally, wait for transmitter to become empty
0509      *  and switch back to FIFO
0510      */
0511     wait_for_xmitr(&vt8500_port->uart);
0512     vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
0513 }
0514 
0515 static int __init vt8500_console_setup(struct console *co, char *options)
0516 {
0517     struct vt8500_port *vt8500_port;
0518     int baud = 9600;
0519     int bits = 8;
0520     int parity = 'n';
0521     int flow = 'n';
0522 
0523     if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
0524         return -ENXIO;
0525 
0526     vt8500_port = vt8500_uart_ports[co->index];
0527 
0528     if (!vt8500_port)
0529         return -ENODEV;
0530 
0531     if (options)
0532         uart_parse_options(options, &baud, &parity, &bits, &flow);
0533 
0534     return uart_set_options(&vt8500_port->uart,
0535                  co, baud, parity, bits, flow);
0536 }
0537 
0538 static struct console vt8500_console = {
0539     .name = "ttyWMT",
0540     .write = vt8500_console_write,
0541     .device = uart_console_device,
0542     .setup = vt8500_console_setup,
0543     .flags = CON_PRINTBUFFER,
0544     .index = -1,
0545     .data = &vt8500_uart_driver,
0546 };
0547 
0548 #define VT8500_CONSOLE  (&vt8500_console)
0549 
0550 #else
0551 #define VT8500_CONSOLE  NULL
0552 #endif
0553 
0554 #ifdef CONFIG_CONSOLE_POLL
0555 static int vt8500_get_poll_char(struct uart_port *port)
0556 {
0557     unsigned int status = vt8500_read(port, VT8500_URFIDX);
0558 
0559     if (!(status & 0x1f00))
0560         return NO_POLL_CHAR;
0561 
0562     return vt8500_read(port, VT8500_RXFIFO) & 0xff;
0563 }
0564 
0565 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
0566 {
0567     unsigned int status, tmout = 10000;
0568 
0569     do {
0570         status = vt8500_read(port, VT8500_URFIDX);
0571 
0572         if (--tmout == 0)
0573             break;
0574         udelay(1);
0575     } while (status & 0x10);
0576 
0577     vt8500_write(port, c, VT8500_TXFIFO);
0578 }
0579 #endif
0580 
0581 static const struct uart_ops vt8500_uart_pops = {
0582     .tx_empty   = vt8500_tx_empty,
0583     .set_mctrl  = vt8500_set_mctrl,
0584     .get_mctrl  = vt8500_get_mctrl,
0585     .stop_tx    = vt8500_stop_tx,
0586     .start_tx   = vt8500_start_tx,
0587     .stop_rx    = vt8500_stop_rx,
0588     .enable_ms  = vt8500_enable_ms,
0589     .break_ctl  = vt8500_break_ctl,
0590     .startup    = vt8500_startup,
0591     .shutdown   = vt8500_shutdown,
0592     .set_termios    = vt8500_set_termios,
0593     .type       = vt8500_type,
0594     .release_port   = vt8500_release_port,
0595     .request_port   = vt8500_request_port,
0596     .config_port    = vt8500_config_port,
0597     .verify_port    = vt8500_verify_port,
0598 #ifdef CONFIG_CONSOLE_POLL
0599     .poll_get_char  = vt8500_get_poll_char,
0600     .poll_put_char  = vt8500_put_poll_char,
0601 #endif
0602 };
0603 
0604 static struct uart_driver vt8500_uart_driver = {
0605     .owner      = THIS_MODULE,
0606     .driver_name    = "vt8500_serial",
0607     .dev_name   = "ttyWMT",
0608     .nr     = 6,
0609     .cons       = VT8500_CONSOLE,
0610 };
0611 
0612 static unsigned int vt8500_flags; /* none required so far */
0613 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
0614 
0615 static const struct of_device_id wmt_dt_ids[] = {
0616     { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
0617     { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
0618     {}
0619 };
0620 
0621 static int vt8500_serial_probe(struct platform_device *pdev)
0622 {
0623     struct vt8500_port *vt8500_port;
0624     struct resource *mmres;
0625     struct device_node *np = pdev->dev.of_node;
0626     const unsigned int *flags;
0627     int ret;
0628     int port;
0629     int irq;
0630 
0631     flags = of_device_get_match_data(&pdev->dev);
0632     if (!flags)
0633         return -EINVAL;
0634 
0635     mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0636     if (!mmres)
0637         return -ENODEV;
0638 
0639     irq = platform_get_irq(pdev, 0);
0640     if (irq < 0)
0641         return irq;
0642 
0643     if (np) {
0644         port = of_alias_get_id(np, "serial");
0645         if (port >= VT8500_MAX_PORTS)
0646             port = -1;
0647     } else {
0648         port = -1;
0649     }
0650 
0651     if (port < 0) {
0652         /* calculate the port id */
0653         port = find_first_zero_bit(vt8500_ports_in_use,
0654                        VT8500_MAX_PORTS);
0655     }
0656 
0657     if (port >= VT8500_MAX_PORTS)
0658         return -ENODEV;
0659 
0660     /* reserve the port id */
0661     if (test_and_set_bit(port, vt8500_ports_in_use)) {
0662         /* port already in use - shouldn't really happen */
0663         return -EBUSY;
0664     }
0665 
0666     vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
0667                    GFP_KERNEL);
0668     if (!vt8500_port)
0669         return -ENOMEM;
0670 
0671     vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
0672     if (IS_ERR(vt8500_port->uart.membase))
0673         return PTR_ERR(vt8500_port->uart.membase);
0674 
0675     vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
0676     if (IS_ERR(vt8500_port->clk)) {
0677         dev_err(&pdev->dev, "failed to get clock\n");
0678         return  -EINVAL;
0679     }
0680 
0681     ret = clk_prepare_enable(vt8500_port->clk);
0682     if (ret) {
0683         dev_err(&pdev->dev, "failed to enable clock\n");
0684         return ret;
0685     }
0686 
0687     vt8500_port->vt8500_uart_flags = *flags;
0688     vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
0689                     clk_get_rate(vt8500_port->clk),
0690                     VT8500_RECOMMENDED_CLK
0691                       );
0692     vt8500_port->uart.type = PORT_VT8500;
0693     vt8500_port->uart.iotype = UPIO_MEM;
0694     vt8500_port->uart.mapbase = mmres->start;
0695     vt8500_port->uart.irq = irq;
0696     vt8500_port->uart.fifosize = 16;
0697     vt8500_port->uart.ops = &vt8500_uart_pops;
0698     vt8500_port->uart.line = port;
0699     vt8500_port->uart.dev = &pdev->dev;
0700     vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
0701     vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
0702 
0703     /* Serial core uses the magic "16" everywhere - adjust for it */
0704     vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
0705                     vt8500_port->clk_predivisor /
0706                     VT8500_OVERSAMPLING_DIVISOR;
0707 
0708     snprintf(vt8500_port->name, sizeof(vt8500_port->name),
0709          "VT8500 UART%d", pdev->id);
0710 
0711     vt8500_uart_ports[port] = vt8500_port;
0712 
0713     uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
0714 
0715     platform_set_drvdata(pdev, vt8500_port);
0716 
0717     return 0;
0718 }
0719 
0720 static struct platform_driver vt8500_platform_driver = {
0721     .probe  = vt8500_serial_probe,
0722     .driver = {
0723         .name = "vt8500_serial",
0724         .of_match_table = wmt_dt_ids,
0725         .suppress_bind_attrs = true,
0726     },
0727 };
0728 
0729 static int __init vt8500_serial_init(void)
0730 {
0731     int ret;
0732 
0733     ret = uart_register_driver(&vt8500_uart_driver);
0734     if (unlikely(ret))
0735         return ret;
0736 
0737     ret = platform_driver_register(&vt8500_platform_driver);
0738 
0739     if (unlikely(ret))
0740         uart_unregister_driver(&vt8500_uart_driver);
0741 
0742     return ret;
0743 }
0744 device_initcall(vt8500_serial_init);
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