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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * uartlite.c: Serial driver for Xilinx uartlite serial controller
0004  *
0005  * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
0006  * Copyright (C) 2007 Secret Lab Technologies Ltd.
0007  */
0008 
0009 #include <linux/platform_device.h>
0010 #include <linux/module.h>
0011 #include <linux/bitfield.h>
0012 #include <linux/console.h>
0013 #include <linux/serial.h>
0014 #include <linux/serial_core.h>
0015 #include <linux/tty.h>
0016 #include <linux/tty_flip.h>
0017 #include <linux/delay.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/init.h>
0020 #include <linux/io.h>
0021 #include <linux/iopoll.h>
0022 #include <linux/of.h>
0023 #include <linux/of_address.h>
0024 #include <linux/of_device.h>
0025 #include <linux/of_platform.h>
0026 #include <linux/clk.h>
0027 #include <linux/pm_runtime.h>
0028 
0029 #define ULITE_NAME      "ttyUL"
0030 #define ULITE_MAJOR     204
0031 #define ULITE_MINOR     187
0032 #define ULITE_NR_UARTS      CONFIG_SERIAL_UARTLITE_NR_UARTS
0033 
0034 /* ---------------------------------------------------------------------
0035  * Register definitions
0036  *
0037  * For register details see datasheet:
0038  * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
0039  */
0040 
0041 #define ULITE_RX        0x00
0042 #define ULITE_TX        0x04
0043 #define ULITE_STATUS        0x08
0044 #define ULITE_CONTROL       0x0c
0045 
0046 #define ULITE_REGION        16
0047 
0048 #define ULITE_STATUS_RXVALID    0x01
0049 #define ULITE_STATUS_RXFULL 0x02
0050 #define ULITE_STATUS_TXEMPTY    0x04
0051 #define ULITE_STATUS_TXFULL 0x08
0052 #define ULITE_STATUS_IE     0x10
0053 #define ULITE_STATUS_OVERRUN    0x20
0054 #define ULITE_STATUS_FRAME  0x40
0055 #define ULITE_STATUS_PARITY 0x80
0056 
0057 #define ULITE_CONTROL_RST_TX    0x01
0058 #define ULITE_CONTROL_RST_RX    0x02
0059 #define ULITE_CONTROL_IE    0x10
0060 #define UART_AUTOSUSPEND_TIMEOUT    3000    /* ms */
0061 
0062 /* Static pointer to console port */
0063 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
0064 static struct uart_port *console_port;
0065 #endif
0066 
0067 /**
0068  * struct uartlite_data: Driver private data
0069  * reg_ops: Functions to read/write registers
0070  * clk: Our parent clock, if present
0071  * baud: The baud rate configured when this device was synthesized
0072  * cflags: The cflags for parity and data bits
0073  */
0074 struct uartlite_data {
0075     const struct uartlite_reg_ops *reg_ops;
0076     struct clk *clk;
0077     unsigned int baud;
0078     tcflag_t cflags;
0079 };
0080 
0081 struct uartlite_reg_ops {
0082     u32 (*in)(void __iomem *addr);
0083     void (*out)(u32 val, void __iomem *addr);
0084 };
0085 
0086 static u32 uartlite_inbe32(void __iomem *addr)
0087 {
0088     return ioread32be(addr);
0089 }
0090 
0091 static void uartlite_outbe32(u32 val, void __iomem *addr)
0092 {
0093     iowrite32be(val, addr);
0094 }
0095 
0096 static const struct uartlite_reg_ops uartlite_be = {
0097     .in = uartlite_inbe32,
0098     .out = uartlite_outbe32,
0099 };
0100 
0101 static u32 uartlite_inle32(void __iomem *addr)
0102 {
0103     return ioread32(addr);
0104 }
0105 
0106 static void uartlite_outle32(u32 val, void __iomem *addr)
0107 {
0108     iowrite32(val, addr);
0109 }
0110 
0111 static const struct uartlite_reg_ops uartlite_le = {
0112     .in = uartlite_inle32,
0113     .out = uartlite_outle32,
0114 };
0115 
0116 static inline u32 uart_in32(u32 offset, struct uart_port *port)
0117 {
0118     struct uartlite_data *pdata = port->private_data;
0119 
0120     return pdata->reg_ops->in(port->membase + offset);
0121 }
0122 
0123 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
0124 {
0125     struct uartlite_data *pdata = port->private_data;
0126 
0127     pdata->reg_ops->out(val, port->membase + offset);
0128 }
0129 
0130 static struct uart_port ulite_ports[ULITE_NR_UARTS];
0131 
0132 static struct uart_driver ulite_uart_driver;
0133 
0134 /* ---------------------------------------------------------------------
0135  * Core UART driver operations
0136  */
0137 
0138 static int ulite_receive(struct uart_port *port, int stat)
0139 {
0140     struct tty_port *tport = &port->state->port;
0141     unsigned char ch = 0;
0142     char flag = TTY_NORMAL;
0143 
0144     if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
0145              | ULITE_STATUS_FRAME)) == 0)
0146         return 0;
0147 
0148     /* stats */
0149     if (stat & ULITE_STATUS_RXVALID) {
0150         port->icount.rx++;
0151         ch = uart_in32(ULITE_RX, port);
0152 
0153         if (stat & ULITE_STATUS_PARITY)
0154             port->icount.parity++;
0155     }
0156 
0157     if (stat & ULITE_STATUS_OVERRUN)
0158         port->icount.overrun++;
0159 
0160     if (stat & ULITE_STATUS_FRAME)
0161         port->icount.frame++;
0162 
0163 
0164     /* drop byte with parity error if IGNPAR specificed */
0165     if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
0166         stat &= ~ULITE_STATUS_RXVALID;
0167 
0168     stat &= port->read_status_mask;
0169 
0170     if (stat & ULITE_STATUS_PARITY)
0171         flag = TTY_PARITY;
0172 
0173 
0174     stat &= ~port->ignore_status_mask;
0175 
0176     if (stat & ULITE_STATUS_RXVALID)
0177         tty_insert_flip_char(tport, ch, flag);
0178 
0179     if (stat & ULITE_STATUS_FRAME)
0180         tty_insert_flip_char(tport, 0, TTY_FRAME);
0181 
0182     if (stat & ULITE_STATUS_OVERRUN)
0183         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0184 
0185     return 1;
0186 }
0187 
0188 static int ulite_transmit(struct uart_port *port, int stat)
0189 {
0190     struct circ_buf *xmit  = &port->state->xmit;
0191 
0192     if (stat & ULITE_STATUS_TXFULL)
0193         return 0;
0194 
0195     if (port->x_char) {
0196         uart_out32(port->x_char, ULITE_TX, port);
0197         port->x_char = 0;
0198         port->icount.tx++;
0199         return 1;
0200     }
0201 
0202     if (uart_circ_empty(xmit) || uart_tx_stopped(port))
0203         return 0;
0204 
0205     uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
0206     xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
0207     port->icount.tx++;
0208 
0209     /* wake up */
0210     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0211         uart_write_wakeup(port);
0212 
0213     return 1;
0214 }
0215 
0216 static irqreturn_t ulite_isr(int irq, void *dev_id)
0217 {
0218     struct uart_port *port = dev_id;
0219     int stat, busy, n = 0;
0220     unsigned long flags;
0221 
0222     do {
0223         spin_lock_irqsave(&port->lock, flags);
0224         stat = uart_in32(ULITE_STATUS, port);
0225         busy  = ulite_receive(port, stat);
0226         busy |= ulite_transmit(port, stat);
0227         spin_unlock_irqrestore(&port->lock, flags);
0228         n++;
0229     } while (busy);
0230 
0231     /* work done? */
0232     if (n > 1) {
0233         tty_flip_buffer_push(&port->state->port);
0234         return IRQ_HANDLED;
0235     } else {
0236         return IRQ_NONE;
0237     }
0238 }
0239 
0240 static unsigned int ulite_tx_empty(struct uart_port *port)
0241 {
0242     unsigned long flags;
0243     unsigned int ret;
0244 
0245     spin_lock_irqsave(&port->lock, flags);
0246     ret = uart_in32(ULITE_STATUS, port);
0247     spin_unlock_irqrestore(&port->lock, flags);
0248 
0249     return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
0250 }
0251 
0252 static unsigned int ulite_get_mctrl(struct uart_port *port)
0253 {
0254     return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
0255 }
0256 
0257 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
0258 {
0259     /* N/A */
0260 }
0261 
0262 static void ulite_stop_tx(struct uart_port *port)
0263 {
0264     /* N/A */
0265 }
0266 
0267 static void ulite_start_tx(struct uart_port *port)
0268 {
0269     ulite_transmit(port, uart_in32(ULITE_STATUS, port));
0270 }
0271 
0272 static void ulite_stop_rx(struct uart_port *port)
0273 {
0274     /* don't forward any more data (like !CREAD) */
0275     port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
0276         | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
0277 }
0278 
0279 static void ulite_break_ctl(struct uart_port *port, int ctl)
0280 {
0281     /* N/A */
0282 }
0283 
0284 static int ulite_startup(struct uart_port *port)
0285 {
0286     struct uartlite_data *pdata = port->private_data;
0287     int ret;
0288 
0289     ret = clk_enable(pdata->clk);
0290     if (ret) {
0291         dev_err(port->dev, "Failed to enable clock\n");
0292         return ret;
0293     }
0294 
0295     ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
0296               "uartlite", port);
0297     if (ret)
0298         return ret;
0299 
0300     uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
0301         ULITE_CONTROL, port);
0302     uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
0303 
0304     return 0;
0305 }
0306 
0307 static void ulite_shutdown(struct uart_port *port)
0308 {
0309     struct uartlite_data *pdata = port->private_data;
0310 
0311     uart_out32(0, ULITE_CONTROL, port);
0312     uart_in32(ULITE_CONTROL, port); /* dummy */
0313     free_irq(port->irq, port);
0314     clk_disable(pdata->clk);
0315 }
0316 
0317 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
0318                   struct ktermios *old)
0319 {
0320     unsigned long flags;
0321     struct uartlite_data *pdata = port->private_data;
0322 
0323     /* Set termios to what the hardware supports */
0324     termios->c_iflag &= ~BRKINT;
0325     termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE);
0326     termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
0327     tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
0328 
0329     spin_lock_irqsave(&port->lock, flags);
0330 
0331     port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
0332         | ULITE_STATUS_TXFULL;
0333 
0334     if (termios->c_iflag & INPCK)
0335         port->read_status_mask |=
0336             ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
0337 
0338     port->ignore_status_mask = 0;
0339     if (termios->c_iflag & IGNPAR)
0340         port->ignore_status_mask |= ULITE_STATUS_PARITY
0341             | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
0342 
0343     /* ignore all characters if CREAD is not set */
0344     if ((termios->c_cflag & CREAD) == 0)
0345         port->ignore_status_mask |=
0346             ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
0347             | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
0348 
0349     /* update timeout */
0350     uart_update_timeout(port, termios->c_cflag, pdata->baud);
0351 
0352     spin_unlock_irqrestore(&port->lock, flags);
0353 }
0354 
0355 static const char *ulite_type(struct uart_port *port)
0356 {
0357     return port->type == PORT_UARTLITE ? "uartlite" : NULL;
0358 }
0359 
0360 static void ulite_release_port(struct uart_port *port)
0361 {
0362     release_mem_region(port->mapbase, ULITE_REGION);
0363     iounmap(port->membase);
0364     port->membase = NULL;
0365 }
0366 
0367 static int ulite_request_port(struct uart_port *port)
0368 {
0369     struct uartlite_data *pdata = port->private_data;
0370     int ret;
0371 
0372     pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
0373          port, (unsigned long long) port->mapbase);
0374 
0375     if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
0376         dev_err(port->dev, "Memory region busy\n");
0377         return -EBUSY;
0378     }
0379 
0380     port->membase = ioremap(port->mapbase, ULITE_REGION);
0381     if (!port->membase) {
0382         dev_err(port->dev, "Unable to map registers\n");
0383         release_mem_region(port->mapbase, ULITE_REGION);
0384         return -EBUSY;
0385     }
0386 
0387     pdata->reg_ops = &uartlite_be;
0388     ret = uart_in32(ULITE_CONTROL, port);
0389     uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
0390     ret = uart_in32(ULITE_STATUS, port);
0391     /* Endianess detection */
0392     if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
0393         pdata->reg_ops = &uartlite_le;
0394 
0395     return 0;
0396 }
0397 
0398 static void ulite_config_port(struct uart_port *port, int flags)
0399 {
0400     if (!ulite_request_port(port))
0401         port->type = PORT_UARTLITE;
0402 }
0403 
0404 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
0405 {
0406     /* we don't want the core code to modify any port params */
0407     return -EINVAL;
0408 }
0409 
0410 static void ulite_pm(struct uart_port *port, unsigned int state,
0411              unsigned int oldstate)
0412 {
0413     int ret;
0414 
0415     if (!state) {
0416         ret = pm_runtime_get_sync(port->dev);
0417         if (ret < 0)
0418             dev_err(port->dev, "Failed to enable clocks\n");
0419     } else {
0420         pm_runtime_mark_last_busy(port->dev);
0421         pm_runtime_put_autosuspend(port->dev);
0422     }
0423 }
0424 
0425 #ifdef CONFIG_CONSOLE_POLL
0426 static int ulite_get_poll_char(struct uart_port *port)
0427 {
0428     if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
0429         return NO_POLL_CHAR;
0430 
0431     return uart_in32(ULITE_RX, port);
0432 }
0433 
0434 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
0435 {
0436     while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
0437         cpu_relax();
0438 
0439     /* write char to device */
0440     uart_out32(ch, ULITE_TX, port);
0441 }
0442 #endif
0443 
0444 static const struct uart_ops ulite_ops = {
0445     .tx_empty   = ulite_tx_empty,
0446     .set_mctrl  = ulite_set_mctrl,
0447     .get_mctrl  = ulite_get_mctrl,
0448     .stop_tx    = ulite_stop_tx,
0449     .start_tx   = ulite_start_tx,
0450     .stop_rx    = ulite_stop_rx,
0451     .break_ctl  = ulite_break_ctl,
0452     .startup    = ulite_startup,
0453     .shutdown   = ulite_shutdown,
0454     .set_termios    = ulite_set_termios,
0455     .type       = ulite_type,
0456     .release_port   = ulite_release_port,
0457     .request_port   = ulite_request_port,
0458     .config_port    = ulite_config_port,
0459     .verify_port    = ulite_verify_port,
0460     .pm     = ulite_pm,
0461 #ifdef CONFIG_CONSOLE_POLL
0462     .poll_get_char  = ulite_get_poll_char,
0463     .poll_put_char  = ulite_put_poll_char,
0464 #endif
0465 };
0466 
0467 /* ---------------------------------------------------------------------
0468  * Console driver operations
0469  */
0470 
0471 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
0472 static void ulite_console_wait_tx(struct uart_port *port)
0473 {
0474     u8 val;
0475 
0476     /*
0477      * Spin waiting for TX fifo to have space available.
0478      * When using the Microblaze Debug Module this can take up to 1s
0479      */
0480     if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL),
0481                      0, 1000000, false, ULITE_STATUS, port))
0482         dev_warn(port->dev,
0483              "timeout waiting for TX buffer empty\n");
0484 }
0485 
0486 static void ulite_console_putchar(struct uart_port *port, unsigned char ch)
0487 {
0488     ulite_console_wait_tx(port);
0489     uart_out32(ch, ULITE_TX, port);
0490 }
0491 
0492 static void ulite_console_write(struct console *co, const char *s,
0493                 unsigned int count)
0494 {
0495     struct uart_port *port = console_port;
0496     unsigned long flags;
0497     unsigned int ier;
0498     int locked = 1;
0499 
0500     if (oops_in_progress) {
0501         locked = spin_trylock_irqsave(&port->lock, flags);
0502     } else
0503         spin_lock_irqsave(&port->lock, flags);
0504 
0505     /* save and disable interrupt */
0506     ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
0507     uart_out32(0, ULITE_CONTROL, port);
0508 
0509     uart_console_write(port, s, count, ulite_console_putchar);
0510 
0511     ulite_console_wait_tx(port);
0512 
0513     /* restore interrupt state */
0514     if (ier)
0515         uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
0516 
0517     if (locked)
0518         spin_unlock_irqrestore(&port->lock, flags);
0519 }
0520 
0521 static int ulite_console_setup(struct console *co, char *options)
0522 {
0523     struct uart_port *port = NULL;
0524     int baud = 9600;
0525     int bits = 8;
0526     int parity = 'n';
0527     int flow = 'n';
0528 
0529     if (co->index >= 0 && co->index < ULITE_NR_UARTS)
0530         port = ulite_ports + co->index;
0531 
0532     /* Has the device been initialized yet? */
0533     if (!port || !port->mapbase) {
0534         pr_debug("console on ttyUL%i not present\n", co->index);
0535         return -ENODEV;
0536     }
0537 
0538     console_port = port;
0539 
0540     /* not initialized yet? */
0541     if (!port->membase) {
0542         if (ulite_request_port(port))
0543             return -ENODEV;
0544     }
0545 
0546     if (options)
0547         uart_parse_options(options, &baud, &parity, &bits, &flow);
0548 
0549     return uart_set_options(port, co, baud, parity, bits, flow);
0550 }
0551 
0552 static struct console ulite_console = {
0553     .name   = ULITE_NAME,
0554     .write  = ulite_console_write,
0555     .device = uart_console_device,
0556     .setup  = ulite_console_setup,
0557     .flags  = CON_PRINTBUFFER,
0558     .index  = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
0559     .data   = &ulite_uart_driver,
0560 };
0561 
0562 static void early_uartlite_putc(struct uart_port *port, unsigned char c)
0563 {
0564     /*
0565      * Limit how many times we'll spin waiting for TX FIFO status.
0566      * This will prevent lockups if the base address is incorrectly
0567      * set, or any other issue on the UARTLITE.
0568      * This limit is pretty arbitrary, unless we are at about 10 baud
0569      * we'll never timeout on a working UART.
0570      */
0571     unsigned retries = 1000000;
0572 
0573     while (--retries &&
0574            (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL))
0575         ;
0576 
0577     /* Only attempt the iowrite if we didn't timeout */
0578     if (retries)
0579         writel(c & 0xff, port->membase + ULITE_TX);
0580 }
0581 
0582 static void early_uartlite_write(struct console *console,
0583                  const char *s, unsigned n)
0584 {
0585     struct earlycon_device *device = console->data;
0586     uart_console_write(&device->port, s, n, early_uartlite_putc);
0587 }
0588 
0589 static int __init early_uartlite_setup(struct earlycon_device *device,
0590                        const char *options)
0591 {
0592     if (!device->port.membase)
0593         return -ENODEV;
0594 
0595     device->con->write = early_uartlite_write;
0596     return 0;
0597 }
0598 EARLYCON_DECLARE(uartlite, early_uartlite_setup);
0599 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
0600 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
0601 
0602 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
0603 
0604 static struct uart_driver ulite_uart_driver = {
0605     .owner      = THIS_MODULE,
0606     .driver_name    = "uartlite",
0607     .dev_name   = ULITE_NAME,
0608     .major      = ULITE_MAJOR,
0609     .minor      = ULITE_MINOR,
0610     .nr     = ULITE_NR_UARTS,
0611 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
0612     .cons       = &ulite_console,
0613 #endif
0614 };
0615 
0616 /* ---------------------------------------------------------------------
0617  * Port assignment functions (mapping devices to uart_port structures)
0618  */
0619 
0620 /** ulite_assign: register a uartlite device with the driver
0621  *
0622  * @dev: pointer to device structure
0623  * @id: requested id number.  Pass -1 for automatic port assignment
0624  * @base: base address of uartlite registers
0625  * @irq: irq number for uartlite
0626  * @pdata: private data for uartlite
0627  *
0628  * Returns: 0 on success, <0 otherwise
0629  */
0630 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
0631             struct uartlite_data *pdata)
0632 {
0633     struct uart_port *port;
0634     int rc;
0635 
0636     /* if id = -1; then scan for a free id and use that */
0637     if (id < 0) {
0638         for (id = 0; id < ULITE_NR_UARTS; id++)
0639             if (ulite_ports[id].mapbase == 0)
0640                 break;
0641     }
0642     if (id < 0 || id >= ULITE_NR_UARTS) {
0643         dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
0644         return -EINVAL;
0645     }
0646 
0647     if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
0648         dev_err(dev, "cannot assign to %s%i; it is already in use\n",
0649             ULITE_NAME, id);
0650         return -EBUSY;
0651     }
0652 
0653     port = &ulite_ports[id];
0654 
0655     spin_lock_init(&port->lock);
0656     port->fifosize = 16;
0657     port->regshift = 2;
0658     port->iotype = UPIO_MEM;
0659     port->iobase = 1; /* mark port in use */
0660     port->mapbase = base;
0661     port->membase = NULL;
0662     port->ops = &ulite_ops;
0663     port->irq = irq;
0664     port->flags = UPF_BOOT_AUTOCONF;
0665     port->dev = dev;
0666     port->type = PORT_UNKNOWN;
0667     port->line = id;
0668     port->private_data = pdata;
0669 
0670     dev_set_drvdata(dev, port);
0671 
0672     /* Register the port */
0673     rc = uart_add_one_port(&ulite_uart_driver, port);
0674     if (rc) {
0675         dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
0676         port->mapbase = 0;
0677         dev_set_drvdata(dev, NULL);
0678         return rc;
0679     }
0680 
0681     return 0;
0682 }
0683 
0684 /** ulite_release: register a uartlite device with the driver
0685  *
0686  * @dev: pointer to device structure
0687  */
0688 static int ulite_release(struct device *dev)
0689 {
0690     struct uart_port *port = dev_get_drvdata(dev);
0691     int rc = 0;
0692 
0693     if (port) {
0694         rc = uart_remove_one_port(&ulite_uart_driver, port);
0695         dev_set_drvdata(dev, NULL);
0696         port->mapbase = 0;
0697     }
0698 
0699     return rc;
0700 }
0701 
0702 /**
0703  * ulite_suspend - Stop the device.
0704  *
0705  * @dev: handle to the device structure.
0706  * Return: 0 always.
0707  */
0708 static int __maybe_unused ulite_suspend(struct device *dev)
0709 {
0710     struct uart_port *port = dev_get_drvdata(dev);
0711 
0712     if (port)
0713         uart_suspend_port(&ulite_uart_driver, port);
0714 
0715     return 0;
0716 }
0717 
0718 /**
0719  * ulite_resume - Resume the device.
0720  *
0721  * @dev: handle to the device structure.
0722  * Return: 0 on success, errno otherwise.
0723  */
0724 static int __maybe_unused ulite_resume(struct device *dev)
0725 {
0726     struct uart_port *port = dev_get_drvdata(dev);
0727 
0728     if (port)
0729         uart_resume_port(&ulite_uart_driver, port);
0730 
0731     return 0;
0732 }
0733 
0734 static int __maybe_unused ulite_runtime_suspend(struct device *dev)
0735 {
0736     struct uart_port *port = dev_get_drvdata(dev);
0737     struct uartlite_data *pdata = port->private_data;
0738 
0739     clk_disable(pdata->clk);
0740     return 0;
0741 };
0742 
0743 static int __maybe_unused ulite_runtime_resume(struct device *dev)
0744 {
0745     struct uart_port *port = dev_get_drvdata(dev);
0746     struct uartlite_data *pdata = port->private_data;
0747     int ret;
0748 
0749     ret = clk_enable(pdata->clk);
0750     if (ret) {
0751         dev_err(dev, "Cannot enable clock.\n");
0752         return ret;
0753     }
0754     return 0;
0755 }
0756 
0757 /* ---------------------------------------------------------------------
0758  * Platform bus binding
0759  */
0760 
0761 static const struct dev_pm_ops ulite_pm_ops = {
0762     SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
0763     SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
0764                ulite_runtime_resume, NULL)
0765 };
0766 
0767 #if defined(CONFIG_OF)
0768 /* Match table for of_platform binding */
0769 static const struct of_device_id ulite_of_match[] = {
0770     { .compatible = "xlnx,opb-uartlite-1.00.b", },
0771     { .compatible = "xlnx,xps-uartlite-1.00.a", },
0772     {}
0773 };
0774 MODULE_DEVICE_TABLE(of, ulite_of_match);
0775 #endif /* CONFIG_OF */
0776 
0777 static int ulite_probe(struct platform_device *pdev)
0778 {
0779     struct resource *res;
0780     struct uartlite_data *pdata;
0781     int irq, ret;
0782     int id = pdev->id;
0783 
0784     pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
0785                  GFP_KERNEL);
0786     if (!pdata)
0787         return -ENOMEM;
0788 
0789     if (IS_ENABLED(CONFIG_OF)) {
0790         const char *prop;
0791         struct device_node *np = pdev->dev.of_node;
0792         u32 val = 0;
0793 
0794         prop = "port-number";
0795         ret = of_property_read_u32(np, prop, &id);
0796         if (ret && ret != -EINVAL)
0797 of_err:
0798             return dev_err_probe(&pdev->dev, ret,
0799                          "could not read %s\n", prop);
0800 
0801         prop = "current-speed";
0802         ret = of_property_read_u32(np, prop, &pdata->baud);
0803         if (ret)
0804             goto of_err;
0805 
0806         prop = "xlnx,use-parity";
0807         ret = of_property_read_u32(np, prop, &val);
0808         if (ret && ret != -EINVAL)
0809             goto of_err;
0810 
0811         if (val) {
0812             prop = "xlnx,odd-parity";
0813             ret = of_property_read_u32(np, prop, &val);
0814             if (ret)
0815                 goto of_err;
0816 
0817             if (val)
0818                 pdata->cflags |= PARODD;
0819             pdata->cflags |= PARENB;
0820         }
0821 
0822         val = 8;
0823         prop = "xlnx,data-bits";
0824         ret = of_property_read_u32(np, prop, &val);
0825         if (ret && ret != -EINVAL)
0826             goto of_err;
0827 
0828         switch (val) {
0829         case 5:
0830             pdata->cflags |= CS5;
0831             break;
0832         case 6:
0833             pdata->cflags |= CS6;
0834             break;
0835         case 7:
0836             pdata->cflags |= CS7;
0837             break;
0838         case 8:
0839             pdata->cflags |= CS8;
0840             break;
0841         default:
0842             return dev_err_probe(&pdev->dev, -EINVAL,
0843                          "bad data bits %d\n", val);
0844         }
0845     } else {
0846         pdata->baud = 9600;
0847         pdata->cflags = CS8;
0848     }
0849 
0850     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0851     if (!res)
0852         return -ENODEV;
0853 
0854     irq = platform_get_irq(pdev, 0);
0855     if (irq < 0)
0856         return irq;
0857 
0858     pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
0859     if (IS_ERR(pdata->clk)) {
0860         if (PTR_ERR(pdata->clk) != -ENOENT)
0861             return PTR_ERR(pdata->clk);
0862 
0863         /*
0864          * Clock framework support is optional, continue on
0865          * anyways if we don't find a matching clock.
0866          */
0867         pdata->clk = NULL;
0868     }
0869 
0870     ret = clk_prepare_enable(pdata->clk);
0871     if (ret) {
0872         dev_err(&pdev->dev, "Failed to prepare clock\n");
0873         return ret;
0874     }
0875 
0876     pm_runtime_use_autosuspend(&pdev->dev);
0877     pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
0878     pm_runtime_set_active(&pdev->dev);
0879     pm_runtime_enable(&pdev->dev);
0880 
0881     if (!ulite_uart_driver.state) {
0882         dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
0883         ret = uart_register_driver(&ulite_uart_driver);
0884         if (ret < 0) {
0885             dev_err(&pdev->dev, "Failed to register driver\n");
0886             clk_disable_unprepare(pdata->clk);
0887             return ret;
0888         }
0889     }
0890 
0891     ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
0892 
0893     pm_runtime_mark_last_busy(&pdev->dev);
0894     pm_runtime_put_autosuspend(&pdev->dev);
0895 
0896     return ret;
0897 }
0898 
0899 static int ulite_remove(struct platform_device *pdev)
0900 {
0901     struct uart_port *port = dev_get_drvdata(&pdev->dev);
0902     struct uartlite_data *pdata = port->private_data;
0903     int rc;
0904 
0905     clk_disable_unprepare(pdata->clk);
0906     rc = ulite_release(&pdev->dev);
0907     pm_runtime_disable(&pdev->dev);
0908     pm_runtime_set_suspended(&pdev->dev);
0909     pm_runtime_dont_use_autosuspend(&pdev->dev);
0910     return rc;
0911 }
0912 
0913 /* work with hotplug and coldplug */
0914 MODULE_ALIAS("platform:uartlite");
0915 
0916 static struct platform_driver ulite_platform_driver = {
0917     .probe = ulite_probe,
0918     .remove = ulite_remove,
0919     .driver = {
0920         .name  = "uartlite",
0921         .of_match_table = of_match_ptr(ulite_of_match),
0922         .pm = &ulite_pm_ops,
0923     },
0924 };
0925 
0926 /* ---------------------------------------------------------------------
0927  * Module setup/teardown
0928  */
0929 
0930 static int __init ulite_init(void)
0931 {
0932 
0933     pr_debug("uartlite: calling platform_driver_register()\n");
0934     return platform_driver_register(&ulite_platform_driver);
0935 }
0936 
0937 static void __exit ulite_exit(void)
0938 {
0939     platform_driver_unregister(&ulite_platform_driver);
0940     if (ulite_uart_driver.state)
0941         uart_unregister_driver(&ulite_uart_driver);
0942 }
0943 
0944 module_init(ulite_init);
0945 module_exit(ulite_exit);
0946 
0947 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
0948 MODULE_DESCRIPTION("Xilinx uartlite serial driver");
0949 MODULE_LICENSE("GPL");
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