tty/serial/sunzilog.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _SUNZILOG_H
0003 #define _SUNZILOG_H
0004
0005 struct zilog_channel {
0006     volatile unsigned char control;
0007     volatile unsigned char __pad1;
0008     volatile unsigned char data;
0009     volatile unsigned char __pad2;
0010 };
0011
0012 struct zilog_layout {
0013     struct zilog_channel channelB;
0014     struct zilog_channel channelA;
0015 };
0016
0017 #define NUM_ZSREGS  17
0018 #define R7p     16 /* Written as R7 with P15 bit 0 set */
0019
0020 /* Conversion routines to/from brg time constants from/to bits
0021  * per second.
0022  */
0023 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
0024 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
0025
0026 /* The Zilog register set */
0027
0028 #define FLAG    0x7e
0029
0030 /* Write Register 0 */
0031 #define R0  0       /* Register selects */
0032 #define R1  1
0033 #define R2  2
0034 #define R3  3
0035 #define R4  4
0036 #define R5  5
0037 #define R6  6
0038 #define R7  7
0039 #define R8  8
0040 #define R9  9
0041 #define R10 10
0042 #define R11 11
0043 #define R12 12
0044 #define R13 13
0045 #define R14 14
0046 #define R15 15
0047
0048 #define NULLCODE    0   /* Null Code */
0049 #define POINT_HIGH  0x8 /* Select upper half of registers */
0050 #define RES_EXT_INT 0x10    /* Reset Ext. Status Interrupts */
0051 #define SEND_ABORT  0x18    /* HDLC Abort */
0052 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
0053 #define RES_Tx_P    0x28    /* Reset TxINT Pending */
0054 #define ERR_RES     0x30    /* Error Reset */
0055 #define RES_H_IUS   0x38    /* Reset highest IUS */
0056
0057 #define RES_Rx_CRC  0x40    /* Reset Rx CRC Checker */
0058 #define RES_Tx_CRC  0x80    /* Reset Tx CRC Checker */
0059 #define RES_EOM_L   0xC0    /* Reset EOM latch */
0060
0061 /* Write Register 1 */
0062
0063 #define EXT_INT_ENAB    0x1 /* Ext Int Enable */
0064 #define TxINT_ENAB  0x2 /* Tx Int Enable */
0065 #define PAR_SPEC    0x4 /* Parity is special condition */
0066
0067 #define RxINT_DISAB 0   /* Rx Int Disable */
0068 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
0069 #define INT_ALL_Rx  0x10    /* Int on all Rx Characters or error */
0070 #define INT_ERR_Rx  0x18    /* Int on error only */
0071 #define RxINT_MASK  0x18
0072
0073 #define WT_RDY_RT   0x20    /* Wait/Ready on R/T */
0074 #define WT_FN_RDYFN 0x40    /* Wait/FN/Ready FN */
0075 #define WT_RDY_ENAB 0x80    /* Wait/Ready Enable */
0076
0077 /* Write Register #2 (Interrupt Vector) */
0078
0079 /* Write Register 3 */
0080
0081 #define RxENAB      0x1 /* Rx Enable */
0082 #define SYNC_L_INH  0x2 /* Sync Character Load Inhibit */
0083 #define ADD_SM      0x4 /* Address Search Mode (SDLC) */
0084 #define RxCRC_ENAB  0x8 /* Rx CRC Enable */
0085 #define ENT_HM      0x10    /* Enter Hunt Mode */
0086 #define AUTO_ENAB   0x20    /* Auto Enables */
0087 #define Rx5     0x0 /* Rx 5 Bits/Character */
0088 #define Rx7     0x40    /* Rx 7 Bits/Character */
0089 #define Rx6     0x80    /* Rx 6 Bits/Character */
0090 #define Rx8     0xc0    /* Rx 8 Bits/Character */
0091 #define RxN_MASK    0xc0
0092
0093 /* Write Register 4 */
0094
0095 #define PAR_ENAB    0x1 /* Parity Enable */
0096 #define PAR_EVEN    0x2 /* Parity Even/Odd* */
0097
0098 #define SYNC_ENAB   0   /* Sync Modes Enable */
0099 #define SB1     0x4 /* 1 stop bit/char */
0100 #define SB15        0x8 /* 1.5 stop bits/char */
0101 #define SB2     0xc /* 2 stop bits/char */
0102
0103 #define MONSYNC     0   /* 8 Bit Sync character */
0104 #define BISYNC      0x10    /* 16 bit sync character */
0105 #define SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
0106 #define EXTSYNC     0x30    /* External Sync Mode */
0107
0108 #define X1CLK       0x0 /* x1 clock mode */
0109 #define X16CLK      0x40    /* x16 clock mode */
0110 #define X32CLK      0x80    /* x32 clock mode */
0111 #define X64CLK      0xC0    /* x64 clock mode */
0112 #define XCLK_MASK   0xC0
0113
0114 /* Write Register 5 */
0115
0116 #define TxCRC_ENAB  0x1 /* Tx CRC Enable */
0117 #define RTS     0x2 /* RTS */
0118 #define SDLC_CRC    0x4 /* SDLC/CRC-16 */
0119 #define TxENAB      0x8 /* Tx Enable */
0120 #define SND_BRK     0x10    /* Send Break */
0121 #define Tx5     0x0 /* Tx 5 bits (or less)/character */
0122 #define Tx7     0x20    /* Tx 7 bits/character */
0123 #define Tx6     0x40    /* Tx 6 bits/character */
0124 #define Tx8     0x60    /* Tx 8 bits/character */
0125 #define TxN_MASK    0x60
0126 #define DTR     0x80    /* DTR */
0127
0128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
0129
0130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
0131
0132 /* Write Register 7' (ESCC Only) */
0133 #define AUTO_TxFLAG 1   /* Automatic Tx SDLC Flag */
0134 #define AUTO_EOM_RST    2   /* Automatic EOM Reset */
0135 #define AUTOnRTS    4   /* Automatic /RTS pin deactivation */
0136 #define RxFIFO_LVL  8   /* Receive FIFO interrupt level */
0137 #define nDTRnREQ    0x10    /* /DTR/REQ timing */
0138 #define TxFIFO_LVL  0x20    /* Transmit FIFO interrupt level */
0139 #define EXT_RD_EN   0x40    /* Extended read register enable */
0140
0141 /* Write Register 8 (transmit buffer) */
0142
0143 /* Write Register 9 (Master interrupt control) */
0144 #define VIS 1   /* Vector Includes Status */
0145 #define NV  2   /* No Vector */
0146 #define DLC 4   /* Disable Lower Chain */
0147 #define MIE 8   /* Master Interrupt Enable */
0148 #define STATHI  0x10    /* Status high */
0149 #define SWIACK  0x20    /* Software Interrupt Ack (not on NMOS) */
0150 #define NORESET 0   /* No reset on write to R9 */
0151 #define CHRB    0x40    /* Reset channel B */
0152 #define CHRA    0x80    /* Reset channel A */
0153 #define FHWRES  0xc0    /* Force hardware reset */
0154
0155 /* Write Register 10 (misc control bits) */
0156 #define BIT6    1   /* 6 bit/8bit sync */
0157 #define LOOPMODE 2  /* SDLC Loop mode */
0158 #define ABUNDER 4   /* Abort/flag on SDLC xmit underrun */
0159 #define MARKIDLE 8  /* Mark/flag on idle */
0160 #define GAOP    0x10    /* Go active on poll */
0161 #define NRZ 0   /* NRZ mode */
0162 #define NRZI    0x20    /* NRZI mode */
0163 #define FM1 0x40    /* FM1 (transition = 1) */
0164 #define FM0 0x60    /* FM0 (transition = 0) */
0165 #define CRCPS   0x80    /* CRC Preset I/O */
0166
0167 /* Write Register 11 (Clock Mode control) */
0168 #define TRxCXT  0   /* TRxC = Xtal output */
0169 #define TRxCTC  1   /* TRxC = Transmit clock */
0170 #define TRxCBR  2   /* TRxC = BR Generator Output */
0171 #define TRxCDP  3   /* TRxC = DPLL output */
0172 #define TRxCOI  4   /* TRxC O/I */
0173 #define TCRTxCP 0   /* Transmit clock = RTxC pin */
0174 #define TCTRxCP 8   /* Transmit clock = TRxC pin */
0175 #define TCBR    0x10    /* Transmit clock = BR Generator output */
0176 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
0177 #define RCRTxCP 0   /* Receive clock = RTxC pin */
0178 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
0179 #define RCBR    0x40    /* Receive clock = BR Generator output */
0180 #define RCDPLL  0x60    /* Receive clock = DPLL output */
0181 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
0182
0183 /* Write Register 12 (lower byte of baud rate generator time constant) */
0184
0185 /* Write Register 13 (upper byte of baud rate generator time constant) */
0186
0187 /* Write Register 14 (Misc control bits) */
0188 #define BRENAB  1   /* Baud rate generator enable */
0189 #define BRSRC   2   /* Baud rate generator source */
0190 #define DTRREQ  4   /* DTR/Request function */
0191 #define AUTOECHO 8  /* Auto Echo */
0192 #define LOOPBAK 0x10    /* Local loopback */
0193 #define SEARCH  0x20    /* Enter search mode */
0194 #define RMC 0x40    /* Reset missing clock */
0195 #define DISDPLL 0x60    /* Disable DPLL */
0196 #define SSBR    0x80    /* Set DPLL source = BR generator */
0197 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
0198 #define SFMM    0xc0    /* Set FM mode */
0199 #define SNRZI   0xe0    /* Set NRZI mode */
0200
0201 /* Write Register 15 (external/status interrupt control) */
0202 #define WR7pEN  1   /* WR7' Enable (ESCC only) */
0203 #define ZCIE    2   /* Zero count IE */
0204 #define FIFOEN  4   /* FIFO Enable (ESCC only) */
0205 #define DCDIE   8   /* DCD IE */
0206 #define SYNCIE  0x10    /* Sync/hunt IE */
0207 #define CTSIE   0x20    /* CTS IE */
0208 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
0209 #define BRKIE   0x80    /* Break/Abort IE */
0210
0211
0212 /* Read Register 0 */
0213 #define Rx_CH_AV    0x1 /* Rx Character Available */
0214 #define ZCOUNT      0x2 /* Zero count */
0215 #define Tx_BUF_EMP  0x4 /* Tx Buffer empty */
0216 #define DCD     0x8 /* DCD */
0217 #define SYNC        0x10    /* Sync/hunt */
0218 #define CTS     0x20    /* CTS */
0219 #define TxEOM       0x40    /* Tx underrun */
0220 #define BRK_ABRT    0x80    /* Break/Abort */
0221
0222 /* Read Register 1 */
0223 #define ALL_SNT     0x1 /* All sent */
0224 /* Residue Data for 8 Rx bits/char programmed */
0225 #define RES3        0x8 /* 0/3 */
0226 #define RES4        0x4 /* 0/4 */
0227 #define RES5        0xc /* 0/5 */
0228 #define RES6        0x2 /* 0/6 */
0229 #define RES7        0xa /* 0/7 */
0230 #define RES8        0x6 /* 0/8 */
0231 #define RES18       0xe /* 1/8 */
0232 #define RES28       0x0 /* 2/8 */
0233 /* Special Rx Condition Interrupts */
0234 #define PAR_ERR     0x10    /* Parity error */
0235 #define Rx_OVR      0x20    /* Rx Overrun Error */
0236 #define CRC_ERR     0x40    /* CRC/Framing Error */
0237 #define END_FR      0x80    /* End of Frame (SDLC) */
0238
0239 /* Read Register 2 (channel b only) - Interrupt vector */
0240 #define CHB_Tx_EMPTY    0x00
0241 #define CHB_EXT_STAT    0x02
0242 #define CHB_Rx_AVAIL    0x04
0243 #define CHB_SPECIAL 0x06
0244 #define CHA_Tx_EMPTY    0x08
0245 #define CHA_EXT_STAT    0x0a
0246 #define CHA_Rx_AVAIL    0x0c
0247 #define CHA_SPECIAL 0x0e
0248 #define STATUS_MASK 0x0e
0249
0250 /* Read Register 3 (interrupt pending register) ch a only */
0251 #define CHBEXT  0x1     /* Channel B Ext/Stat IP */
0252 #define CHBTxIP 0x2     /* Channel B Tx IP */
0253 #define CHBRxIP 0x4     /* Channel B Rx IP */
0254 #define CHAEXT  0x8     /* Channel A Ext/Stat IP */
0255 #define CHATxIP 0x10        /* Channel A Tx IP */
0256 #define CHARxIP 0x20        /* Channel A Rx IP */
0257
0258 /* Read Register 6 (LSB frame byte count [Not on NMOS]) */
0259
0260 /* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */
0261
0262 /* Read Register 8 (receive data register) */
0263
0264 /* Read Register 10  (misc status bits) */
0265 #define ONLOOP  2       /* On loop */
0266 #define LOOPSEND 0x10       /* Loop sending */
0267 #define CLK2MIS 0x40        /* Two clocks missing */
0268 #define CLK1MIS 0x80        /* One clock missing */
0269
0270 /* Read Register 12 (lower byte of baud rate generator constant) */
0271
0272 /* Read Register 13 (upper byte of baud rate generator constant) */
0273
0274 /* Read Register 15 (value of WR 15) */
0275
0276 /* Misc macros */
0277 #define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
0278                      udelay(5); } while(0)
0279
0280 #define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
0281                      udelay(5); } while(0)
0282
0283 #define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
0284                      udelay(2); \
0285                      sbus_readb(&channel->data); \
0286                      udelay(2); \
0287                      sbus_readb(&channel->data); \
0288                      udelay(2); } while(0)
0289
0290 #endif /* _SUNZILOG_H */