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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* sunzilog.c: Zilog serial driver for Sparc systems.
0003  *
0004  * Driver for Zilog serial chips found on Sun workstations and
0005  * servers.  This driver could actually be made more generic.
0006  *
0007  * This is based on the old drivers/sbus/char/zs.c code.  A lot
0008  * of code has been simply moved over directly from there but
0009  * much has been rewritten.  Credits therefore go out to Eddie
0010  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
0011  * work there.
0012  *
0013  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/kernel.h>
0018 #include <linux/errno.h>
0019 #include <linux/delay.h>
0020 #include <linux/tty.h>
0021 #include <linux/tty_flip.h>
0022 #include <linux/major.h>
0023 #include <linux/string.h>
0024 #include <linux/ptrace.h>
0025 #include <linux/ioport.h>
0026 #include <linux/slab.h>
0027 #include <linux/circ_buf.h>
0028 #include <linux/serial.h>
0029 #include <linux/sysrq.h>
0030 #include <linux/console.h>
0031 #include <linux/spinlock.h>
0032 #ifdef CONFIG_SERIO
0033 #include <linux/serio.h>
0034 #endif
0035 #include <linux/init.h>
0036 #include <linux/of_device.h>
0037 
0038 #include <linux/io.h>
0039 #include <asm/irq.h>
0040 #include <asm/prom.h>
0041 #include <asm/setup.h>
0042 
0043 #include <linux/serial_core.h>
0044 #include <linux/sunserialcore.h>
0045 
0046 #include "sunzilog.h"
0047 
0048 /* On 32-bit sparcs we need to delay after register accesses
0049  * to accommodate sun4 systems, but we do not need to flush writes.
0050  * On 64-bit sparc we only need to flush single writes to ensure
0051  * completion.
0052  */
0053 #ifndef CONFIG_SPARC64
0054 #define ZSDELAY()       udelay(5)
0055 #define ZSDELAY_LONG()      udelay(20)
0056 #define ZS_WSYNC(channel)   do { } while (0)
0057 #else
0058 #define ZSDELAY()
0059 #define ZSDELAY_LONG()
0060 #define ZS_WSYNC(__channel) \
0061     readb(&((__channel)->control))
0062 #endif
0063 
0064 #define ZS_CLOCK        4915200 /* Zilog input clock rate. */
0065 #define ZS_CLOCK_DIVISOR    16      /* Divisor this driver uses. */
0066 
0067 /*
0068  * We wrap our port structure around the generic uart_port.
0069  */
0070 struct uart_sunzilog_port {
0071     struct uart_port        port;
0072 
0073     /* IRQ servicing chain.  */
0074     struct uart_sunzilog_port   *next;
0075 
0076     /* Current values of Zilog write registers.  */
0077     unsigned char           curregs[NUM_ZSREGS];
0078 
0079     unsigned int            flags;
0080 #define SUNZILOG_FLAG_CONS_KEYB     0x00000001
0081 #define SUNZILOG_FLAG_CONS_MOUSE    0x00000002
0082 #define SUNZILOG_FLAG_IS_CONS       0x00000004
0083 #define SUNZILOG_FLAG_IS_KGDB       0x00000008
0084 #define SUNZILOG_FLAG_MODEM_STATUS  0x00000010
0085 #define SUNZILOG_FLAG_IS_CHANNEL_A  0x00000020
0086 #define SUNZILOG_FLAG_REGS_HELD     0x00000040
0087 #define SUNZILOG_FLAG_TX_STOPPED    0x00000080
0088 #define SUNZILOG_FLAG_TX_ACTIVE     0x00000100
0089 #define SUNZILOG_FLAG_ESCC      0x00000200
0090 #define SUNZILOG_FLAG_ISR_HANDLER   0x00000400
0091 
0092     unsigned int cflag;
0093 
0094     unsigned char           parity_mask;
0095     unsigned char           prev_status;
0096 
0097 #ifdef CONFIG_SERIO
0098     struct serio            serio;
0099     int             serio_open;
0100 #endif
0101 };
0102 
0103 static void sunzilog_putchar(struct uart_port *port, unsigned char ch);
0104 
0105 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
0106 #define UART_ZILOG(PORT)        ((struct uart_sunzilog_port *)(PORT))
0107 
0108 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
0109 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
0110 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
0111 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
0112 #define ZS_WANTS_MODEM_STATUS(UP)   ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
0113 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
0114 #define ZS_REGS_HELD(UP)    ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
0115 #define ZS_TX_STOPPED(UP)   ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
0116 #define ZS_TX_ACTIVE(UP)    ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
0117 
0118 /* Reading and writing Zilog8530 registers.  The delays are to make this
0119  * driver work on the Sun4 which needs a settling delay after each chip
0120  * register access, other machines handle this in hardware via auxiliary
0121  * flip-flops which implement the settle time we do in software.
0122  *
0123  * The port lock must be held and local IRQs must be disabled
0124  * when {read,write}_zsreg is invoked.
0125  */
0126 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
0127                 unsigned char reg)
0128 {
0129     unsigned char retval;
0130 
0131     writeb(reg, &channel->control);
0132     ZSDELAY();
0133     retval = readb(&channel->control);
0134     ZSDELAY();
0135 
0136     return retval;
0137 }
0138 
0139 static void write_zsreg(struct zilog_channel __iomem *channel,
0140             unsigned char reg, unsigned char value)
0141 {
0142     writeb(reg, &channel->control);
0143     ZSDELAY();
0144     writeb(value, &channel->control);
0145     ZSDELAY();
0146 }
0147 
0148 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
0149 {
0150     int i;
0151 
0152     for (i = 0; i < 32; i++) {
0153         unsigned char regval;
0154 
0155         regval = readb(&channel->control);
0156         ZSDELAY();
0157         if (regval & Rx_CH_AV)
0158             break;
0159 
0160         regval = read_zsreg(channel, R1);
0161         readb(&channel->data);
0162         ZSDELAY();
0163 
0164         if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
0165             writeb(ERR_RES, &channel->control);
0166             ZSDELAY();
0167             ZS_WSYNC(channel);
0168         }
0169     }
0170 }
0171 
0172 /* This function must only be called when the TX is not busy.  The UART
0173  * port lock must be held and local interrupts disabled.
0174  */
0175 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
0176 {
0177     int i;
0178     int escc;
0179     unsigned char r15;
0180 
0181     /* Let pending transmits finish.  */
0182     for (i = 0; i < 1000; i++) {
0183         unsigned char stat = read_zsreg(channel, R1);
0184         if (stat & ALL_SNT)
0185             break;
0186         udelay(100);
0187     }
0188 
0189     writeb(ERR_RES, &channel->control);
0190     ZSDELAY();
0191     ZS_WSYNC(channel);
0192 
0193     sunzilog_clear_fifo(channel);
0194 
0195     /* Disable all interrupts.  */
0196     write_zsreg(channel, R1,
0197             regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
0198 
0199     /* Set parity, sync config, stop bits, and clock divisor.  */
0200     write_zsreg(channel, R4, regs[R4]);
0201 
0202     /* Set misc. TX/RX control bits.  */
0203     write_zsreg(channel, R10, regs[R10]);
0204 
0205     /* Set TX/RX controls sans the enable bits.  */
0206     write_zsreg(channel, R3, regs[R3] & ~RxENAB);
0207     write_zsreg(channel, R5, regs[R5] & ~TxENAB);
0208 
0209     /* Synchronous mode config.  */
0210     write_zsreg(channel, R6, regs[R6]);
0211     write_zsreg(channel, R7, regs[R7]);
0212 
0213     /* Don't mess with the interrupt vector (R2, unused by us) and
0214      * master interrupt control (R9).  We make sure this is setup
0215      * properly at probe time then never touch it again.
0216      */
0217 
0218     /* Disable baud generator.  */
0219     write_zsreg(channel, R14, regs[R14] & ~BRENAB);
0220 
0221     /* Clock mode control.  */
0222     write_zsreg(channel, R11, regs[R11]);
0223 
0224     /* Lower and upper byte of baud rate generator divisor.  */
0225     write_zsreg(channel, R12, regs[R12]);
0226     write_zsreg(channel, R13, regs[R13]);
0227     
0228     /* Now rewrite R14, with BRENAB (if set).  */
0229     write_zsreg(channel, R14, regs[R14]);
0230 
0231     /* External status interrupt control.  */
0232     write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
0233 
0234     /* ESCC Extension Register */
0235     r15 = read_zsreg(channel, R15);
0236     if (r15 & 0x01) {
0237         write_zsreg(channel, R7,  regs[R7p]);
0238 
0239         /* External status interrupt and FIFO control.  */
0240         write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
0241         escc = 1;
0242     } else {
0243          /* Clear FIFO bit case it is an issue */
0244         regs[R15] &= ~FIFOEN;
0245         escc = 0;
0246     }
0247 
0248     /* Reset external status interrupts.  */
0249     write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
0250     write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
0251 
0252     /* Rewrite R3/R5, this time without enables masked.  */
0253     write_zsreg(channel, R3, regs[R3]);
0254     write_zsreg(channel, R5, regs[R5]);
0255 
0256     /* Rewrite R1, this time without IRQ enabled masked.  */
0257     write_zsreg(channel, R1, regs[R1]);
0258 
0259     return escc;
0260 }
0261 
0262 /* Reprogram the Zilog channel HW registers with the copies found in the
0263  * software state struct.  If the transmitter is busy, we defer this update
0264  * until the next TX complete interrupt.  Else, we do it right now.
0265  *
0266  * The UART port lock must be held and local interrupts disabled.
0267  */
0268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
0269                        struct zilog_channel __iomem *channel)
0270 {
0271     if (!ZS_REGS_HELD(up)) {
0272         if (ZS_TX_ACTIVE(up)) {
0273             up->flags |= SUNZILOG_FLAG_REGS_HELD;
0274         } else {
0275             __load_zsregs(channel, up->curregs);
0276         }
0277     }
0278 }
0279 
0280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
0281 {
0282     unsigned int cur_cflag = up->cflag;
0283     int brg, new_baud;
0284 
0285     up->cflag &= ~CBAUD;
0286     up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
0287 
0288     brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
0289     up->curregs[R12] = (brg & 0xff);
0290     up->curregs[R13] = (brg >> 8) & 0xff;
0291     sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
0292 }
0293 
0294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
0295                      unsigned char ch, int is_break)
0296 {
0297     if (ZS_IS_KEYB(up)) {
0298         /* Stop-A is handled by drivers/char/keyboard.c now. */
0299 #ifdef CONFIG_SERIO
0300         if (up->serio_open)
0301             serio_interrupt(&up->serio, ch, 0);
0302 #endif
0303     } else if (ZS_IS_MOUSE(up)) {
0304         int ret = suncore_mouse_baud_detection(ch, is_break);
0305 
0306         switch (ret) {
0307         case 2:
0308             sunzilog_change_mouse_baud(up);
0309             fallthrough;
0310         case 1:
0311             break;
0312 
0313         case 0:
0314 #ifdef CONFIG_SERIO
0315             if (up->serio_open)
0316                 serio_interrupt(&up->serio, ch, 0);
0317 #endif
0318             break;
0319         }
0320     }
0321 }
0322 
0323 static struct tty_port *
0324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
0325                struct zilog_channel __iomem *channel)
0326 {
0327     struct tty_port *port = NULL;
0328     unsigned char ch, r1, flag;
0329 
0330     if (up->port.state != NULL)     /* Unopened serial console */
0331         port = &up->port.state->port;
0332 
0333     for (;;) {
0334 
0335         r1 = read_zsreg(channel, R1);
0336         if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
0337             writeb(ERR_RES, &channel->control);
0338             ZSDELAY();
0339             ZS_WSYNC(channel);
0340         }
0341 
0342         ch = readb(&channel->control);
0343         ZSDELAY();
0344 
0345         /* This funny hack depends upon BRK_ABRT not interfering
0346          * with the other bits we care about in R1.
0347          */
0348         if (ch & BRK_ABRT)
0349             r1 |= BRK_ABRT;
0350 
0351         if (!(ch & Rx_CH_AV))
0352             break;
0353 
0354         ch = readb(&channel->data);
0355         ZSDELAY();
0356 
0357         ch &= up->parity_mask;
0358 
0359         if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
0360             sunzilog_kbdms_receive_chars(up, ch, 0);
0361             continue;
0362         }
0363 
0364         /* A real serial line, record the character and status.  */
0365         flag = TTY_NORMAL;
0366         up->port.icount.rx++;
0367         if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
0368             if (r1 & BRK_ABRT) {
0369                 r1 &= ~(PAR_ERR | CRC_ERR);
0370                 up->port.icount.brk++;
0371                 if (uart_handle_break(&up->port))
0372                     continue;
0373             }
0374             else if (r1 & PAR_ERR)
0375                 up->port.icount.parity++;
0376             else if (r1 & CRC_ERR)
0377                 up->port.icount.frame++;
0378             if (r1 & Rx_OVR)
0379                 up->port.icount.overrun++;
0380             r1 &= up->port.read_status_mask;
0381             if (r1 & BRK_ABRT)
0382                 flag = TTY_BREAK;
0383             else if (r1 & PAR_ERR)
0384                 flag = TTY_PARITY;
0385             else if (r1 & CRC_ERR)
0386                 flag = TTY_FRAME;
0387         }
0388         if (uart_handle_sysrq_char(&up->port, ch) || !port)
0389             continue;
0390 
0391         if (up->port.ignore_status_mask == 0xff ||
0392             (r1 & up->port.ignore_status_mask) == 0) {
0393                 tty_insert_flip_char(port, ch, flag);
0394         }
0395         if (r1 & Rx_OVR)
0396             tty_insert_flip_char(port, 0, TTY_OVERRUN);
0397     }
0398 
0399     return port;
0400 }
0401 
0402 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
0403                    struct zilog_channel __iomem *channel)
0404 {
0405     unsigned char status;
0406 
0407     status = readb(&channel->control);
0408     ZSDELAY();
0409 
0410     writeb(RES_EXT_INT, &channel->control);
0411     ZSDELAY();
0412     ZS_WSYNC(channel);
0413 
0414     if (status & BRK_ABRT) {
0415         if (ZS_IS_MOUSE(up))
0416             sunzilog_kbdms_receive_chars(up, 0, 1);
0417         if (ZS_IS_CONS(up)) {
0418             /* Wait for BREAK to deassert to avoid potentially
0419              * confusing the PROM.
0420              */
0421             while (1) {
0422                 status = readb(&channel->control);
0423                 ZSDELAY();
0424                 if (!(status & BRK_ABRT))
0425                     break;
0426             }
0427             sun_do_break();
0428             return;
0429         }
0430     }
0431 
0432     if (ZS_WANTS_MODEM_STATUS(up)) {
0433         if (status & SYNC)
0434             up->port.icount.dsr++;
0435 
0436         /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
0437          * But it does not tell us which bit has changed, we have to keep
0438          * track of this ourselves.
0439          */
0440         if ((status ^ up->prev_status) ^ DCD)
0441             uart_handle_dcd_change(&up->port,
0442                            (status & DCD));
0443         if ((status ^ up->prev_status) ^ CTS)
0444             uart_handle_cts_change(&up->port,
0445                            (status & CTS));
0446 
0447         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
0448     }
0449 
0450     up->prev_status = status;
0451 }
0452 
0453 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
0454                     struct zilog_channel __iomem *channel)
0455 {
0456     struct circ_buf *xmit;
0457 
0458     if (ZS_IS_CONS(up)) {
0459         unsigned char status = readb(&channel->control);
0460         ZSDELAY();
0461 
0462         /* TX still busy?  Just wait for the next TX done interrupt.
0463          *
0464          * It can occur because of how we do serial console writes.  It would
0465          * be nice to transmit console writes just like we normally would for
0466          * a TTY line. (ie. buffered and TX interrupt driven).  That is not
0467          * easy because console writes cannot sleep.  One solution might be
0468          * to poll on enough port->xmit space becoming free.  -DaveM
0469          */
0470         if (!(status & Tx_BUF_EMP))
0471             return;
0472     }
0473 
0474     up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
0475 
0476     if (ZS_REGS_HELD(up)) {
0477         __load_zsregs(channel, up->curregs);
0478         up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
0479     }
0480 
0481     if (ZS_TX_STOPPED(up)) {
0482         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
0483         goto ack_tx_int;
0484     }
0485 
0486     if (up->port.x_char) {
0487         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
0488         writeb(up->port.x_char, &channel->data);
0489         ZSDELAY();
0490         ZS_WSYNC(channel);
0491 
0492         up->port.icount.tx++;
0493         up->port.x_char = 0;
0494         return;
0495     }
0496 
0497     if (up->port.state == NULL)
0498         goto ack_tx_int;
0499     xmit = &up->port.state->xmit;
0500     if (uart_circ_empty(xmit))
0501         goto ack_tx_int;
0502 
0503     if (uart_tx_stopped(&up->port))
0504         goto ack_tx_int;
0505 
0506     up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
0507     writeb(xmit->buf[xmit->tail], &channel->data);
0508     ZSDELAY();
0509     ZS_WSYNC(channel);
0510 
0511     xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0512     up->port.icount.tx++;
0513 
0514     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0515         uart_write_wakeup(&up->port);
0516 
0517     return;
0518 
0519 ack_tx_int:
0520     writeb(RES_Tx_P, &channel->control);
0521     ZSDELAY();
0522     ZS_WSYNC(channel);
0523 }
0524 
0525 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
0526 {
0527     struct uart_sunzilog_port *up = dev_id;
0528 
0529     while (up) {
0530         struct zilog_channel __iomem *channel
0531             = ZILOG_CHANNEL_FROM_PORT(&up->port);
0532         struct tty_port *port;
0533         unsigned char r3;
0534 
0535         spin_lock(&up->port.lock);
0536         r3 = read_zsreg(channel, R3);
0537 
0538         /* Channel A */
0539         port = NULL;
0540         if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
0541             writeb(RES_H_IUS, &channel->control);
0542             ZSDELAY();
0543             ZS_WSYNC(channel);
0544 
0545             if (r3 & CHARxIP)
0546                 port = sunzilog_receive_chars(up, channel);
0547             if (r3 & CHAEXT)
0548                 sunzilog_status_handle(up, channel);
0549             if (r3 & CHATxIP)
0550                 sunzilog_transmit_chars(up, channel);
0551         }
0552         spin_unlock(&up->port.lock);
0553 
0554         if (port)
0555             tty_flip_buffer_push(port);
0556 
0557         /* Channel B */
0558         up = up->next;
0559         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
0560 
0561         spin_lock(&up->port.lock);
0562         port = NULL;
0563         if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
0564             writeb(RES_H_IUS, &channel->control);
0565             ZSDELAY();
0566             ZS_WSYNC(channel);
0567 
0568             if (r3 & CHBRxIP)
0569                 port = sunzilog_receive_chars(up, channel);
0570             if (r3 & CHBEXT)
0571                 sunzilog_status_handle(up, channel);
0572             if (r3 & CHBTxIP)
0573                 sunzilog_transmit_chars(up, channel);
0574         }
0575         spin_unlock(&up->port.lock);
0576 
0577         if (port)
0578             tty_flip_buffer_push(port);
0579 
0580         up = up->next;
0581     }
0582 
0583     return IRQ_HANDLED;
0584 }
0585 
0586 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
0587  * port lock, it is acquired here.
0588  */
0589 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
0590 {
0591     struct zilog_channel __iomem *channel;
0592     unsigned char status;
0593 
0594     channel = ZILOG_CHANNEL_FROM_PORT(port);
0595     status = readb(&channel->control);
0596     ZSDELAY();
0597 
0598     return status;
0599 }
0600 
0601 /* The port lock is not held.  */
0602 static unsigned int sunzilog_tx_empty(struct uart_port *port)
0603 {
0604     unsigned long flags;
0605     unsigned char status;
0606     unsigned int ret;
0607 
0608     spin_lock_irqsave(&port->lock, flags);
0609 
0610     status = sunzilog_read_channel_status(port);
0611 
0612     spin_unlock_irqrestore(&port->lock, flags);
0613 
0614     if (status & Tx_BUF_EMP)
0615         ret = TIOCSER_TEMT;
0616     else
0617         ret = 0;
0618 
0619     return ret;
0620 }
0621 
0622 /* The port lock is held and interrupts are disabled.  */
0623 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
0624 {
0625     unsigned char status;
0626     unsigned int ret;
0627 
0628     status = sunzilog_read_channel_status(port);
0629 
0630     ret = 0;
0631     if (status & DCD)
0632         ret |= TIOCM_CAR;
0633     if (status & SYNC)
0634         ret |= TIOCM_DSR;
0635     if (status & CTS)
0636         ret |= TIOCM_CTS;
0637 
0638     return ret;
0639 }
0640 
0641 /* The port lock is held and interrupts are disabled.  */
0642 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
0643 {
0644     struct uart_sunzilog_port *up =
0645         container_of(port, struct uart_sunzilog_port, port);
0646     struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
0647     unsigned char set_bits, clear_bits;
0648 
0649     set_bits = clear_bits = 0;
0650 
0651     if (mctrl & TIOCM_RTS)
0652         set_bits |= RTS;
0653     else
0654         clear_bits |= RTS;
0655     if (mctrl & TIOCM_DTR)
0656         set_bits |= DTR;
0657     else
0658         clear_bits |= DTR;
0659 
0660     /* NOTE: Not subject to 'transmitter active' rule.  */ 
0661     up->curregs[R5] |= set_bits;
0662     up->curregs[R5] &= ~clear_bits;
0663     write_zsreg(channel, R5, up->curregs[R5]);
0664 }
0665 
0666 /* The port lock is held and interrupts are disabled.  */
0667 static void sunzilog_stop_tx(struct uart_port *port)
0668 {
0669     struct uart_sunzilog_port *up =
0670         container_of(port, struct uart_sunzilog_port, port);
0671 
0672     up->flags |= SUNZILOG_FLAG_TX_STOPPED;
0673 }
0674 
0675 /* The port lock is held and interrupts are disabled.  */
0676 static void sunzilog_start_tx(struct uart_port *port)
0677 {
0678     struct uart_sunzilog_port *up =
0679         container_of(port, struct uart_sunzilog_port, port);
0680     struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
0681     unsigned char status;
0682 
0683     up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
0684     up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
0685 
0686     status = readb(&channel->control);
0687     ZSDELAY();
0688 
0689     /* TX busy?  Just wait for the TX done interrupt.  */
0690     if (!(status & Tx_BUF_EMP))
0691         return;
0692 
0693     /* Send the first character to jump-start the TX done
0694      * IRQ sending engine.
0695      */
0696     if (port->x_char) {
0697         writeb(port->x_char, &channel->data);
0698         ZSDELAY();
0699         ZS_WSYNC(channel);
0700 
0701         port->icount.tx++;
0702         port->x_char = 0;
0703     } else {
0704         struct circ_buf *xmit = &port->state->xmit;
0705 
0706         if (uart_circ_empty(xmit))
0707             return;
0708         writeb(xmit->buf[xmit->tail], &channel->data);
0709         ZSDELAY();
0710         ZS_WSYNC(channel);
0711 
0712         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0713         port->icount.tx++;
0714 
0715         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0716             uart_write_wakeup(&up->port);
0717     }
0718 }
0719 
0720 /* The port lock is held.  */
0721 static void sunzilog_stop_rx(struct uart_port *port)
0722 {
0723     struct uart_sunzilog_port *up = UART_ZILOG(port);
0724     struct zilog_channel __iomem *channel;
0725 
0726     if (ZS_IS_CONS(up))
0727         return;
0728 
0729     channel = ZILOG_CHANNEL_FROM_PORT(port);
0730 
0731     /* Disable all RX interrupts.  */
0732     up->curregs[R1] &= ~RxINT_MASK;
0733     sunzilog_maybe_update_regs(up, channel);
0734 }
0735 
0736 /* The port lock is held.  */
0737 static void sunzilog_enable_ms(struct uart_port *port)
0738 {
0739     struct uart_sunzilog_port *up =
0740         container_of(port, struct uart_sunzilog_port, port);
0741     struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
0742     unsigned char new_reg;
0743 
0744     new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
0745     if (new_reg != up->curregs[R15]) {
0746         up->curregs[R15] = new_reg;
0747 
0748         /* NOTE: Not subject to 'transmitter active' rule.  */ 
0749         write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
0750     }
0751 }
0752 
0753 /* The port lock is not held.  */
0754 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
0755 {
0756     struct uart_sunzilog_port *up =
0757         container_of(port, struct uart_sunzilog_port, port);
0758     struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
0759     unsigned char set_bits, clear_bits, new_reg;
0760     unsigned long flags;
0761 
0762     set_bits = clear_bits = 0;
0763 
0764     if (break_state)
0765         set_bits |= SND_BRK;
0766     else
0767         clear_bits |= SND_BRK;
0768 
0769     spin_lock_irqsave(&port->lock, flags);
0770 
0771     new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
0772     if (new_reg != up->curregs[R5]) {
0773         up->curregs[R5] = new_reg;
0774 
0775         /* NOTE: Not subject to 'transmitter active' rule.  */ 
0776         write_zsreg(channel, R5, up->curregs[R5]);
0777     }
0778 
0779     spin_unlock_irqrestore(&port->lock, flags);
0780 }
0781 
0782 static void __sunzilog_startup(struct uart_sunzilog_port *up)
0783 {
0784     struct zilog_channel __iomem *channel;
0785 
0786     channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
0787     up->prev_status = readb(&channel->control);
0788 
0789     /* Enable receiver and transmitter.  */
0790     up->curregs[R3] |= RxENAB;
0791     up->curregs[R5] |= TxENAB;
0792 
0793     up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
0794     sunzilog_maybe_update_regs(up, channel);
0795 }
0796 
0797 static int sunzilog_startup(struct uart_port *port)
0798 {
0799     struct uart_sunzilog_port *up = UART_ZILOG(port);
0800     unsigned long flags;
0801 
0802     if (ZS_IS_CONS(up))
0803         return 0;
0804 
0805     spin_lock_irqsave(&port->lock, flags);
0806     __sunzilog_startup(up);
0807     spin_unlock_irqrestore(&port->lock, flags);
0808     return 0;
0809 }
0810 
0811 /*
0812  * The test for ZS_IS_CONS is explained by the following e-mail:
0813  *****
0814  * From: Russell King <rmk@arm.linux.org.uk>
0815  * Date: Sun, 8 Dec 2002 10:18:38 +0000
0816  *
0817  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
0818  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
0819  * > and I noticed that something is not right with reference
0820  * > counting in this case. It seems that when the console
0821  * > is open by kernel initially, this is not accounted
0822  * > as an open, and uart_startup is not called.
0823  *
0824  * That is correct.  We are unable to call uart_startup when the serial
0825  * console is initialised because it may need to allocate memory (as
0826  * request_irq does) and the memory allocators may not have been
0827  * initialised.
0828  *
0829  * 1. initialise the port into a state where it can send characters in the
0830  *    console write method.
0831  *
0832  * 2. don't do the actual hardware shutdown in your shutdown() method (but
0833  *    do the normal software shutdown - ie, free irqs etc)
0834  *****
0835  */
0836 static void sunzilog_shutdown(struct uart_port *port)
0837 {
0838     struct uart_sunzilog_port *up = UART_ZILOG(port);
0839     struct zilog_channel __iomem *channel;
0840     unsigned long flags;
0841 
0842     if (ZS_IS_CONS(up))
0843         return;
0844 
0845     spin_lock_irqsave(&port->lock, flags);
0846 
0847     channel = ZILOG_CHANNEL_FROM_PORT(port);
0848 
0849     /* Disable receiver and transmitter.  */
0850     up->curregs[R3] &= ~RxENAB;
0851     up->curregs[R5] &= ~TxENAB;
0852 
0853     /* Disable all interrupts and BRK assertion.  */
0854     up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
0855     up->curregs[R5] &= ~SND_BRK;
0856     sunzilog_maybe_update_regs(up, channel);
0857 
0858     spin_unlock_irqrestore(&port->lock, flags);
0859 }
0860 
0861 /* Shared by TTY driver and serial console setup.  The port lock is held
0862  * and local interrupts are disabled.
0863  */
0864 static void
0865 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
0866                unsigned int iflag, int brg)
0867 {
0868 
0869     up->curregs[R10] = NRZ;
0870     up->curregs[R11] = TCBR | RCBR;
0871 
0872     /* Program BAUD and clock source. */
0873     up->curregs[R4] &= ~XCLK_MASK;
0874     up->curregs[R4] |= X16CLK;
0875     up->curregs[R12] = brg & 0xff;
0876     up->curregs[R13] = (brg >> 8) & 0xff;
0877     up->curregs[R14] = BRSRC | BRENAB;
0878 
0879     /* Character size, stop bits, and parity. */
0880     up->curregs[R3] &= ~RxN_MASK;
0881     up->curregs[R5] &= ~TxN_MASK;
0882     switch (cflag & CSIZE) {
0883     case CS5:
0884         up->curregs[R3] |= Rx5;
0885         up->curregs[R5] |= Tx5;
0886         up->parity_mask = 0x1f;
0887         break;
0888     case CS6:
0889         up->curregs[R3] |= Rx6;
0890         up->curregs[R5] |= Tx6;
0891         up->parity_mask = 0x3f;
0892         break;
0893     case CS7:
0894         up->curregs[R3] |= Rx7;
0895         up->curregs[R5] |= Tx7;
0896         up->parity_mask = 0x7f;
0897         break;
0898     case CS8:
0899     default:
0900         up->curregs[R3] |= Rx8;
0901         up->curregs[R5] |= Tx8;
0902         up->parity_mask = 0xff;
0903         break;
0904     }
0905     up->curregs[R4] &= ~0x0c;
0906     if (cflag & CSTOPB)
0907         up->curregs[R4] |= SB2;
0908     else
0909         up->curregs[R4] |= SB1;
0910     if (cflag & PARENB)
0911         up->curregs[R4] |= PAR_ENAB;
0912     else
0913         up->curregs[R4] &= ~PAR_ENAB;
0914     if (!(cflag & PARODD))
0915         up->curregs[R4] |= PAR_EVEN;
0916     else
0917         up->curregs[R4] &= ~PAR_EVEN;
0918 
0919     up->port.read_status_mask = Rx_OVR;
0920     if (iflag & INPCK)
0921         up->port.read_status_mask |= CRC_ERR | PAR_ERR;
0922     if (iflag & (IGNBRK | BRKINT | PARMRK))
0923         up->port.read_status_mask |= BRK_ABRT;
0924 
0925     up->port.ignore_status_mask = 0;
0926     if (iflag & IGNPAR)
0927         up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
0928     if (iflag & IGNBRK) {
0929         up->port.ignore_status_mask |= BRK_ABRT;
0930         if (iflag & IGNPAR)
0931             up->port.ignore_status_mask |= Rx_OVR;
0932     }
0933 
0934     if ((cflag & CREAD) == 0)
0935         up->port.ignore_status_mask = 0xff;
0936 }
0937 
0938 /* The port lock is not held.  */
0939 static void
0940 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
0941              struct ktermios *old)
0942 {
0943     struct uart_sunzilog_port *up =
0944         container_of(port, struct uart_sunzilog_port, port);
0945     unsigned long flags;
0946     int baud, brg;
0947 
0948     baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
0949 
0950     spin_lock_irqsave(&up->port.lock, flags);
0951 
0952     brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
0953 
0954     sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
0955 
0956     if (UART_ENABLE_MS(&up->port, termios->c_cflag))
0957         up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
0958     else
0959         up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
0960 
0961     up->cflag = termios->c_cflag;
0962 
0963     sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
0964 
0965     uart_update_timeout(port, termios->c_cflag, baud);
0966 
0967     spin_unlock_irqrestore(&up->port.lock, flags);
0968 }
0969 
0970 static const char *sunzilog_type(struct uart_port *port)
0971 {
0972     struct uart_sunzilog_port *up = UART_ZILOG(port);
0973 
0974     return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
0975 }
0976 
0977 /* We do not request/release mappings of the registers here, this
0978  * happens at early serial probe time.
0979  */
0980 static void sunzilog_release_port(struct uart_port *port)
0981 {
0982 }
0983 
0984 static int sunzilog_request_port(struct uart_port *port)
0985 {
0986     return 0;
0987 }
0988 
0989 /* These do not need to do anything interesting either.  */
0990 static void sunzilog_config_port(struct uart_port *port, int flags)
0991 {
0992 }
0993 
0994 /* We do not support letting the user mess with the divisor, IRQ, etc. */
0995 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
0996 {
0997     return -EINVAL;
0998 }
0999 
1000 #ifdef CONFIG_CONSOLE_POLL
1001 static int sunzilog_get_poll_char(struct uart_port *port)
1002 {
1003     unsigned char ch, r1;
1004     struct uart_sunzilog_port *up =
1005         container_of(port, struct uart_sunzilog_port, port);
1006     struct zilog_channel __iomem *channel
1007         = ZILOG_CHANNEL_FROM_PORT(&up->port);
1008 
1009 
1010     r1 = read_zsreg(channel, R1);
1011     if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1012         writeb(ERR_RES, &channel->control);
1013         ZSDELAY();
1014         ZS_WSYNC(channel);
1015     }
1016 
1017     ch = readb(&channel->control);
1018     ZSDELAY();
1019 
1020     /* This funny hack depends upon BRK_ABRT not interfering
1021      * with the other bits we care about in R1.
1022      */
1023     if (ch & BRK_ABRT)
1024         r1 |= BRK_ABRT;
1025 
1026     if (!(ch & Rx_CH_AV))
1027         return NO_POLL_CHAR;
1028 
1029     ch = readb(&channel->data);
1030     ZSDELAY();
1031 
1032     ch &= up->parity_mask;
1033     return ch;
1034 }
1035 
1036 static void sunzilog_put_poll_char(struct uart_port *port,
1037             unsigned char ch)
1038 {
1039     struct uart_sunzilog_port *up =
1040         container_of(port, struct uart_sunzilog_port, port);
1041 
1042     sunzilog_putchar(&up->port, ch);
1043 }
1044 #endif /* CONFIG_CONSOLE_POLL */
1045 
1046 static const struct uart_ops sunzilog_pops = {
1047     .tx_empty   =   sunzilog_tx_empty,
1048     .set_mctrl  =   sunzilog_set_mctrl,
1049     .get_mctrl  =   sunzilog_get_mctrl,
1050     .stop_tx    =   sunzilog_stop_tx,
1051     .start_tx   =   sunzilog_start_tx,
1052     .stop_rx    =   sunzilog_stop_rx,
1053     .enable_ms  =   sunzilog_enable_ms,
1054     .break_ctl  =   sunzilog_break_ctl,
1055     .startup    =   sunzilog_startup,
1056     .shutdown   =   sunzilog_shutdown,
1057     .set_termios    =   sunzilog_set_termios,
1058     .type       =   sunzilog_type,
1059     .release_port   =   sunzilog_release_port,
1060     .request_port   =   sunzilog_request_port,
1061     .config_port    =   sunzilog_config_port,
1062     .verify_port    =   sunzilog_verify_port,
1063 #ifdef CONFIG_CONSOLE_POLL
1064     .poll_get_char  =   sunzilog_get_poll_char,
1065     .poll_put_char  =   sunzilog_put_poll_char,
1066 #endif
1067 };
1068 
1069 static int uart_chip_count;
1070 static struct uart_sunzilog_port *sunzilog_port_table;
1071 static struct zilog_layout __iomem **sunzilog_chip_regs;
1072 
1073 static struct uart_sunzilog_port *sunzilog_irq_chain;
1074 
1075 static struct uart_driver sunzilog_reg = {
1076     .owner      =   THIS_MODULE,
1077     .driver_name    =   "sunzilog",
1078     .dev_name   =   "ttyS",
1079     .major      =   TTY_MAJOR,
1080 };
1081 
1082 static int __init sunzilog_alloc_tables(int num_sunzilog)
1083 {
1084     struct uart_sunzilog_port *up;
1085     unsigned long size;
1086     int num_channels = num_sunzilog * 2;
1087     int i;
1088 
1089     size = num_channels * sizeof(struct uart_sunzilog_port);
1090     sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1091     if (!sunzilog_port_table)
1092         return -ENOMEM;
1093 
1094     for (i = 0; i < num_channels; i++) {
1095         up = &sunzilog_port_table[i];
1096 
1097         spin_lock_init(&up->port.lock);
1098 
1099         if (i == 0)
1100             sunzilog_irq_chain = up;
1101 
1102         if (i < num_channels - 1)
1103             up->next = up + 1;
1104         else
1105             up->next = NULL;
1106     }
1107 
1108     size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1109     sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1110     if (!sunzilog_chip_regs) {
1111         kfree(sunzilog_port_table);
1112         sunzilog_irq_chain = NULL;
1113         return -ENOMEM;
1114     }
1115 
1116     return 0;
1117 }
1118 
1119 static void sunzilog_free_tables(void)
1120 {
1121     kfree(sunzilog_port_table);
1122     sunzilog_irq_chain = NULL;
1123     kfree(sunzilog_chip_regs);
1124 }
1125 
1126 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1127 
1128 static void __maybe_unused sunzilog_putchar(struct uart_port *port, unsigned char ch)
1129 {
1130     struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1131     int loops = ZS_PUT_CHAR_MAX_DELAY;
1132 
1133     /* This is a timed polling loop so do not switch the explicit
1134      * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1135      */
1136     do {
1137         unsigned char val = readb(&channel->control);
1138         if (val & Tx_BUF_EMP) {
1139             ZSDELAY();
1140             break;
1141         }
1142         udelay(5);
1143     } while (--loops);
1144 
1145     writeb(ch, &channel->data);
1146     ZSDELAY();
1147     ZS_WSYNC(channel);
1148 }
1149 
1150 #ifdef CONFIG_SERIO
1151 
1152 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1153 
1154 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1155 {
1156     struct uart_sunzilog_port *up = serio->port_data;
1157     unsigned long flags;
1158 
1159     spin_lock_irqsave(&sunzilog_serio_lock, flags);
1160 
1161     sunzilog_putchar(&up->port, ch);
1162 
1163     spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1164 
1165     return 0;
1166 }
1167 
1168 static int sunzilog_serio_open(struct serio *serio)
1169 {
1170     struct uart_sunzilog_port *up = serio->port_data;
1171     unsigned long flags;
1172     int ret;
1173 
1174     spin_lock_irqsave(&sunzilog_serio_lock, flags);
1175     if (!up->serio_open) {
1176         up->serio_open = 1;
1177         ret = 0;
1178     } else
1179         ret = -EBUSY;
1180     spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1181 
1182     return ret;
1183 }
1184 
1185 static void sunzilog_serio_close(struct serio *serio)
1186 {
1187     struct uart_sunzilog_port *up = serio->port_data;
1188     unsigned long flags;
1189 
1190     spin_lock_irqsave(&sunzilog_serio_lock, flags);
1191     up->serio_open = 0;
1192     spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1193 }
1194 
1195 #endif /* CONFIG_SERIO */
1196 
1197 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1198 static void
1199 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1200 {
1201     struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1202     unsigned long flags;
1203     int locked = 1;
1204 
1205     if (up->port.sysrq || oops_in_progress)
1206         locked = spin_trylock_irqsave(&up->port.lock, flags);
1207     else
1208         spin_lock_irqsave(&up->port.lock, flags);
1209 
1210     uart_console_write(&up->port, s, count, sunzilog_putchar);
1211     udelay(2);
1212 
1213     if (locked)
1214         spin_unlock_irqrestore(&up->port.lock, flags);
1215 }
1216 
1217 static int __init sunzilog_console_setup(struct console *con, char *options)
1218 {
1219     struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1220     unsigned long flags;
1221     int baud, brg;
1222 
1223     if (up->port.type != PORT_SUNZILOG)
1224         return -EINVAL;
1225 
1226     printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1227            (sunzilog_reg.minor - 64) + con->index, con->index);
1228 
1229     /* Get firmware console settings.  */
1230     sunserial_console_termios(con, up->port.dev->of_node);
1231 
1232     /* Firmware console speed is limited to 150-->38400 baud so
1233      * this hackish cflag thing is OK.
1234      */
1235     switch (con->cflag & CBAUD) {
1236     case B150: baud = 150; break;
1237     case B300: baud = 300; break;
1238     case B600: baud = 600; break;
1239     case B1200: baud = 1200; break;
1240     case B2400: baud = 2400; break;
1241     case B4800: baud = 4800; break;
1242     default: case B9600: baud = 9600; break;
1243     case B19200: baud = 19200; break;
1244     case B38400: baud = 38400; break;
1245     }
1246 
1247     brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1248 
1249     spin_lock_irqsave(&up->port.lock, flags);
1250 
1251     up->curregs[R15] |= BRKIE;
1252     sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1253 
1254     sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1255     __sunzilog_startup(up);
1256 
1257     spin_unlock_irqrestore(&up->port.lock, flags);
1258 
1259     return 0;
1260 }
1261 
1262 static struct console sunzilog_console_ops = {
1263     .name   =   "ttyS",
1264     .write  =   sunzilog_console_write,
1265     .device =   uart_console_device,
1266     .setup  =   sunzilog_console_setup,
1267     .flags  =   CON_PRINTBUFFER,
1268     .index  =   -1,
1269     .data   =   &sunzilog_reg,
1270 };
1271 
1272 static inline struct console *SUNZILOG_CONSOLE(void)
1273 {
1274     return &sunzilog_console_ops;
1275 }
1276 
1277 #else
1278 #define SUNZILOG_CONSOLE()  (NULL)
1279 #endif
1280 
1281 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1282 {
1283     int baud, brg;
1284 
1285     if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1286         up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1287         baud = 1200;
1288     } else {
1289         up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1290         baud = 4800;
1291     }
1292 
1293     up->curregs[R15] |= BRKIE;
1294     brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1295     sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1296     sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1297     __sunzilog_startup(up);
1298 }
1299 
1300 #ifdef CONFIG_SERIO
1301 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1302 {
1303     struct serio *serio = &up->serio;
1304 
1305     serio->port_data = up;
1306 
1307     serio->id.type = SERIO_RS232;
1308     if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1309         serio->id.proto = SERIO_SUNKBD;
1310         strlcpy(serio->name, "zskbd", sizeof(serio->name));
1311     } else {
1312         serio->id.proto = SERIO_SUN;
1313         serio->id.extra = 1;
1314         strlcpy(serio->name, "zsms", sizeof(serio->name));
1315     }
1316     strlcpy(serio->phys,
1317         ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1318          "zs/serio0" : "zs/serio1"),
1319         sizeof(serio->phys));
1320 
1321     serio->write = sunzilog_serio_write;
1322     serio->open = sunzilog_serio_open;
1323     serio->close = sunzilog_serio_close;
1324     serio->dev.parent = up->port.dev;
1325 
1326     serio_register_port(serio);
1327 }
1328 #endif
1329 
1330 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1331 {
1332     struct zilog_channel __iomem *channel;
1333     unsigned long flags;
1334     int baud, brg;
1335 
1336     channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1337 
1338     spin_lock_irqsave(&up->port.lock, flags);
1339     if (ZS_IS_CHANNEL_A(up)) {
1340         write_zsreg(channel, R9, FHWRES);
1341         ZSDELAY_LONG();
1342         (void) read_zsreg(channel, R0);
1343     }
1344 
1345     if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1346              SUNZILOG_FLAG_CONS_MOUSE)) {
1347         up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1348         up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1349         up->curregs[R3] = RxENAB | Rx8;
1350         up->curregs[R5] = TxENAB | Tx8;
1351         up->curregs[R6] = 0x00; /* SDLC Address */
1352         up->curregs[R7] = 0x7E; /* SDLC Flag    */
1353         up->curregs[R9] = NV;
1354         up->curregs[R7p] = 0x00;
1355         sunzilog_init_kbdms(up);
1356         /* Only enable interrupts if an ISR handler available */
1357         if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1358             up->curregs[R9] |= MIE;
1359         write_zsreg(channel, R9, up->curregs[R9]);
1360     } else {
1361         /* Normal serial TTY. */
1362         up->parity_mask = 0xff;
1363         up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1364         up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1365         up->curregs[R3] = RxENAB | Rx8;
1366         up->curregs[R5] = TxENAB | Tx8;
1367         up->curregs[R6] = 0x00; /* SDLC Address */
1368         up->curregs[R7] = 0x7E; /* SDLC Flag    */
1369         up->curregs[R9] = NV;
1370         up->curregs[R10] = NRZ;
1371         up->curregs[R11] = TCBR | RCBR;
1372         baud = 9600;
1373         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1374         up->curregs[R12] = (brg & 0xff);
1375         up->curregs[R13] = (brg >> 8) & 0xff;
1376         up->curregs[R14] = BRSRC | BRENAB;
1377         up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1378         up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1379         if (__load_zsregs(channel, up->curregs)) {
1380             up->flags |= SUNZILOG_FLAG_ESCC;
1381         }
1382         /* Only enable interrupts if an ISR handler available */
1383         if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1384             up->curregs[R9] |= MIE;
1385         write_zsreg(channel, R9, up->curregs[R9]);
1386     }
1387 
1388     spin_unlock_irqrestore(&up->port.lock, flags);
1389 
1390 #ifdef CONFIG_SERIO
1391     if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1392              SUNZILOG_FLAG_CONS_MOUSE))
1393         sunzilog_register_serio(up);
1394 #endif
1395 }
1396 
1397 static int zilog_irq;
1398 
1399 static int zs_probe(struct platform_device *op)
1400 {
1401     static int kbm_inst, uart_inst;
1402     int inst;
1403     struct uart_sunzilog_port *up;
1404     struct zilog_layout __iomem *rp;
1405     int keyboard_mouse = 0;
1406     int err;
1407 
1408     if (of_find_property(op->dev.of_node, "keyboard", NULL))
1409         keyboard_mouse = 1;
1410 
1411     /* uarts must come before keyboards/mice */
1412     if (keyboard_mouse)
1413         inst = uart_chip_count + kbm_inst;
1414     else
1415         inst = uart_inst;
1416 
1417     sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1418                           sizeof(struct zilog_layout),
1419                           "zs");
1420     if (!sunzilog_chip_regs[inst])
1421         return -ENOMEM;
1422 
1423     rp = sunzilog_chip_regs[inst];
1424 
1425     if (!zilog_irq)
1426         zilog_irq = op->archdata.irqs[0];
1427 
1428     up = &sunzilog_port_table[inst * 2];
1429 
1430     /* Channel A */
1431     up[0].port.mapbase = op->resource[0].start + 0x00;
1432     up[0].port.membase = (void __iomem *) &rp->channelA;
1433     up[0].port.iotype = UPIO_MEM;
1434     up[0].port.irq = op->archdata.irqs[0];
1435     up[0].port.uartclk = ZS_CLOCK;
1436     up[0].port.fifosize = 1;
1437     up[0].port.ops = &sunzilog_pops;
1438     up[0].port.type = PORT_SUNZILOG;
1439     up[0].port.flags = 0;
1440     up[0].port.line = (inst * 2) + 0;
1441     up[0].port.dev = &op->dev;
1442     up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1443     up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1444     if (keyboard_mouse)
1445         up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1446     sunzilog_init_hw(&up[0]);
1447 
1448     /* Channel B */
1449     up[1].port.mapbase = op->resource[0].start + 0x04;
1450     up[1].port.membase = (void __iomem *) &rp->channelB;
1451     up[1].port.iotype = UPIO_MEM;
1452     up[1].port.irq = op->archdata.irqs[0];
1453     up[1].port.uartclk = ZS_CLOCK;
1454     up[1].port.fifosize = 1;
1455     up[1].port.ops = &sunzilog_pops;
1456     up[1].port.type = PORT_SUNZILOG;
1457     up[1].port.flags = 0;
1458     up[1].port.line = (inst * 2) + 1;
1459     up[1].port.dev = &op->dev;
1460     up[1].flags |= 0;
1461     up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1462     if (keyboard_mouse)
1463         up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1464     sunzilog_init_hw(&up[1]);
1465 
1466     if (!keyboard_mouse) {
1467         if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1468                         &sunzilog_reg, up[0].port.line,
1469                         false))
1470             up->flags |= SUNZILOG_FLAG_IS_CONS;
1471         err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1472         if (err) {
1473             of_iounmap(&op->resource[0],
1474                    rp, sizeof(struct zilog_layout));
1475             return err;
1476         }
1477         if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1478                         &sunzilog_reg, up[1].port.line,
1479                         false))
1480             up->flags |= SUNZILOG_FLAG_IS_CONS;
1481         err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1482         if (err) {
1483             uart_remove_one_port(&sunzilog_reg, &up[0].port);
1484             of_iounmap(&op->resource[0],
1485                    rp, sizeof(struct zilog_layout));
1486             return err;
1487         }
1488         uart_inst++;
1489     } else {
1490         printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1491                "is a %s\n",
1492                dev_name(&op->dev),
1493                (unsigned long long) up[0].port.mapbase,
1494                op->archdata.irqs[0], sunzilog_type(&up[0].port));
1495         printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1496                "is a %s\n",
1497                dev_name(&op->dev),
1498                (unsigned long long) up[1].port.mapbase,
1499                op->archdata.irqs[0], sunzilog_type(&up[1].port));
1500         kbm_inst++;
1501     }
1502 
1503     platform_set_drvdata(op, &up[0]);
1504 
1505     return 0;
1506 }
1507 
1508 static void zs_remove_one(struct uart_sunzilog_port *up)
1509 {
1510     if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1511 #ifdef CONFIG_SERIO
1512         serio_unregister_port(&up->serio);
1513 #endif
1514     } else
1515         uart_remove_one_port(&sunzilog_reg, &up->port);
1516 }
1517 
1518 static int zs_remove(struct platform_device *op)
1519 {
1520     struct uart_sunzilog_port *up = platform_get_drvdata(op);
1521     struct zilog_layout __iomem *regs;
1522 
1523     zs_remove_one(&up[0]);
1524     zs_remove_one(&up[1]);
1525 
1526     regs = sunzilog_chip_regs[up[0].port.line / 2];
1527     of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1528 
1529     return 0;
1530 }
1531 
1532 static const struct of_device_id zs_match[] = {
1533     {
1534         .name = "zs",
1535     },
1536     {},
1537 };
1538 MODULE_DEVICE_TABLE(of, zs_match);
1539 
1540 static struct platform_driver zs_driver = {
1541     .driver = {
1542         .name = "zs",
1543         .of_match_table = zs_match,
1544     },
1545     .probe      = zs_probe,
1546     .remove     = zs_remove,
1547 };
1548 
1549 static int __init sunzilog_init(void)
1550 {
1551     struct device_node *dp;
1552     int err;
1553     int num_keybms = 0;
1554     int num_sunzilog = 0;
1555 
1556     for_each_node_by_name(dp, "zs") {
1557         num_sunzilog++;
1558         if (of_find_property(dp, "keyboard", NULL))
1559             num_keybms++;
1560     }
1561 
1562     if (num_sunzilog) {
1563         err = sunzilog_alloc_tables(num_sunzilog);
1564         if (err)
1565             goto out;
1566 
1567         uart_chip_count = num_sunzilog - num_keybms;
1568 
1569         err = sunserial_register_minors(&sunzilog_reg,
1570                         uart_chip_count * 2);
1571         if (err)
1572             goto out_free_tables;
1573     }
1574 
1575     err = platform_driver_register(&zs_driver);
1576     if (err)
1577         goto out_unregister_uart;
1578 
1579     if (zilog_irq) {
1580         struct uart_sunzilog_port *up = sunzilog_irq_chain;
1581         err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1582                   "zs", sunzilog_irq_chain);
1583         if (err)
1584             goto out_unregister_driver;
1585 
1586         /* Enable Interrupts */
1587         while (up) {
1588             struct zilog_channel __iomem *channel;
1589 
1590             /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1591             channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1592             up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1593             up->curregs[R9] |= MIE;
1594             write_zsreg(channel, R9, up->curregs[R9]);
1595             up = up->next;
1596         }
1597     }
1598 
1599 out:
1600     return err;
1601 
1602 out_unregister_driver:
1603     platform_driver_unregister(&zs_driver);
1604 
1605 out_unregister_uart:
1606     if (num_sunzilog) {
1607         sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1608         sunzilog_reg.cons = NULL;
1609     }
1610 
1611 out_free_tables:
1612     sunzilog_free_tables();
1613     goto out;
1614 }
1615 
1616 static void __exit sunzilog_exit(void)
1617 {
1618     platform_driver_unregister(&zs_driver);
1619 
1620     if (zilog_irq) {
1621         struct uart_sunzilog_port *up = sunzilog_irq_chain;
1622 
1623         /* Disable Interrupts */
1624         while (up) {
1625             struct zilog_channel __iomem *channel;
1626 
1627             /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1628             channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1629             up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1630             up->curregs[R9] &= ~MIE;
1631             write_zsreg(channel, R9, up->curregs[R9]);
1632             up = up->next;
1633         }
1634 
1635         free_irq(zilog_irq, sunzilog_irq_chain);
1636         zilog_irq = 0;
1637     }
1638 
1639     if (sunzilog_reg.nr) {
1640         sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1641         sunzilog_free_tables();
1642     }
1643 }
1644 
1645 module_init(sunzilog_init);
1646 module_exit(sunzilog_exit);
1647 
1648 MODULE_AUTHOR("David S. Miller");
1649 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1650 MODULE_VERSION("2.0");
1651 MODULE_LICENSE("GPL");
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