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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC
0003  *
0004  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
0005  */
0006 
0007 #ifndef _SUNSAB_H
0008 #define _SUNSAB_H
0009 
0010 struct sab82532_async_rd_regs {
0011     u8  rfifo[0x20];    /* Receive FIFO             */
0012     u8  star;       /* Status Register          */
0013     u8  __pad1;
0014     u8  mode;       /* Mode Register            */
0015     u8  timr;       /* Timer Register           */
0016     u8  xon;        /* XON Character            */
0017     u8  xoff;       /* XOFF Character           */
0018     u8  tcr;        /* Termination Character Register   */
0019     u8  dafo;       /* Data Format              */
0020     u8  rfc;        /* RFIFO Control Register       */
0021     u8  __pad2;
0022     u8  rbcl;       /* Receive Byte Count Low       */
0023     u8  rbch;       /* Receive Byte Count High      */
0024     u8  ccr0;       /* Channel Configuration Register 0 */
0025     u8  ccr1;       /* Channel Configuration Register 1 */
0026     u8  ccr2;       /* Channel Configuration Register 2 */
0027     u8  ccr3;       /* Channel Configuration Register 3 */
0028     u8  __pad3[4];
0029     u8  vstr;       /* Version Status Register      */
0030     u8  __pad4[3];
0031     u8  gis;        /* Global Interrupt Status      */
0032     u8  ipc;        /* Interrupt Port Configuration     */
0033     u8  isr0;       /* Interrupt Status 0           */
0034     u8  isr1;       /* Interrupt Status 1           */
0035     u8  pvr;        /* Port Value Register          */
0036     u8  pis;        /* Port Interrupt Status        */
0037     u8  pcr;        /* Port Configuration Register      */
0038     u8  ccr4;       /* Channel Configuration Register 4 */
0039 };
0040 
0041 struct sab82532_async_wr_regs {
0042     u8  xfifo[0x20];    /* Transmit FIFO            */
0043     u8  cmdr;       /* Command Register         */
0044     u8  __pad1;
0045     u8  mode;
0046     u8  timr;
0047     u8  xon;
0048     u8  xoff;
0049     u8  tcr;
0050     u8  dafo;
0051     u8  rfc;
0052     u8  __pad2;
0053     u8  xbcl;       /* Transmit Byte Count Low      */
0054     u8  xbch;       /* Transmit Byte Count High     */
0055     u8  ccr0;
0056     u8  ccr1;
0057     u8  ccr2;
0058     u8  ccr3;
0059     u8  tsax;       /* Time-Slot Assignment Reg. Transmit   */
0060     u8  tsar;       /* Time-Slot Assignment Reg. Receive    */
0061     u8  xccr;       /* Transmit Channel Capacity Register   */
0062     u8  rccr;       /* Receive Channel Capacity Register    */
0063     u8  bgr;        /* Baud Rate Generator Register     */
0064     u8  tic;        /* Transmit Immediate Character     */
0065     u8  mxn;        /* Mask XON Character           */
0066     u8  mxf;        /* Mask XOFF Character          */
0067     u8  iva;        /* Interrupt Vector Address     */
0068     u8  ipc;
0069     u8  imr0;       /* Interrupt Mask Register 0        */
0070     u8  imr1;       /* Interrupt Mask Register 1        */
0071     u8  pvr;
0072     u8  pim;        /* Port Interrupt Mask          */
0073     u8  pcr;
0074     u8  ccr4;
0075 };
0076 
0077 struct sab82532_async_rw_regs { /* Read/Write registers         */
0078     u8  __pad1[0x20];
0079     u8  __pad2;
0080     u8  __pad3;
0081     u8  mode;
0082     u8  timr;
0083     u8  xon;
0084     u8  xoff;
0085     u8  tcr;
0086     u8  dafo;
0087     u8  rfc;
0088     u8  __pad4;
0089     u8  __pad5;
0090     u8  __pad6;
0091     u8  ccr0;
0092     u8  ccr1;
0093     u8  ccr2;
0094     u8  ccr3;
0095     u8  __pad7;
0096     u8  __pad8;
0097     u8  __pad9;
0098     u8  __pad10;
0099     u8  __pad11;
0100     u8  __pad12;
0101     u8  __pad13;
0102     u8  __pad14;
0103     u8  __pad15;
0104     u8  ipc;
0105     u8  __pad16;
0106     u8  __pad17;
0107     u8  pvr;
0108     u8  __pad18;
0109     u8  pcr;
0110     u8  ccr4;
0111 };
0112 
0113 union sab82532_async_regs {
0114     __volatile__ struct sab82532_async_rd_regs  r;
0115     __volatile__ struct sab82532_async_wr_regs  w;
0116     __volatile__ struct sab82532_async_rw_regs  rw;
0117 };
0118 
0119 union sab82532_irq_status {
0120     unsigned short           stat;
0121     struct {
0122         unsigned char        isr0;
0123         unsigned char        isr1;
0124     } sreg;
0125 };
0126 
0127 /* irqflags bits */
0128 #define SAB82532_ALLS           0x00000001
0129 #define SAB82532_XPR            0x00000002
0130 #define SAB82532_REGS_PENDING       0x00000004
0131 
0132 /* RFIFO Status Byte */
0133 #define SAB82532_RSTAT_PE       0x80
0134 #define SAB82532_RSTAT_FE       0x40
0135 #define SAB82532_RSTAT_PARITY       0x01
0136 
0137 /* Status Register (STAR) */
0138 #define SAB82532_STAR_XDOV      0x80
0139 #define SAB82532_STAR_XFW       0x40
0140 #define SAB82532_STAR_RFNE      0x20
0141 #define SAB82532_STAR_FCS       0x10
0142 #define SAB82532_STAR_TEC       0x08
0143 #define SAB82532_STAR_CEC       0x04
0144 #define SAB82532_STAR_CTS       0x02
0145 
0146 /* Command Register (CMDR) */
0147 #define SAB82532_CMDR_RMC       0x80
0148 #define SAB82532_CMDR_RRES      0x40
0149 #define SAB82532_CMDR_RFRD      0x20
0150 #define SAB82532_CMDR_STI       0x10
0151 #define SAB82532_CMDR_XF        0x08
0152 #define SAB82532_CMDR_XRES      0x01
0153 
0154 /* Mode Register (MODE) */
0155 #define SAB82532_MODE_FRTS      0x40
0156 #define SAB82532_MODE_FCTS      0x20
0157 #define SAB82532_MODE_FLON      0x10
0158 #define SAB82532_MODE_RAC       0x08
0159 #define SAB82532_MODE_RTS       0x04
0160 #define SAB82532_MODE_TRS       0x02
0161 #define SAB82532_MODE_TLP       0x01
0162 
0163 /* Timer Register (TIMR) */
0164 #define SAB82532_TIMR_CNT_MASK      0xe0
0165 #define SAB82532_TIMR_VALUE_MASK    0x1f
0166 
0167 /* Data Format (DAFO) */
0168 #define SAB82532_DAFO_XBRK      0x40
0169 #define SAB82532_DAFO_STOP      0x20
0170 #define SAB82532_DAFO_PAR_SPACE     0x00
0171 #define SAB82532_DAFO_PAR_ODD       0x08
0172 #define SAB82532_DAFO_PAR_EVEN      0x10
0173 #define SAB82532_DAFO_PAR_MARK      0x18
0174 #define SAB82532_DAFO_PARE      0x04
0175 #define SAB82532_DAFO_CHL8      0x00
0176 #define SAB82532_DAFO_CHL7      0x01
0177 #define SAB82532_DAFO_CHL6      0x02
0178 #define SAB82532_DAFO_CHL5      0x03
0179 
0180 /* RFIFO Control Register (RFC) */
0181 #define SAB82532_RFC_DPS        0x40
0182 #define SAB82532_RFC_DXS        0x20
0183 #define SAB82532_RFC_RFDF       0x10
0184 #define SAB82532_RFC_RFTH_1     0x00
0185 #define SAB82532_RFC_RFTH_4     0x04
0186 #define SAB82532_RFC_RFTH_16        0x08
0187 #define SAB82532_RFC_RFTH_32        0x0c
0188 #define SAB82532_RFC_TCDE       0x01
0189 
0190 /* Received Byte Count High (RBCH) */
0191 #define SAB82532_RBCH_DMA       0x80
0192 #define SAB82532_RBCH_CAS       0x20
0193 
0194 /* Transmit Byte Count High (XBCH) */
0195 #define SAB82532_XBCH_DMA       0x80
0196 #define SAB82532_XBCH_CAS       0x20
0197 #define SAB82532_XBCH_XC        0x10
0198 
0199 /* Channel Configuration Register 0 (CCR0) */
0200 #define SAB82532_CCR0_PU        0x80
0201 #define SAB82532_CCR0_MCE       0x40
0202 #define SAB82532_CCR0_SC_NRZ        0x00
0203 #define SAB82532_CCR0_SC_NRZI       0x08
0204 #define SAB82532_CCR0_SC_FM0        0x10
0205 #define SAB82532_CCR0_SC_FM1        0x14
0206 #define SAB82532_CCR0_SC_MANCH      0x18
0207 #define SAB82532_CCR0_SM_HDLC       0x00
0208 #define SAB82532_CCR0_SM_SDLC_LOOP  0x01
0209 #define SAB82532_CCR0_SM_BISYNC     0x02
0210 #define SAB82532_CCR0_SM_ASYNC      0x03
0211 
0212 /* Channel Configuration Register 1 (CCR1) */
0213 #define SAB82532_CCR1_ODS       0x10
0214 #define SAB82532_CCR1_BCR       0x08
0215 #define SAB82532_CCR1_CM_MASK       0x07
0216 
0217 /* Channel Configuration Register 2 (CCR2) */
0218 #define SAB82532_CCR2_SOC1      0x80
0219 #define SAB82532_CCR2_SOC0      0x40
0220 #define SAB82532_CCR2_BR9       0x80
0221 #define SAB82532_CCR2_BR8       0x40
0222 #define SAB82532_CCR2_BDF       0x20
0223 #define SAB82532_CCR2_SSEL      0x10
0224 #define SAB82532_CCR2_XCS0      0x20
0225 #define SAB82532_CCR2_RCS0      0x10
0226 #define SAB82532_CCR2_TOE       0x08
0227 #define SAB82532_CCR2_RWX       0x04
0228 #define SAB82532_CCR2_DIV       0x01
0229 
0230 /* Channel Configuration Register 3 (CCR3) */
0231 #define SAB82532_CCR3_PSD       0x01
0232 
0233 /* Time Slot Assignment Register Transmit (TSAX) */
0234 #define SAB82532_TSAX_TSNX_MASK     0xfc
0235 #define SAB82532_TSAX_XCS2      0x02    /* see also CCR2 */
0236 #define SAB82532_TSAX_XCS1      0x01
0237 
0238 /* Time Slot Assignment Register Receive (TSAR) */
0239 #define SAB82532_TSAR_TSNR_MASK     0xfc
0240 #define SAB82532_TSAR_RCS2      0x02    /* see also CCR2 */
0241 #define SAB82532_TSAR_RCS1      0x01
0242 
0243 /* Version Status Register (VSTR) */
0244 #define SAB82532_VSTR_CD        0x80
0245 #define SAB82532_VSTR_DPLA      0x40
0246 #define SAB82532_VSTR_VN_MASK       0x0f
0247 #define SAB82532_VSTR_VN_1      0x00
0248 #define SAB82532_VSTR_VN_2      0x01
0249 #define SAB82532_VSTR_VN_3_2        0x02
0250 
0251 /* Global Interrupt Status Register (GIS) */
0252 #define SAB82532_GIS_PI         0x80
0253 #define SAB82532_GIS_ISA1       0x08
0254 #define SAB82532_GIS_ISA0       0x04
0255 #define SAB82532_GIS_ISB1       0x02
0256 #define SAB82532_GIS_ISB0       0x01
0257 
0258 /* Interrupt Vector Address (IVA) */
0259 #define SAB82532_IVA_MASK       0xf1
0260 
0261 /* Interrupt Port Configuration (IPC) */
0262 #define SAB82532_IPC_VIS        0x80
0263 #define SAB82532_IPC_SLA1       0x10
0264 #define SAB82532_IPC_SLA0       0x08
0265 #define SAB82532_IPC_CASM       0x04
0266 #define SAB82532_IPC_IC_OPEN_DRAIN  0x00
0267 #define SAB82532_IPC_IC_ACT_LOW     0x01
0268 #define SAB82532_IPC_IC_ACT_HIGH    0x03
0269 
0270 /* Interrupt Status Register 0 (ISR0) */
0271 #define SAB82532_ISR0_TCD       0x80
0272 #define SAB82532_ISR0_TIME      0x40
0273 #define SAB82532_ISR0_PERR      0x20
0274 #define SAB82532_ISR0_FERR      0x10
0275 #define SAB82532_ISR0_PLLA      0x08
0276 #define SAB82532_ISR0_CDSC      0x04
0277 #define SAB82532_ISR0_RFO       0x02
0278 #define SAB82532_ISR0_RPF       0x01
0279 
0280 /* Interrupt Status Register 1 (ISR1) */
0281 #define SAB82532_ISR1_BRK       0x80
0282 #define SAB82532_ISR1_BRKT      0x40
0283 #define SAB82532_ISR1_ALLS      0x20
0284 #define SAB82532_ISR1_XOFF      0x10
0285 #define SAB82532_ISR1_TIN       0x08
0286 #define SAB82532_ISR1_CSC       0x04
0287 #define SAB82532_ISR1_XON       0x02
0288 #define SAB82532_ISR1_XPR       0x01
0289 
0290 /* Interrupt Mask Register 0 (IMR0) */
0291 #define SAB82532_IMR0_TCD       0x80
0292 #define SAB82532_IMR0_TIME      0x40
0293 #define SAB82532_IMR0_PERR      0x20
0294 #define SAB82532_IMR0_FERR      0x10
0295 #define SAB82532_IMR0_PLLA      0x08
0296 #define SAB82532_IMR0_CDSC      0x04
0297 #define SAB82532_IMR0_RFO       0x02
0298 #define SAB82532_IMR0_RPF       0x01
0299 
0300 /* Interrupt Mask Register 1 (IMR1) */
0301 #define SAB82532_IMR1_BRK       0x80
0302 #define SAB82532_IMR1_BRKT      0x40
0303 #define SAB82532_IMR1_ALLS      0x20
0304 #define SAB82532_IMR1_XOFF      0x10
0305 #define SAB82532_IMR1_TIN       0x08
0306 #define SAB82532_IMR1_CSC       0x04
0307 #define SAB82532_IMR1_XON       0x02
0308 #define SAB82532_IMR1_XPR       0x01
0309 
0310 /* Port Interrupt Status Register (PIS) */
0311 #define SAB82532_PIS_SYNC_B     0x08
0312 #define SAB82532_PIS_DTR_B      0x04
0313 #define SAB82532_PIS_DTR_A      0x02
0314 #define SAB82532_PIS_SYNC_A     0x01
0315 
0316 /* Channel Configuration Register 4 (CCR4) */
0317 #define SAB82532_CCR4_MCK4      0x80
0318 #define SAB82532_CCR4_EBRG      0x40
0319 #define SAB82532_CCR4_TST1      0x20
0320 #define SAB82532_CCR4_ICD       0x10
0321 
0322 
0323 #endif /* !(_SUNSAB_H) */
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