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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
0003  *
0004  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
0005  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
0006  *
0007  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
0008  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
0009  *
0010  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
0011  * rates to be programmed into the UART.  Also eliminated a lot of
0012  * duplicated code in the console setup.
0013  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
0014  *
0015  * Ported to new 2.5.x UART layer.
0016  *   David S. Miller <davem@davemloft.net>
0017  */
0018 
0019 #include <linux/module.h>
0020 #include <linux/kernel.h>
0021 #include <linux/errno.h>
0022 #include <linux/tty.h>
0023 #include <linux/tty_flip.h>
0024 #include <linux/major.h>
0025 #include <linux/string.h>
0026 #include <linux/ptrace.h>
0027 #include <linux/ioport.h>
0028 #include <linux/circ_buf.h>
0029 #include <linux/serial.h>
0030 #include <linux/sysrq.h>
0031 #include <linux/console.h>
0032 #include <linux/spinlock.h>
0033 #include <linux/slab.h>
0034 #include <linux/delay.h>
0035 #include <linux/init.h>
0036 #include <linux/of_device.h>
0037 
0038 #include <linux/io.h>
0039 #include <asm/irq.h>
0040 #include <asm/prom.h>
0041 #include <asm/setup.h>
0042 
0043 #include <linux/serial_core.h>
0044 #include <linux/sunserialcore.h>
0045 
0046 #include "sunsab.h"
0047 
0048 struct uart_sunsab_port {
0049     struct uart_port        port;       /* Generic UART port    */
0050     union sab82532_async_regs   __iomem *regs;  /* Chip registers   */
0051     unsigned long           irqflags;   /* IRQ state flags  */
0052     int             dsr;        /* Current DSR state    */
0053     unsigned int            cec_timeout;    /* Chip poll timeout... */
0054     unsigned int            tec_timeout;    /* likewise     */
0055     unsigned char           interrupt_mask0;/* ISR0 masking     */
0056     unsigned char           interrupt_mask1;/* ISR1 masking     */
0057     unsigned char           pvr_dtr_bit;    /* Which PVR bit is DTR */
0058     unsigned char           pvr_dsr_bit;    /* Which PVR bit is DSR */
0059     unsigned int            gis_shift;
0060     int             type;       /* SAB82532 version */
0061 
0062     /* Setting configuration bits while the transmitter is active
0063      * can cause garbage characters to get emitted by the chip.
0064      * Therefore, we cache such writes here and do the real register
0065      * write the next time the transmitter becomes idle.
0066      */
0067     unsigned int            cached_ebrg;
0068     unsigned char           cached_mode;
0069     unsigned char           cached_pvr;
0070     unsigned char           cached_dafo;
0071 };
0072 
0073 /*
0074  * This assumes you have a 29.4912 MHz clock for your UART.
0075  */
0076 #define SAB_BASE_BAUD ( 29491200 / 16 )
0077 
0078 static char *sab82532_version[16] = {
0079     "V1.0", "V2.0", "V3.2", "V(0x03)",
0080     "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
0081     "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
0082     "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
0083 };
0084 
0085 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
0086 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
0087 
0088 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
0089 #define SAB82532_XMIT_FIFO_SIZE 32
0090 
0091 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
0092 {
0093     int timeout = up->tec_timeout;
0094 
0095     while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
0096         udelay(1);
0097 }
0098 
0099 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
0100 {
0101     int timeout = up->cec_timeout;
0102 
0103     while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
0104         udelay(1);
0105 }
0106 
0107 static struct tty_port *
0108 receive_chars(struct uart_sunsab_port *up,
0109           union sab82532_irq_status *stat)
0110 {
0111     struct tty_port *port = NULL;
0112     unsigned char buf[32];
0113     int saw_console_brk = 0;
0114     int free_fifo = 0;
0115     int count = 0;
0116     int i;
0117 
0118     if (up->port.state != NULL)     /* Unopened serial console */
0119         port = &up->port.state->port;
0120 
0121     /* Read number of BYTES (Character + Status) available. */
0122     if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
0123         count = SAB82532_RECV_FIFO_SIZE;
0124         free_fifo++;
0125     }
0126 
0127     if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
0128         count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
0129         free_fifo++;
0130     }
0131 
0132     /* Issue a FIFO read command in case we where idle. */
0133     if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
0134         sunsab_cec_wait(up);
0135         writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
0136         return port;
0137     }
0138 
0139     if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
0140         free_fifo++;
0141 
0142     /* Read the FIFO. */
0143     for (i = 0; i < count; i++)
0144         buf[i] = readb(&up->regs->r.rfifo[i]);
0145 
0146     /* Issue Receive Message Complete command. */
0147     if (free_fifo) {
0148         sunsab_cec_wait(up);
0149         writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
0150     }
0151 
0152     /* Count may be zero for BRK, so we check for it here */
0153     if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
0154         (up->port.line == up->port.cons->index))
0155         saw_console_brk = 1;
0156 
0157     if (count == 0) {
0158         if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
0159             stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
0160                          SAB82532_ISR0_FERR);
0161             up->port.icount.brk++;
0162             uart_handle_break(&up->port);
0163         }
0164     }
0165 
0166     for (i = 0; i < count; i++) {
0167         unsigned char ch = buf[i], flag;
0168 
0169         flag = TTY_NORMAL;
0170         up->port.icount.rx++;
0171 
0172         if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
0173                         SAB82532_ISR0_FERR |
0174                         SAB82532_ISR0_RFO)) ||
0175             unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
0176             /*
0177              * For statistics only
0178              */
0179             if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
0180                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
0181                              SAB82532_ISR0_FERR);
0182                 up->port.icount.brk++;
0183                 /*
0184                  * We do the SysRQ and SAK checking
0185                  * here because otherwise the break
0186                  * may get masked by ignore_status_mask
0187                  * or read_status_mask.
0188                  */
0189                 if (uart_handle_break(&up->port))
0190                     continue;
0191             } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
0192                 up->port.icount.parity++;
0193             else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
0194                 up->port.icount.frame++;
0195             if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
0196                 up->port.icount.overrun++;
0197 
0198             /*
0199              * Mask off conditions which should be ingored.
0200              */
0201             stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
0202             stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
0203 
0204             if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
0205                 flag = TTY_BREAK;
0206             } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
0207                 flag = TTY_PARITY;
0208             else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
0209                 flag = TTY_FRAME;
0210         }
0211 
0212         if (uart_handle_sysrq_char(&up->port, ch) || !port)
0213             continue;
0214 
0215         if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
0216             (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
0217             tty_insert_flip_char(port, ch, flag);
0218         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
0219             tty_insert_flip_char(port, 0, TTY_OVERRUN);
0220     }
0221 
0222     if (saw_console_brk)
0223         sun_do_break();
0224 
0225     return port;
0226 }
0227 
0228 static void sunsab_stop_tx(struct uart_port *);
0229 static void sunsab_tx_idle(struct uart_sunsab_port *);
0230 
0231 static void transmit_chars(struct uart_sunsab_port *up,
0232                union sab82532_irq_status *stat)
0233 {
0234     struct circ_buf *xmit = &up->port.state->xmit;
0235     int i;
0236 
0237     if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
0238         up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
0239         writeb(up->interrupt_mask1, &up->regs->w.imr1);
0240         set_bit(SAB82532_ALLS, &up->irqflags);
0241     }
0242 
0243 #if 0 /* bde@nwlink.com says this check causes problems */
0244     if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
0245         return;
0246 #endif
0247 
0248     if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
0249         return;
0250 
0251     set_bit(SAB82532_XPR, &up->irqflags);
0252     sunsab_tx_idle(up);
0253 
0254     if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
0255         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
0256         writeb(up->interrupt_mask1, &up->regs->w.imr1);
0257         return;
0258     }
0259 
0260     up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
0261     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0262     clear_bit(SAB82532_ALLS, &up->irqflags);
0263 
0264     /* Stuff 32 bytes into Transmit FIFO. */
0265     clear_bit(SAB82532_XPR, &up->irqflags);
0266     for (i = 0; i < up->port.fifosize; i++) {
0267         writeb(xmit->buf[xmit->tail],
0268                &up->regs->w.xfifo[i]);
0269         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0270         up->port.icount.tx++;
0271         if (uart_circ_empty(xmit))
0272             break;
0273     }
0274 
0275     /* Issue a Transmit Frame command. */
0276     sunsab_cec_wait(up);
0277     writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
0278 
0279     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0280         uart_write_wakeup(&up->port);
0281 
0282     if (uart_circ_empty(xmit))
0283         sunsab_stop_tx(&up->port);
0284 }
0285 
0286 static void check_status(struct uart_sunsab_port *up,
0287              union sab82532_irq_status *stat)
0288 {
0289     if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
0290         uart_handle_dcd_change(&up->port,
0291                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
0292 
0293     if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
0294         uart_handle_cts_change(&up->port,
0295                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
0296 
0297     if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
0298         up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
0299         up->port.icount.dsr++;
0300     }
0301 
0302     wake_up_interruptible(&up->port.state->port.delta_msr_wait);
0303 }
0304 
0305 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
0306 {
0307     struct uart_sunsab_port *up = dev_id;
0308     struct tty_port *port = NULL;
0309     union sab82532_irq_status status;
0310     unsigned long flags;
0311     unsigned char gis;
0312 
0313     spin_lock_irqsave(&up->port.lock, flags);
0314 
0315     status.stat = 0;
0316     gis = readb(&up->regs->r.gis) >> up->gis_shift;
0317     if (gis & 1)
0318         status.sreg.isr0 = readb(&up->regs->r.isr0);
0319     if (gis & 2)
0320         status.sreg.isr1 = readb(&up->regs->r.isr1);
0321 
0322     if (status.stat) {
0323         if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
0324                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
0325             (status.sreg.isr1 & SAB82532_ISR1_BRK))
0326             port = receive_chars(up, &status);
0327         if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
0328             (status.sreg.isr1 & SAB82532_ISR1_CSC))
0329             check_status(up, &status);
0330         if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
0331             transmit_chars(up, &status);
0332     }
0333 
0334     spin_unlock_irqrestore(&up->port.lock, flags);
0335 
0336     if (port)
0337         tty_flip_buffer_push(port);
0338 
0339     return IRQ_HANDLED;
0340 }
0341 
0342 /* port->lock is not held.  */
0343 static unsigned int sunsab_tx_empty(struct uart_port *port)
0344 {
0345     struct uart_sunsab_port *up =
0346         container_of(port, struct uart_sunsab_port, port);
0347     int ret;
0348 
0349     /* Do not need a lock for a state test like this.  */
0350     if (test_bit(SAB82532_ALLS, &up->irqflags))
0351         ret = TIOCSER_TEMT;
0352     else
0353         ret = 0;
0354 
0355     return ret;
0356 }
0357 
0358 /* port->lock held by caller.  */
0359 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
0360 {
0361     struct uart_sunsab_port *up =
0362         container_of(port, struct uart_sunsab_port, port);
0363 
0364     if (mctrl & TIOCM_RTS) {
0365         up->cached_mode &= ~SAB82532_MODE_FRTS;
0366         up->cached_mode |= SAB82532_MODE_RTS;
0367     } else {
0368         up->cached_mode |= (SAB82532_MODE_FRTS |
0369                     SAB82532_MODE_RTS);
0370     }
0371     if (mctrl & TIOCM_DTR) {
0372         up->cached_pvr &= ~(up->pvr_dtr_bit);
0373     } else {
0374         up->cached_pvr |= up->pvr_dtr_bit;
0375     }
0376 
0377     set_bit(SAB82532_REGS_PENDING, &up->irqflags);
0378     if (test_bit(SAB82532_XPR, &up->irqflags))
0379         sunsab_tx_idle(up);
0380 }
0381 
0382 /* port->lock is held by caller and interrupts are disabled.  */
0383 static unsigned int sunsab_get_mctrl(struct uart_port *port)
0384 {
0385     struct uart_sunsab_port *up =
0386         container_of(port, struct uart_sunsab_port, port);
0387     unsigned char val;
0388     unsigned int result;
0389 
0390     result = 0;
0391 
0392     val = readb(&up->regs->r.pvr);
0393     result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
0394 
0395     val = readb(&up->regs->r.vstr);
0396     result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
0397 
0398     val = readb(&up->regs->r.star);
0399     result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
0400 
0401     return result;
0402 }
0403 
0404 /* port->lock held by caller.  */
0405 static void sunsab_stop_tx(struct uart_port *port)
0406 {
0407     struct uart_sunsab_port *up =
0408         container_of(port, struct uart_sunsab_port, port);
0409 
0410     up->interrupt_mask1 |= SAB82532_IMR1_XPR;
0411     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0412 }
0413 
0414 /* port->lock held by caller.  */
0415 static void sunsab_tx_idle(struct uart_sunsab_port *up)
0416 {
0417     if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
0418         u8 tmp;
0419 
0420         clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
0421         writeb(up->cached_mode, &up->regs->rw.mode);
0422         writeb(up->cached_pvr, &up->regs->rw.pvr);
0423         writeb(up->cached_dafo, &up->regs->w.dafo);
0424 
0425         writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
0426         tmp = readb(&up->regs->rw.ccr2);
0427         tmp &= ~0xc0;
0428         tmp |= (up->cached_ebrg >> 2) & 0xc0;
0429         writeb(tmp, &up->regs->rw.ccr2);
0430     }
0431 }
0432 
0433 /* port->lock held by caller.  */
0434 static void sunsab_start_tx(struct uart_port *port)
0435 {
0436     struct uart_sunsab_port *up =
0437         container_of(port, struct uart_sunsab_port, port);
0438     struct circ_buf *xmit = &up->port.state->xmit;
0439     int i;
0440 
0441     if (uart_circ_empty(xmit) || uart_tx_stopped(port))
0442         return;
0443 
0444     up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
0445     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0446     
0447     if (!test_bit(SAB82532_XPR, &up->irqflags))
0448         return;
0449 
0450     clear_bit(SAB82532_ALLS, &up->irqflags);
0451     clear_bit(SAB82532_XPR, &up->irqflags);
0452 
0453     for (i = 0; i < up->port.fifosize; i++) {
0454         writeb(xmit->buf[xmit->tail],
0455                &up->regs->w.xfifo[i]);
0456         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0457         up->port.icount.tx++;
0458         if (uart_circ_empty(xmit))
0459             break;
0460     }
0461 
0462     /* Issue a Transmit Frame command.  */
0463     sunsab_cec_wait(up);
0464     writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
0465 }
0466 
0467 /* port->lock is not held.  */
0468 static void sunsab_send_xchar(struct uart_port *port, char ch)
0469 {
0470     struct uart_sunsab_port *up =
0471         container_of(port, struct uart_sunsab_port, port);
0472     unsigned long flags;
0473 
0474     if (ch == __DISABLED_CHAR)
0475         return;
0476 
0477     spin_lock_irqsave(&up->port.lock, flags);
0478 
0479     sunsab_tec_wait(up);
0480     writeb(ch, &up->regs->w.tic);
0481 
0482     spin_unlock_irqrestore(&up->port.lock, flags);
0483 }
0484 
0485 /* port->lock held by caller.  */
0486 static void sunsab_stop_rx(struct uart_port *port)
0487 {
0488     struct uart_sunsab_port *up =
0489         container_of(port, struct uart_sunsab_port, port);
0490 
0491     up->interrupt_mask0 |= SAB82532_IMR0_TCD;
0492     writeb(up->interrupt_mask1, &up->regs->w.imr0);
0493 }
0494 
0495 /* port->lock is not held.  */
0496 static void sunsab_break_ctl(struct uart_port *port, int break_state)
0497 {
0498     struct uart_sunsab_port *up =
0499         container_of(port, struct uart_sunsab_port, port);
0500     unsigned long flags;
0501     unsigned char val;
0502 
0503     spin_lock_irqsave(&up->port.lock, flags);
0504 
0505     val = up->cached_dafo;
0506     if (break_state)
0507         val |= SAB82532_DAFO_XBRK;
0508     else
0509         val &= ~SAB82532_DAFO_XBRK;
0510     up->cached_dafo = val;
0511 
0512     set_bit(SAB82532_REGS_PENDING, &up->irqflags);
0513     if (test_bit(SAB82532_XPR, &up->irqflags))
0514         sunsab_tx_idle(up);
0515 
0516     spin_unlock_irqrestore(&up->port.lock, flags);
0517 }
0518 
0519 /* port->lock is not held.  */
0520 static int sunsab_startup(struct uart_port *port)
0521 {
0522     struct uart_sunsab_port *up =
0523         container_of(port, struct uart_sunsab_port, port);
0524     unsigned long flags;
0525     unsigned char tmp;
0526     int err = request_irq(up->port.irq, sunsab_interrupt,
0527                   IRQF_SHARED, "sab", up);
0528     if (err)
0529         return err;
0530 
0531     spin_lock_irqsave(&up->port.lock, flags);
0532 
0533     /*
0534      * Wait for any commands or immediate characters
0535      */
0536     sunsab_cec_wait(up);
0537     sunsab_tec_wait(up);
0538 
0539     /*
0540      * Clear the FIFO buffers.
0541      */
0542     writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
0543     sunsab_cec_wait(up);
0544     writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
0545 
0546     /*
0547      * Clear the interrupt registers.
0548      */
0549     (void) readb(&up->regs->r.isr0);
0550     (void) readb(&up->regs->r.isr1);
0551 
0552     /*
0553      * Now, initialize the UART 
0554      */
0555     writeb(0, &up->regs->w.ccr0);               /* power-down */
0556     writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
0557            SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
0558     writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
0559     writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
0560            SAB82532_CCR2_TOE, &up->regs->w.ccr2);
0561     writeb(0, &up->regs->w.ccr3);
0562     writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
0563     up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
0564                SAB82532_MODE_RAC);
0565     writeb(up->cached_mode, &up->regs->w.mode);
0566     writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
0567     
0568     tmp = readb(&up->regs->rw.ccr0);
0569     tmp |= SAB82532_CCR0_PU;    /* power-up */
0570     writeb(tmp, &up->regs->rw.ccr0);
0571 
0572     /*
0573      * Finally, enable interrupts
0574      */
0575     up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
0576                    SAB82532_IMR0_PLLA);
0577     writeb(up->interrupt_mask0, &up->regs->w.imr0);
0578     up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
0579                    SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
0580                    SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
0581                    SAB82532_IMR1_XPR);
0582     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0583     set_bit(SAB82532_ALLS, &up->irqflags);
0584     set_bit(SAB82532_XPR, &up->irqflags);
0585 
0586     spin_unlock_irqrestore(&up->port.lock, flags);
0587 
0588     return 0;
0589 }
0590 
0591 /* port->lock is not held.  */
0592 static void sunsab_shutdown(struct uart_port *port)
0593 {
0594     struct uart_sunsab_port *up =
0595         container_of(port, struct uart_sunsab_port, port);
0596     unsigned long flags;
0597 
0598     spin_lock_irqsave(&up->port.lock, flags);
0599 
0600     /* Disable Interrupts */
0601     up->interrupt_mask0 = 0xff;
0602     writeb(up->interrupt_mask0, &up->regs->w.imr0);
0603     up->interrupt_mask1 = 0xff;
0604     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0605 
0606     /* Disable break condition */
0607     up->cached_dafo = readb(&up->regs->rw.dafo);
0608     up->cached_dafo &= ~SAB82532_DAFO_XBRK;
0609     writeb(up->cached_dafo, &up->regs->rw.dafo);
0610 
0611     /* Disable Receiver */  
0612     up->cached_mode &= ~SAB82532_MODE_RAC;
0613     writeb(up->cached_mode, &up->regs->rw.mode);
0614 
0615     /*
0616      * XXX FIXME
0617      *
0618      * If the chip is powered down here the system hangs/crashes during
0619      * reboot or shutdown.  This needs to be investigated further,
0620      * similar behaviour occurs in 2.4 when the driver is configured
0621      * as a module only.  One hint may be that data is sometimes
0622      * transmitted at 9600 baud during shutdown (regardless of the
0623      * speed the chip was configured for when the port was open).
0624      */
0625 #if 0
0626     /* Power Down */    
0627     tmp = readb(&up->regs->rw.ccr0);
0628     tmp &= ~SAB82532_CCR0_PU;
0629     writeb(tmp, &up->regs->rw.ccr0);
0630 #endif
0631 
0632     spin_unlock_irqrestore(&up->port.lock, flags);
0633     free_irq(up->port.irq, up);
0634 }
0635 
0636 /*
0637  * This is used to figure out the divisor speeds.
0638  *
0639  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
0640  *
0641  * with               0 <= N < 64 and 0 <= M < 16
0642  */
0643 
0644 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
0645 {
0646     int n, m;
0647 
0648     if (baud == 0) {
0649         *n_ret = 0;
0650         *m_ret = 0;
0651         return;
0652     }
0653      
0654     /*
0655      * We scale numbers by 10 so that we get better accuracy
0656      * without having to use floating point.  Here we increment m
0657      * until n is within the valid range.
0658      */
0659     n = (SAB_BASE_BAUD * 10) / baud;
0660     m = 0;
0661     while (n >= 640) {
0662         n = n / 2;
0663         m++;
0664     }
0665     n = (n+5) / 10;
0666     /*
0667      * We try very hard to avoid speeds with M == 0 since they may
0668      * not work correctly for XTAL frequences above 10 MHz.
0669      */
0670     if ((m == 0) && ((n & 1) == 0)) {
0671         n = n / 2;
0672         m++;
0673     }
0674     *n_ret = n - 1;
0675     *m_ret = m;
0676 }
0677 
0678 /* Internal routine, port->lock is held and local interrupts are disabled.  */
0679 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
0680                   unsigned int iflag, unsigned int baud,
0681                   unsigned int quot)
0682 {
0683     unsigned char dafo;
0684     int bits, n, m;
0685 
0686     /* Byte size and parity */
0687     switch (cflag & CSIZE) {
0688           case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
0689           case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
0690           case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
0691           case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
0692           /* Never happens, but GCC is too dumb to figure it out */
0693           default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
0694     }
0695 
0696     if (cflag & CSTOPB) {
0697         dafo |= SAB82532_DAFO_STOP;
0698         bits++;
0699     }
0700 
0701     if (cflag & PARENB) {
0702         dafo |= SAB82532_DAFO_PARE;
0703         bits++;
0704     }
0705 
0706     if (cflag & PARODD) {
0707         dafo |= SAB82532_DAFO_PAR_ODD;
0708     } else {
0709         dafo |= SAB82532_DAFO_PAR_EVEN;
0710     }
0711     up->cached_dafo = dafo;
0712 
0713     calc_ebrg(baud, &n, &m);
0714 
0715     up->cached_ebrg = n | (m << 6);
0716 
0717     up->tec_timeout = (10 * 1000000) / baud;
0718     up->cec_timeout = up->tec_timeout >> 2;
0719 
0720     /* CTS flow control flags */
0721     /* We encode read_status_mask and ignore_status_mask like so:
0722      *
0723      * ---------------------
0724      * | ... | ISR1 | ISR0 |
0725      * ---------------------
0726      *  ..    15   8 7    0
0727      */
0728 
0729     up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
0730                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
0731                      SAB82532_ISR0_CDSC);
0732     up->port.read_status_mask |= (SAB82532_ISR1_CSC |
0733                       SAB82532_ISR1_ALLS |
0734                       SAB82532_ISR1_XPR) << 8;
0735     if (iflag & INPCK)
0736         up->port.read_status_mask |= (SAB82532_ISR0_PERR |
0737                           SAB82532_ISR0_FERR);
0738     if (iflag & (IGNBRK | BRKINT | PARMRK))
0739         up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
0740 
0741     /*
0742      * Characteres to ignore
0743      */
0744     up->port.ignore_status_mask = 0;
0745     if (iflag & IGNPAR)
0746         up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
0747                         SAB82532_ISR0_FERR);
0748     if (iflag & IGNBRK) {
0749         up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
0750         /*
0751          * If we're ignoring parity and break indicators,
0752          * ignore overruns too (for real raw support).
0753          */
0754         if (iflag & IGNPAR)
0755             up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
0756     }
0757 
0758     /*
0759      * ignore all characters if CREAD is not set
0760      */
0761     if ((cflag & CREAD) == 0)
0762         up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
0763                         SAB82532_ISR0_TCD);
0764 
0765     uart_update_timeout(&up->port, cflag,
0766                 (up->port.uartclk / (16 * quot)));
0767 
0768     /* Now schedule a register update when the chip's
0769      * transmitter is idle.
0770      */
0771     up->cached_mode |= SAB82532_MODE_RAC;
0772     set_bit(SAB82532_REGS_PENDING, &up->irqflags);
0773     if (test_bit(SAB82532_XPR, &up->irqflags))
0774         sunsab_tx_idle(up);
0775 }
0776 
0777 /* port->lock is not held.  */
0778 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
0779                    struct ktermios *old)
0780 {
0781     struct uart_sunsab_port *up =
0782         container_of(port, struct uart_sunsab_port, port);
0783     unsigned long flags;
0784     unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
0785     unsigned int quot = uart_get_divisor(port, baud);
0786 
0787     spin_lock_irqsave(&up->port.lock, flags);
0788     sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
0789     spin_unlock_irqrestore(&up->port.lock, flags);
0790 }
0791 
0792 static const char *sunsab_type(struct uart_port *port)
0793 {
0794     struct uart_sunsab_port *up = (void *)port;
0795     static char buf[36];
0796     
0797     sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
0798     return buf;
0799 }
0800 
0801 static void sunsab_release_port(struct uart_port *port)
0802 {
0803 }
0804 
0805 static int sunsab_request_port(struct uart_port *port)
0806 {
0807     return 0;
0808 }
0809 
0810 static void sunsab_config_port(struct uart_port *port, int flags)
0811 {
0812 }
0813 
0814 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
0815 {
0816     return -EINVAL;
0817 }
0818 
0819 static const struct uart_ops sunsab_pops = {
0820     .tx_empty   = sunsab_tx_empty,
0821     .set_mctrl  = sunsab_set_mctrl,
0822     .get_mctrl  = sunsab_get_mctrl,
0823     .stop_tx    = sunsab_stop_tx,
0824     .start_tx   = sunsab_start_tx,
0825     .send_xchar = sunsab_send_xchar,
0826     .stop_rx    = sunsab_stop_rx,
0827     .break_ctl  = sunsab_break_ctl,
0828     .startup    = sunsab_startup,
0829     .shutdown   = sunsab_shutdown,
0830     .set_termios    = sunsab_set_termios,
0831     .type       = sunsab_type,
0832     .release_port   = sunsab_release_port,
0833     .request_port   = sunsab_request_port,
0834     .config_port    = sunsab_config_port,
0835     .verify_port    = sunsab_verify_port,
0836 };
0837 
0838 static struct uart_driver sunsab_reg = {
0839     .owner          = THIS_MODULE,
0840     .driver_name        = "sunsab",
0841     .dev_name       = "ttyS",
0842     .major          = TTY_MAJOR,
0843 };
0844 
0845 static struct uart_sunsab_port *sunsab_ports;
0846 
0847 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
0848 
0849 static void sunsab_console_putchar(struct uart_port *port, unsigned char c)
0850 {
0851     struct uart_sunsab_port *up =
0852         container_of(port, struct uart_sunsab_port, port);
0853 
0854     sunsab_tec_wait(up);
0855     writeb(c, &up->regs->w.tic);
0856 }
0857 
0858 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
0859 {
0860     struct uart_sunsab_port *up = &sunsab_ports[con->index];
0861     unsigned long flags;
0862     int locked = 1;
0863 
0864     if (up->port.sysrq || oops_in_progress)
0865         locked = spin_trylock_irqsave(&up->port.lock, flags);
0866     else
0867         spin_lock_irqsave(&up->port.lock, flags);
0868 
0869     uart_console_write(&up->port, s, n, sunsab_console_putchar);
0870     sunsab_tec_wait(up);
0871 
0872     if (locked)
0873         spin_unlock_irqrestore(&up->port.lock, flags);
0874 }
0875 
0876 static int sunsab_console_setup(struct console *con, char *options)
0877 {
0878     struct uart_sunsab_port *up = &sunsab_ports[con->index];
0879     unsigned long flags;
0880     unsigned int baud, quot;
0881 
0882     /*
0883      * The console framework calls us for each and every port
0884      * registered. Defer the console setup until the requested
0885      * port has been properly discovered. A bit of a hack,
0886      * though...
0887      */
0888     if (up->port.type != PORT_SUNSAB)
0889         return -EINVAL;
0890 
0891     printk("Console: ttyS%d (SAB82532)\n",
0892            (sunsab_reg.minor - 64) + con->index);
0893 
0894     sunserial_console_termios(con, up->port.dev->of_node);
0895 
0896     switch (con->cflag & CBAUD) {
0897     case B150: baud = 150; break;
0898     case B300: baud = 300; break;
0899     case B600: baud = 600; break;
0900     case B1200: baud = 1200; break;
0901     case B2400: baud = 2400; break;
0902     case B4800: baud = 4800; break;
0903     default: case B9600: baud = 9600; break;
0904     case B19200: baud = 19200; break;
0905     case B38400: baud = 38400; break;
0906     case B57600: baud = 57600; break;
0907     case B115200: baud = 115200; break;
0908     case B230400: baud = 230400; break;
0909     case B460800: baud = 460800; break;
0910     }
0911 
0912     /*
0913      * Temporary fix.
0914      */
0915     spin_lock_init(&up->port.lock);
0916 
0917     /*
0918      * Initialize the hardware
0919      */
0920     sunsab_startup(&up->port);
0921 
0922     spin_lock_irqsave(&up->port.lock, flags);
0923 
0924     /*
0925      * Finally, enable interrupts
0926      */
0927     up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
0928                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
0929     writeb(up->interrupt_mask0, &up->regs->w.imr0);
0930     up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
0931                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
0932                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
0933                 SAB82532_IMR1_XPR;
0934     writeb(up->interrupt_mask1, &up->regs->w.imr1);
0935 
0936     quot = uart_get_divisor(&up->port, baud);
0937     sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
0938     sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
0939 
0940     spin_unlock_irqrestore(&up->port.lock, flags);
0941     
0942     return 0;
0943 }
0944 
0945 static struct console sunsab_console = {
0946     .name   =   "ttyS",
0947     .write  =   sunsab_console_write,
0948     .device =   uart_console_device,
0949     .setup  =   sunsab_console_setup,
0950     .flags  =   CON_PRINTBUFFER,
0951     .index  =   -1,
0952     .data   =   &sunsab_reg,
0953 };
0954 
0955 static inline struct console *SUNSAB_CONSOLE(void)
0956 {
0957     return &sunsab_console;
0958 }
0959 #else
0960 #define SUNSAB_CONSOLE()    (NULL)
0961 #define sunsab_console_init()   do { } while (0)
0962 #endif
0963 
0964 static int sunsab_init_one(struct uart_sunsab_port *up,
0965                      struct platform_device *op,
0966                      unsigned long offset,
0967                      int line)
0968 {
0969     up->port.line = line;
0970     up->port.dev = &op->dev;
0971 
0972     up->port.mapbase = op->resource[0].start + offset;
0973     up->port.membase = of_ioremap(&op->resource[0], offset,
0974                       sizeof(union sab82532_async_regs),
0975                       "sab");
0976     if (!up->port.membase)
0977         return -ENOMEM;
0978     up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
0979 
0980     up->port.irq = op->archdata.irqs[0];
0981 
0982     up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
0983     up->port.iotype = UPIO_MEM;
0984     up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
0985 
0986     writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
0987 
0988     up->port.ops = &sunsab_pops;
0989     up->port.type = PORT_SUNSAB;
0990     up->port.uartclk = SAB_BASE_BAUD;
0991 
0992     up->type = readb(&up->regs->r.vstr) & 0x0f;
0993     writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
0994     writeb(0xff, &up->regs->w.pim);
0995     if ((up->port.line & 0x1) == 0) {
0996         up->pvr_dsr_bit = (1 << 0);
0997         up->pvr_dtr_bit = (1 << 1);
0998         up->gis_shift = 2;
0999     } else {
1000         up->pvr_dsr_bit = (1 << 3);
1001         up->pvr_dtr_bit = (1 << 2);
1002         up->gis_shift = 0;
1003     }
1004     up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1005     writeb(up->cached_pvr, &up->regs->w.pvr);
1006     up->cached_mode = readb(&up->regs->rw.mode);
1007     up->cached_mode |= SAB82532_MODE_FRTS;
1008     writeb(up->cached_mode, &up->regs->rw.mode);
1009     up->cached_mode |= SAB82532_MODE_RTS;
1010     writeb(up->cached_mode, &up->regs->rw.mode);
1011 
1012     up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1013     up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1014 
1015     return 0;
1016 }
1017 
1018 static int sab_probe(struct platform_device *op)
1019 {
1020     static int inst;
1021     struct uart_sunsab_port *up;
1022     int err;
1023 
1024     up = &sunsab_ports[inst * 2];
1025 
1026     err = sunsab_init_one(&up[0], op,
1027                   0,
1028                   (inst * 2) + 0);
1029     if (err)
1030         goto out;
1031 
1032     err = sunsab_init_one(&up[1], op,
1033                   sizeof(union sab82532_async_regs),
1034                   (inst * 2) + 1);
1035     if (err)
1036         goto out1;
1037 
1038     sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1039                 &sunsab_reg, up[0].port.line,
1040                 false);
1041 
1042     sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1043                 &sunsab_reg, up[1].port.line,
1044                 false);
1045 
1046     err = uart_add_one_port(&sunsab_reg, &up[0].port);
1047     if (err)
1048         goto out2;
1049 
1050     err = uart_add_one_port(&sunsab_reg, &up[1].port);
1051     if (err)
1052         goto out3;
1053 
1054     platform_set_drvdata(op, &up[0]);
1055 
1056     inst++;
1057 
1058     return 0;
1059 
1060 out3:
1061     uart_remove_one_port(&sunsab_reg, &up[0].port);
1062 out2:
1063     of_iounmap(&op->resource[0],
1064            up[1].port.membase,
1065            sizeof(union sab82532_async_regs));
1066 out1:
1067     of_iounmap(&op->resource[0],
1068            up[0].port.membase,
1069            sizeof(union sab82532_async_regs));
1070 out:
1071     return err;
1072 }
1073 
1074 static int sab_remove(struct platform_device *op)
1075 {
1076     struct uart_sunsab_port *up = platform_get_drvdata(op);
1077 
1078     uart_remove_one_port(&sunsab_reg, &up[1].port);
1079     uart_remove_one_port(&sunsab_reg, &up[0].port);
1080     of_iounmap(&op->resource[0],
1081            up[1].port.membase,
1082            sizeof(union sab82532_async_regs));
1083     of_iounmap(&op->resource[0],
1084            up[0].port.membase,
1085            sizeof(union sab82532_async_regs));
1086 
1087     return 0;
1088 }
1089 
1090 static const struct of_device_id sab_match[] = {
1091     {
1092         .name = "se",
1093     },
1094     {
1095         .name = "serial",
1096         .compatible = "sab82532",
1097     },
1098     {},
1099 };
1100 MODULE_DEVICE_TABLE(of, sab_match);
1101 
1102 static struct platform_driver sab_driver = {
1103     .driver = {
1104         .name = "sab",
1105         .of_match_table = sab_match,
1106     },
1107     .probe      = sab_probe,
1108     .remove     = sab_remove,
1109 };
1110 
1111 static int __init sunsab_init(void)
1112 {
1113     struct device_node *dp;
1114     int err;
1115     int num_channels = 0;
1116 
1117     for_each_node_by_name(dp, "se")
1118         num_channels += 2;
1119     for_each_node_by_name(dp, "serial") {
1120         if (of_device_is_compatible(dp, "sab82532"))
1121             num_channels += 2;
1122     }
1123 
1124     if (num_channels) {
1125         sunsab_ports = kcalloc(num_channels,
1126                        sizeof(struct uart_sunsab_port),
1127                        GFP_KERNEL);
1128         if (!sunsab_ports)
1129             return -ENOMEM;
1130 
1131         err = sunserial_register_minors(&sunsab_reg, num_channels);
1132         if (err) {
1133             kfree(sunsab_ports);
1134             sunsab_ports = NULL;
1135 
1136             return err;
1137         }
1138     }
1139 
1140     return platform_driver_register(&sab_driver);
1141 }
1142 
1143 static void __exit sunsab_exit(void)
1144 {
1145     platform_driver_unregister(&sab_driver);
1146     if (sunsab_reg.nr) {
1147         sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1148     }
1149 
1150     kfree(sunsab_ports);
1151     sunsab_ports = NULL;
1152 }
1153 
1154 module_init(sunsab_init);
1155 module_exit(sunsab_exit);
1156 
1157 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1158 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1159 MODULE_LICENSE("GPL");
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