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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Sunplus SoC UART driver
0004  *
0005  * Author: Hammer Hsieh <hammerh0314@gmail.com>
0006  *
0007  * Note1: This driver is 8250-like uart, but are not register compatible.
0008  *
0009  * Note2: On some buses, for preventing data incoherence, must do a read
0010  * for ensure write made it to hardware. In this driver, function startup
0011  * and shutdown did not do a read but only do a write directly. For what?
0012  * In Sunplus bus communication between memory bus and peripheral bus with
0013  * posted write, it will send a specific command after last write command
0014  * to make sure write done. Then memory bus identify the specific command
0015  * and send done signal back to master device. After master device received
0016  * done signal, then proceed next write command. It is no need to do a read
0017  * before write.
0018  */
0019 #include <linux/clk.h>
0020 #include <linux/console.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/io.h>
0023 #include <linux/iopoll.h>
0024 #include <linux/module.h>
0025 #include <linux/of.h>
0026 #include <linux/of_platform.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/reset.h>
0029 #include <linux/serial_core.h>
0030 #include <linux/serial_reg.h>
0031 #include <linux/sysrq.h>
0032 #include <linux/tty.h>
0033 #include <linux/tty_flip.h>
0034 #include <asm/irq.h>
0035 
0036 /* Register offsets */
0037 #define SUP_UART_DATA           0x00
0038 #define SUP_UART_LSR            0x04
0039 #define SUP_UART_MSR            0x08
0040 #define SUP_UART_LCR            0x0C
0041 #define SUP_UART_MCR            0x10
0042 #define SUP_UART_DIV_L          0x14
0043 #define SUP_UART_DIV_H          0x18
0044 #define SUP_UART_ISC            0x1C
0045 #define SUP_UART_TX_RESIDUE     0x20
0046 #define SUP_UART_RX_RESIDUE     0x24
0047 
0048 /* Line Status Register bits */
0049 #define SUP_UART_LSR_BC         BIT(5) /* break condition status */
0050 #define SUP_UART_LSR_FE         BIT(4) /* frame error status */
0051 #define SUP_UART_LSR_OE         BIT(3) /* overrun error status */
0052 #define SUP_UART_LSR_PE         BIT(2) /* parity error status */
0053 #define SUP_UART_LSR_RX         BIT(1) /* 1: receive fifo not empty */
0054 #define SUP_UART_LSR_TX         BIT(0) /* 1: transmit fifo is not full */
0055 #define SUP_UART_LSR_TX_NOT_FULL    1
0056 #define SUP_UART_LSR_BRK_ERROR_BITS GENMASK(5, 2)
0057 
0058 /* Line Control Register bits */
0059 #define SUP_UART_LCR_SBC        BIT(5) /* select break condition */
0060 
0061 /* Modem Control Register bits */
0062 #define SUP_UART_MCR_RI         BIT(3) /* ring indicator */
0063 #define SUP_UART_MCR_DCD        BIT(2) /* data carrier detect */
0064 
0065 /* Interrupt Status/Control Register bits */
0066 #define SUP_UART_ISC_RXM        BIT(5) /* RX interrupt enable */
0067 #define SUP_UART_ISC_TXM        BIT(4) /* TX interrupt enable */
0068 #define SUP_UART_ISC_RX         BIT(1) /* RX interrupt status */
0069 #define SUP_UART_ISC_TX         BIT(0) /* TX interrupt status */
0070 
0071 #define SUP_DUMMY_READ          BIT(16) /* drop bytes received on a !CREAD port */
0072 #define SUP_UART_NR         5
0073 
0074 struct sunplus_uart_port {
0075     struct uart_port port;
0076     struct clk *clk;
0077     struct reset_control *rstc;
0078 };
0079 
0080 static void sp_uart_put_char(struct uart_port *port, unsigned int ch)
0081 {
0082     writel(ch, port->membase + SUP_UART_DATA);
0083 }
0084 
0085 static u32 sunplus_tx_buf_not_full(struct uart_port *port)
0086 {
0087     unsigned int lsr = readl(port->membase + SUP_UART_LSR);
0088 
0089     return (lsr & SUP_UART_LSR_TX) ? SUP_UART_LSR_TX_NOT_FULL : 0;
0090 }
0091 
0092 static unsigned int sunplus_tx_empty(struct uart_port *port)
0093 {
0094     unsigned int lsr = readl(port->membase + SUP_UART_LSR);
0095 
0096     return (lsr & UART_LSR_TEMT) ? TIOCSER_TEMT : 0;
0097 }
0098 
0099 static void sunplus_set_mctrl(struct uart_port *port, unsigned int mctrl)
0100 {
0101     unsigned int mcr = readl(port->membase + SUP_UART_MCR);
0102 
0103     if (mctrl & TIOCM_DTR)
0104         mcr |= UART_MCR_DTR;
0105     else
0106         mcr &= ~UART_MCR_DTR;
0107 
0108     if (mctrl & TIOCM_RTS)
0109         mcr |= UART_MCR_RTS;
0110     else
0111         mcr &= ~UART_MCR_RTS;
0112 
0113     if (mctrl & TIOCM_CAR)
0114         mcr |= SUP_UART_MCR_DCD;
0115     else
0116         mcr &= ~SUP_UART_MCR_DCD;
0117 
0118     if (mctrl & TIOCM_RI)
0119         mcr |= SUP_UART_MCR_RI;
0120     else
0121         mcr &= ~SUP_UART_MCR_RI;
0122 
0123     if (mctrl & TIOCM_LOOP)
0124         mcr |= UART_MCR_LOOP;
0125     else
0126         mcr &= ~UART_MCR_LOOP;
0127 
0128     writel(mcr, port->membase + SUP_UART_MCR);
0129 }
0130 
0131 static unsigned int sunplus_get_mctrl(struct uart_port *port)
0132 {
0133     unsigned int mcr, ret = 0;
0134 
0135     mcr = readl(port->membase + SUP_UART_MCR);
0136 
0137     if (mcr & UART_MCR_DTR)
0138         ret |= TIOCM_DTR;
0139 
0140     if (mcr & UART_MCR_RTS)
0141         ret |= TIOCM_RTS;
0142 
0143     if (mcr & SUP_UART_MCR_DCD)
0144         ret |= TIOCM_CAR;
0145 
0146     if (mcr & SUP_UART_MCR_RI)
0147         ret |= TIOCM_RI;
0148 
0149     if (mcr & UART_MCR_LOOP)
0150         ret |= TIOCM_LOOP;
0151 
0152     return ret;
0153 }
0154 
0155 static void sunplus_stop_tx(struct uart_port *port)
0156 {
0157     unsigned int isc;
0158 
0159     isc = readl(port->membase + SUP_UART_ISC);
0160     isc &= ~SUP_UART_ISC_TXM;
0161     writel(isc, port->membase + SUP_UART_ISC);
0162 }
0163 
0164 static void sunplus_start_tx(struct uart_port *port)
0165 {
0166     unsigned int isc;
0167 
0168     isc = readl(port->membase + SUP_UART_ISC);
0169     isc |= SUP_UART_ISC_TXM;
0170     writel(isc, port->membase + SUP_UART_ISC);
0171 }
0172 
0173 static void sunplus_stop_rx(struct uart_port *port)
0174 {
0175     unsigned int isc;
0176 
0177     isc = readl(port->membase + SUP_UART_ISC);
0178     isc &= ~SUP_UART_ISC_RXM;
0179     writel(isc, port->membase + SUP_UART_ISC);
0180 }
0181 
0182 static void sunplus_break_ctl(struct uart_port *port, int ctl)
0183 {
0184     unsigned long flags;
0185     unsigned int lcr;
0186 
0187     spin_lock_irqsave(&port->lock, flags);
0188 
0189     lcr = readl(port->membase + SUP_UART_LCR);
0190 
0191     if (ctl)
0192         lcr |= SUP_UART_LCR_SBC; /* start break */
0193     else
0194         lcr &= ~SUP_UART_LCR_SBC; /* stop break */
0195 
0196     writel(lcr, port->membase + SUP_UART_LCR);
0197 
0198     spin_unlock_irqrestore(&port->lock, flags);
0199 }
0200 
0201 static void transmit_chars(struct uart_port *port)
0202 {
0203     struct circ_buf *xmit = &port->state->xmit;
0204 
0205     if (port->x_char) {
0206         sp_uart_put_char(port, port->x_char);
0207         port->icount.tx++;
0208         port->x_char = 0;
0209         return;
0210     }
0211 
0212     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0213         sunplus_stop_tx(port);
0214         return;
0215     }
0216 
0217     do {
0218         sp_uart_put_char(port, xmit->buf[xmit->tail]);
0219         xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
0220         port->icount.tx++;
0221 
0222         if (uart_circ_empty(xmit))
0223             break;
0224     } while (sunplus_tx_buf_not_full(port));
0225 
0226     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0227         uart_write_wakeup(port);
0228 
0229     if (uart_circ_empty(xmit))
0230         sunplus_stop_tx(port);
0231 }
0232 
0233 static void receive_chars(struct uart_port *port)
0234 {
0235     unsigned int lsr = readl(port->membase + SUP_UART_LSR);
0236     unsigned int ch, flag;
0237 
0238     do {
0239         ch = readl(port->membase + SUP_UART_DATA);
0240         flag = TTY_NORMAL;
0241         port->icount.rx++;
0242 
0243         if (unlikely(lsr & SUP_UART_LSR_BRK_ERROR_BITS)) {
0244             if (lsr & SUP_UART_LSR_BC) {
0245                 lsr &= ~(SUP_UART_LSR_FE | SUP_UART_LSR_PE);
0246                 port->icount.brk++;
0247                 flag = TTY_BREAK;
0248                 if (uart_handle_break(port))
0249                     goto ignore_char;
0250             } else if (lsr & SUP_UART_LSR_PE) {
0251                 port->icount.parity++;
0252                 flag = TTY_PARITY;
0253             } else if (lsr & SUP_UART_LSR_FE) {
0254                 port->icount.frame++;
0255                 flag = TTY_FRAME;
0256             }
0257 
0258             if (lsr & SUP_UART_LSR_OE)
0259                 port->icount.overrun++;
0260         }
0261 
0262         if (port->ignore_status_mask & SUP_DUMMY_READ)
0263             goto ignore_char;
0264 
0265         if (uart_handle_sysrq_char(port, ch))
0266             goto ignore_char;
0267 
0268         uart_insert_char(port, lsr, SUP_UART_LSR_OE, ch, flag);
0269 
0270 ignore_char:
0271         lsr = readl(port->membase + SUP_UART_LSR);
0272     } while (lsr & SUP_UART_LSR_RX);
0273 
0274     tty_flip_buffer_push(&port->state->port);
0275 }
0276 
0277 static irqreturn_t sunplus_uart_irq(int irq, void *args)
0278 {
0279     struct uart_port *port = args;
0280     unsigned int isc;
0281 
0282     spin_lock(&port->lock);
0283 
0284     isc = readl(port->membase + SUP_UART_ISC);
0285 
0286     if (isc & SUP_UART_ISC_RX)
0287         receive_chars(port);
0288 
0289     if (isc & SUP_UART_ISC_TX)
0290         transmit_chars(port);
0291 
0292     spin_unlock(&port->lock);
0293 
0294     return IRQ_HANDLED;
0295 }
0296 
0297 static int sunplus_startup(struct uart_port *port)
0298 {
0299     unsigned long flags;
0300     unsigned int isc = 0;
0301     int ret;
0302 
0303     ret = request_irq(port->irq, sunplus_uart_irq, 0, "sunplus_uart", port);
0304     if (ret)
0305         return ret;
0306 
0307     spin_lock_irqsave(&port->lock, flags);
0308     /* isc define Bit[7:4] int setting, Bit[3:0] int status
0309      * isc register will clean Bit[3:0] int status after read
0310      * only do a write to Bit[7:4] int setting
0311      */
0312     isc |= SUP_UART_ISC_RXM;
0313     writel(isc, port->membase + SUP_UART_ISC);
0314     spin_unlock_irqrestore(&port->lock, flags);
0315 
0316     return 0;
0317 }
0318 
0319 static void sunplus_shutdown(struct uart_port *port)
0320 {
0321     unsigned long flags;
0322 
0323     spin_lock_irqsave(&port->lock, flags);
0324     /* isc define Bit[7:4] int setting, Bit[3:0] int status
0325      * isc register will clean Bit[3:0] int status after read
0326      * only do a write to Bit[7:4] int setting
0327      */
0328     writel(0, port->membase + SUP_UART_ISC); /* disable all interrupt */
0329     spin_unlock_irqrestore(&port->lock, flags);
0330 
0331     free_irq(port->irq, port);
0332 }
0333 
0334 static void sunplus_set_termios(struct uart_port *port,
0335                 struct ktermios *termios,
0336                 struct ktermios *oldtermios)
0337 {
0338     u32 ext, div, div_l, div_h, baud, lcr;
0339     u32 clk = port->uartclk;
0340     unsigned long flags;
0341 
0342     baud = uart_get_baud_rate(port, termios, oldtermios, 0, port->uartclk / 16);
0343 
0344     /* baud rate = uartclk / ((16 * divisor + 1) + divisor_ext) */
0345     clk += baud >> 1;
0346     div = clk / baud;
0347     ext = div & 0x0F;
0348     div = (div >> 4) - 1;
0349     div_l = (div & 0xFF) | (ext << 12);
0350     div_h = div >> 8;
0351 
0352     switch (termios->c_cflag & CSIZE) {
0353     case CS5:
0354         lcr = UART_LCR_WLEN5;
0355         break;
0356     case CS6:
0357         lcr = UART_LCR_WLEN6;
0358         break;
0359     case CS7:
0360         lcr = UART_LCR_WLEN7;
0361         break;
0362     default:
0363         lcr = UART_LCR_WLEN8;
0364         break;
0365     }
0366 
0367     if (termios->c_cflag & CSTOPB)
0368         lcr |= UART_LCR_STOP;
0369 
0370     if (termios->c_cflag & PARENB) {
0371         lcr |= UART_LCR_PARITY;
0372 
0373         if (!(termios->c_cflag & PARODD))
0374             lcr |= UART_LCR_EPAR;
0375     }
0376 
0377     spin_lock_irqsave(&port->lock, flags);
0378 
0379     uart_update_timeout(port, termios->c_cflag, baud);
0380 
0381     port->read_status_mask = 0;
0382     if (termios->c_iflag & INPCK)
0383         port->read_status_mask |= SUP_UART_LSR_PE | SUP_UART_LSR_FE;
0384 
0385     if (termios->c_iflag & (BRKINT | PARMRK))
0386         port->read_status_mask |= SUP_UART_LSR_BC;
0387 
0388     /* Characters to ignore */
0389     port->ignore_status_mask = 0;
0390     if (termios->c_iflag & IGNPAR)
0391         port->ignore_status_mask |= SUP_UART_LSR_FE | SUP_UART_LSR_PE;
0392 
0393     if (termios->c_iflag & IGNBRK) {
0394         port->ignore_status_mask |= SUP_UART_LSR_BC;
0395 
0396         if (termios->c_iflag & IGNPAR)
0397             port->ignore_status_mask |= SUP_UART_LSR_OE;
0398     }
0399 
0400     /* Ignore all characters if CREAD is not set */
0401     if ((termios->c_cflag & CREAD) == 0) {
0402         port->ignore_status_mask |= SUP_DUMMY_READ;
0403         /* flush rx data FIFO */
0404         writel(0, port->membase + SUP_UART_RX_RESIDUE);
0405     }
0406 
0407     /* Settings for baud rate divisor and lcr */
0408     writel(div_h, port->membase + SUP_UART_DIV_H);
0409     writel(div_l, port->membase + SUP_UART_DIV_L);
0410     writel(lcr, port->membase + SUP_UART_LCR);
0411 
0412     spin_unlock_irqrestore(&port->lock, flags);
0413 }
0414 
0415 static void sunplus_set_ldisc(struct uart_port *port, struct ktermios *termios)
0416 {
0417     int new = termios->c_line;
0418 
0419     if (new == N_PPS)
0420         port->flags |= UPF_HARDPPS_CD;
0421     else
0422         port->flags &= ~UPF_HARDPPS_CD;
0423 }
0424 
0425 static const char *sunplus_type(struct uart_port *port)
0426 {
0427     return port->type == PORT_SUNPLUS ? "sunplus_uart" : NULL;
0428 }
0429 
0430 static void sunplus_config_port(struct uart_port *port, int type)
0431 {
0432     if (type & UART_CONFIG_TYPE)
0433         port->type = PORT_SUNPLUS;
0434 }
0435 
0436 static int sunplus_verify_port(struct uart_port *port, struct serial_struct *ser)
0437 {
0438     if (ser->type != PORT_UNKNOWN && ser->type != PORT_SUNPLUS)
0439         return -EINVAL;
0440 
0441     return 0;
0442 }
0443 
0444 #if defined(CONFIG_SERIAL_SUNPLUS_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
0445 static void wait_for_xmitr(struct uart_port *port)
0446 {
0447     unsigned int val;
0448     int ret;
0449 
0450     /* Wait while FIFO is full or timeout */
0451     ret = readl_poll_timeout_atomic(port->membase + SUP_UART_LSR, val,
0452                     (val & SUP_UART_LSR_TX), 1, 10000);
0453 
0454     if (ret == -ETIMEDOUT) {
0455         dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
0456         return;
0457     }
0458 }
0459 #endif
0460 
0461 #ifdef CONFIG_CONSOLE_POLL
0462 static void sunplus_poll_put_char(struct uart_port *port, unsigned char data)
0463 {
0464     wait_for_xmitr(port);
0465     sp_uart_put_char(port, data);
0466 }
0467 
0468 static int sunplus_poll_get_char(struct uart_port *port)
0469 {
0470     unsigned int lsr = readl(port->membase + SUP_UART_LSR);
0471 
0472     if (!(lsr & SUP_UART_LSR_RX))
0473         return NO_POLL_CHAR;
0474 
0475     return readl(port->membase + SUP_UART_DATA);
0476 }
0477 #endif
0478 
0479 static const struct uart_ops sunplus_uart_ops = {
0480     .tx_empty   = sunplus_tx_empty,
0481     .set_mctrl  = sunplus_set_mctrl,
0482     .get_mctrl  = sunplus_get_mctrl,
0483     .stop_tx    = sunplus_stop_tx,
0484     .start_tx   = sunplus_start_tx,
0485     .stop_rx    = sunplus_stop_rx,
0486     .break_ctl  = sunplus_break_ctl,
0487     .startup    = sunplus_startup,
0488     .shutdown   = sunplus_shutdown,
0489     .set_termios    = sunplus_set_termios,
0490     .set_ldisc  = sunplus_set_ldisc,
0491     .type       = sunplus_type,
0492     .config_port    = sunplus_config_port,
0493     .verify_port    = sunplus_verify_port,
0494 #ifdef CONFIG_CONSOLE_POLL
0495     .poll_put_char  = sunplus_poll_put_char,
0496     .poll_get_char  = sunplus_poll_get_char,
0497 #endif
0498 };
0499 
0500 #ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
0501 static struct sunplus_uart_port *sunplus_console_ports[SUP_UART_NR];
0502 
0503 static void sunplus_uart_console_putchar(struct uart_port *port,
0504                      unsigned char ch)
0505 {
0506     wait_for_xmitr(port);
0507     sp_uart_put_char(port, ch);
0508 }
0509 
0510 static void sunplus_console_write(struct console *co,
0511                   const char *s,
0512                   unsigned int count)
0513 {
0514     unsigned long flags;
0515     int locked = 1;
0516 
0517     local_irq_save(flags);
0518 
0519     if (sunplus_console_ports[co->index]->port.sysrq)
0520         locked = 0;
0521     else if (oops_in_progress)
0522         locked = spin_trylock(&sunplus_console_ports[co->index]->port.lock);
0523     else
0524         spin_lock(&sunplus_console_ports[co->index]->port.lock);
0525 
0526     uart_console_write(&sunplus_console_ports[co->index]->port, s, count,
0527                sunplus_uart_console_putchar);
0528 
0529     if (locked)
0530         spin_unlock(&sunplus_console_ports[co->index]->port.lock);
0531 
0532     local_irq_restore(flags);
0533 }
0534 
0535 static int __init sunplus_console_setup(struct console *co, char *options)
0536 {
0537     struct sunplus_uart_port *sup;
0538     int baud = 115200;
0539     int bits = 8;
0540     int parity = 'n';
0541     int flow = 'n';
0542 
0543     if (co->index < 0 || co->index >= SUP_UART_NR)
0544         return -EINVAL;
0545 
0546     sup = sunplus_console_ports[co->index];
0547     if (!sup)
0548         return -ENODEV;
0549 
0550     if (options)
0551         uart_parse_options(options, &baud, &parity, &bits, &flow);
0552 
0553     return uart_set_options(&sup->port, co, baud, parity, bits, flow);
0554 }
0555 
0556 static struct uart_driver sunplus_uart_driver;
0557 static struct console sunplus_uart_console = {
0558     .name       = "ttySUP",
0559     .write      = sunplus_console_write,
0560     .device     = uart_console_device,
0561     .setup      = sunplus_console_setup,
0562     .flags      = CON_PRINTBUFFER,
0563     .index      = -1,
0564     .data       = &sunplus_uart_driver
0565 };
0566 
0567 #define SERIAL_SUNPLUS_CONSOLE  (&sunplus_uart_console)
0568 #else
0569 #define SERIAL_SUNPLUS_CONSOLE  NULL
0570 #endif
0571 
0572 static struct uart_driver sunplus_uart_driver = {
0573     .owner      = THIS_MODULE,
0574     .driver_name    = "sunplus_uart",
0575     .dev_name   = "ttySUP",
0576     .major      = TTY_MAJOR,
0577     .minor      = 64,
0578     .nr     = SUP_UART_NR,
0579     .cons       = SERIAL_SUNPLUS_CONSOLE,
0580 };
0581 
0582 static void sunplus_uart_disable_unprepare(void *data)
0583 {
0584     clk_disable_unprepare(data);
0585 }
0586 
0587 static void sunplus_uart_reset_control_assert(void *data)
0588 {
0589     reset_control_assert(data);
0590 }
0591 
0592 static int sunplus_uart_probe(struct platform_device *pdev)
0593 {
0594     struct sunplus_uart_port *sup;
0595     struct uart_port *port;
0596     struct resource *res;
0597     int ret, irq;
0598 
0599     pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
0600 
0601     if (pdev->id < 0 || pdev->id >= SUP_UART_NR)
0602         return -EINVAL;
0603 
0604     sup = devm_kzalloc(&pdev->dev, sizeof(*sup), GFP_KERNEL);
0605     if (!sup)
0606         return -ENOMEM;
0607 
0608     sup->clk = devm_clk_get_optional(&pdev->dev, NULL);
0609     if (IS_ERR(sup->clk))
0610         return dev_err_probe(&pdev->dev, PTR_ERR(sup->clk), "clk not found\n");
0611 
0612     ret = clk_prepare_enable(sup->clk);
0613     if (ret)
0614         return ret;
0615 
0616     ret = devm_add_action_or_reset(&pdev->dev, sunplus_uart_disable_unprepare, sup->clk);
0617     if (ret)
0618         return ret;
0619 
0620     sup->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0621     if (IS_ERR(sup->rstc))
0622         return dev_err_probe(&pdev->dev, PTR_ERR(sup->rstc), "rstc not found\n");
0623 
0624     port = &sup->port;
0625 
0626     port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0627     if (IS_ERR(port->membase))
0628         return dev_err_probe(&pdev->dev, PTR_ERR(port->membase), "membase not found\n");
0629 
0630     irq = platform_get_irq(pdev, 0);
0631     if (irq < 0)
0632         return irq;
0633 
0634     port->mapbase = res->start;
0635     port->uartclk = clk_get_rate(sup->clk);
0636     port->line = pdev->id;
0637     port->irq = irq;
0638     port->dev = &pdev->dev;
0639     port->iotype = UPIO_MEM;
0640     port->ops = &sunplus_uart_ops;
0641     port->flags = UPF_BOOT_AUTOCONF;
0642     port->fifosize = 128;
0643 
0644     ret = reset_control_deassert(sup->rstc);
0645     if (ret)
0646         return ret;
0647 
0648     ret = devm_add_action_or_reset(&pdev->dev, sunplus_uart_reset_control_assert, sup->rstc);
0649     if (ret)
0650         return ret;
0651 
0652 #ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
0653     sunplus_console_ports[sup->port.line] = sup;
0654 #endif
0655 
0656     platform_set_drvdata(pdev, &sup->port);
0657 
0658     ret = uart_add_one_port(&sunplus_uart_driver, &sup->port);
0659 #ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
0660     if (ret)
0661         sunplus_console_ports[sup->port.line] = NULL;
0662 #endif
0663 
0664     return ret;
0665 }
0666 
0667 static int sunplus_uart_remove(struct platform_device *pdev)
0668 {
0669     struct sunplus_uart_port *sup = platform_get_drvdata(pdev);
0670 
0671     uart_remove_one_port(&sunplus_uart_driver, &sup->port);
0672 
0673     return 0;
0674 }
0675 
0676 static int __maybe_unused sunplus_uart_suspend(struct device *dev)
0677 {
0678     struct sunplus_uart_port *sup = dev_get_drvdata(dev);
0679 
0680     if (!uart_console(&sup->port))
0681         uart_suspend_port(&sunplus_uart_driver, &sup->port);
0682 
0683     return 0;
0684 }
0685 
0686 static int __maybe_unused sunplus_uart_resume(struct device *dev)
0687 {
0688     struct sunplus_uart_port *sup = dev_get_drvdata(dev);
0689 
0690     if (!uart_console(&sup->port))
0691         uart_resume_port(&sunplus_uart_driver, &sup->port);
0692 
0693     return 0;
0694 }
0695 
0696 static const struct dev_pm_ops sunplus_uart_pm_ops = {
0697     SET_SYSTEM_SLEEP_PM_OPS(sunplus_uart_suspend, sunplus_uart_resume)
0698 };
0699 
0700 static const struct of_device_id sp_uart_of_match[] = {
0701     { .compatible = "sunplus,sp7021-uart" },
0702     {}
0703 };
0704 MODULE_DEVICE_TABLE(of, sp_uart_of_match);
0705 
0706 static struct platform_driver sunplus_uart_platform_driver = {
0707     .probe      = sunplus_uart_probe,
0708     .remove     = sunplus_uart_remove,
0709     .driver = {
0710         .name   = "sunplus_uart",
0711         .of_match_table = sp_uart_of_match,
0712         .pm     = &sunplus_uart_pm_ops,
0713     }
0714 };
0715 
0716 static int __init sunplus_uart_init(void)
0717 {
0718     int ret;
0719 
0720     ret = uart_register_driver(&sunplus_uart_driver);
0721     if (ret)
0722         return ret;
0723 
0724     ret = platform_driver_register(&sunplus_uart_platform_driver);
0725     if (ret)
0726         uart_unregister_driver(&sunplus_uart_driver);
0727 
0728     return ret;
0729 }
0730 module_init(sunplus_uart_init);
0731 
0732 static void __exit sunplus_uart_exit(void)
0733 {
0734     platform_driver_unregister(&sunplus_uart_platform_driver);
0735     uart_unregister_driver(&sunplus_uart_driver);
0736 }
0737 module_exit(sunplus_uart_exit);
0738 
0739 #ifdef CONFIG_SERIAL_EARLYCON
0740 static void sunplus_uart_putc(struct uart_port *port, unsigned char c)
0741 {
0742     unsigned int val;
0743     int ret;
0744 
0745     ret = readl_poll_timeout_atomic(port->membase + SUP_UART_LSR, val,
0746                     (val & UART_LSR_TEMT), 1, 10000);
0747     if (ret)
0748         return;
0749 
0750     writel(c, port->membase + SUP_UART_DATA);
0751 }
0752 
0753 static void sunplus_uart_early_write(struct console *con, const char *s, unsigned int n)
0754 {
0755     struct earlycon_device *dev = con->data;
0756 
0757     uart_console_write(&dev->port, s, n, sunplus_uart_putc);
0758 }
0759 
0760 static int __init
0761 sunplus_uart_early_setup(struct earlycon_device *dev, const char *opt)
0762 {
0763     if (!(dev->port.membase || dev->port.iobase))
0764         return -ENODEV;
0765 
0766     dev->con->write = sunplus_uart_early_write;
0767 
0768     return 0;
0769 }
0770 OF_EARLYCON_DECLARE(sunplus_uart, "sunplus,sp7021-uart", sunplus_uart_early_setup);
0771 #endif
0772 
0773 MODULE_DESCRIPTION("Sunplus UART driver");
0774 MODULE_AUTHOR("Hammer Hsieh <hammerh0314@gmail.com>");
0775 MODULE_LICENSE("GPL v2");
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