tty/serial/stm32-usart.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) Maxime Coquelin 2015
0004  * Copyright (C) STMicroelectronics SA 2017
0005  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
0006  *       Gerald Baeza <gerald_baeza@yahoo.fr>
0007  */
0008
0009 #define DRIVER_NAME "stm32-usart"
0010
0011 struct stm32_usart_offsets {
0012     u8 cr1;
0013     u8 cr2;
0014     u8 cr3;
0015     u8 brr;
0016     u8 gtpr;
0017     u8 rtor;
0018     u8 rqr;
0019     u8 isr;
0020     u8 icr;
0021     u8 rdr;
0022     u8 tdr;
0023 };
0024
0025 struct stm32_usart_config {
0026     u8 uart_enable_bit; /* USART_CR1_UE */
0027     bool has_7bits_data;
0028     bool has_swap;
0029     bool has_wakeup;
0030     bool has_fifo;
0031     int fifosize;
0032 };
0033
0034 struct stm32_usart_info {
0035     struct stm32_usart_offsets ofs;
0036     struct stm32_usart_config cfg;
0037 };
0038
0039 #define UNDEF_REG 0xff
0040
0041 /* USART_SR (F4) / USART_ISR (F7) */
0042 #define USART_SR_PE     BIT(0)
0043 #define USART_SR_FE     BIT(1)
0044 #define USART_SR_NE     BIT(2)      /* F7 (NF for F4) */
0045 #define USART_SR_ORE        BIT(3)
0046 #define USART_SR_IDLE       BIT(4)
0047 #define USART_SR_RXNE       BIT(5)
0048 #define USART_SR_TC     BIT(6)
0049 #define USART_SR_TXE        BIT(7)
0050 #define USART_SR_CTSIF      BIT(9)
0051 #define USART_SR_CTS        BIT(10)     /* F7 */
0052 #define USART_SR_RTOF       BIT(11)     /* F7 */
0053 #define USART_SR_EOBF       BIT(12)     /* F7 */
0054 #define USART_SR_ABRE       BIT(14)     /* F7 */
0055 #define USART_SR_ABRF       BIT(15)     /* F7 */
0056 #define USART_SR_BUSY       BIT(16)     /* F7 */
0057 #define USART_SR_CMF        BIT(17)     /* F7 */
0058 #define USART_SR_SBKF       BIT(18)     /* F7 */
0059 #define USART_SR_WUF        BIT(20)     /* H7 */
0060 #define USART_SR_TEACK      BIT(21)     /* F7 */
0061 #define USART_SR_ERR_MASK   (USART_SR_ORE | USART_SR_NE | USART_SR_FE |\
0062                  USART_SR_PE)
0063 /* Dummy bits */
0064 #define USART_SR_DUMMY_RX   BIT(16)
0065
0066 /* USART_DR */
0067 #define USART_DR_MASK       GENMASK(8, 0)
0068
0069 /* USART_BRR */
0070 #define USART_BRR_DIV_F_MASK    GENMASK(3, 0)
0071 #define USART_BRR_DIV_M_MASK    GENMASK(15, 4)
0072 #define USART_BRR_DIV_M_SHIFT   4
0073 #define USART_BRR_04_R_SHIFT    1
0074
0075 /* USART_CR1 */
0076 #define USART_CR1_SBK       BIT(0)
0077 #define USART_CR1_RWU       BIT(1)      /* F4 */
0078 #define USART_CR1_UESM      BIT(1)      /* H7 */
0079 #define USART_CR1_RE        BIT(2)
0080 #define USART_CR1_TE        BIT(3)
0081 #define USART_CR1_IDLEIE    BIT(4)
0082 #define USART_CR1_RXNEIE    BIT(5)
0083 #define USART_CR1_TCIE      BIT(6)
0084 #define USART_CR1_TXEIE     BIT(7)
0085 #define USART_CR1_PEIE      BIT(8)
0086 #define USART_CR1_PS        BIT(9)
0087 #define USART_CR1_PCE       BIT(10)
0088 #define USART_CR1_WAKE      BIT(11)
0089 #define USART_CR1_M0        BIT(12)     /* F7 (CR1_M for F4) */
0090 #define USART_CR1_MME       BIT(13)     /* F7 */
0091 #define USART_CR1_CMIE      BIT(14)     /* F7 */
0092 #define USART_CR1_OVER8     BIT(15)
0093 #define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
0094 #define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
0095 #define USART_CR1_RTOIE     BIT(26)     /* F7 */
0096 #define USART_CR1_EOBIE     BIT(27)     /* F7 */
0097 #define USART_CR1_M1        BIT(28)     /* F7 */
0098 #define USART_CR1_IE_MASK   (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
0099 #define USART_CR1_FIFOEN    BIT(29)     /* H7 */
0100 #define USART_CR1_DEAT_SHIFT 21
0101 #define USART_CR1_DEDT_SHIFT 16
0102
0103 /* USART_CR2 */
0104 #define USART_CR2_ADD_MASK  GENMASK(3, 0)   /* F4 */
0105 #define USART_CR2_ADDM7     BIT(4)      /* F7 */
0106 #define USART_CR2_LBCL      BIT(8)
0107 #define USART_CR2_CPHA      BIT(9)
0108 #define USART_CR2_CPOL      BIT(10)
0109 #define USART_CR2_CLKEN     BIT(11)
0110 #define USART_CR2_STOP_2B   BIT(13)
0111 #define USART_CR2_STOP_MASK GENMASK(13, 12)
0112 #define USART_CR2_LINEN     BIT(14)
0113 #define USART_CR2_SWAP      BIT(15)     /* F7 */
0114 #define USART_CR2_RXINV     BIT(16)     /* F7 */
0115 #define USART_CR2_TXINV     BIT(17)     /* F7 */
0116 #define USART_CR2_DATAINV   BIT(18)     /* F7 */
0117 #define USART_CR2_MSBFIRST  BIT(19)     /* F7 */
0118 #define USART_CR2_ABREN     BIT(20)     /* F7 */
0119 #define USART_CR2_ABRMOD_MASK   GENMASK(22, 21) /* F7 */
0120 #define USART_CR2_RTOEN     BIT(23)     /* F7 */
0121 #define USART_CR2_ADD_F7_MASK   GENMASK(31, 24) /* F7 */
0122
0123 /* USART_CR3 */
0124 #define USART_CR3_EIE       BIT(0)
0125 #define USART_CR3_IREN      BIT(1)
0126 #define USART_CR3_IRLP      BIT(2)
0127 #define USART_CR3_HDSEL     BIT(3)
0128 #define USART_CR3_NACK      BIT(4)
0129 #define USART_CR3_SCEN      BIT(5)
0130 #define USART_CR3_DMAR      BIT(6)
0131 #define USART_CR3_DMAT      BIT(7)
0132 #define USART_CR3_RTSE      BIT(8)
0133 #define USART_CR3_CTSE      BIT(9)
0134 #define USART_CR3_CTSIE     BIT(10)
0135 #define USART_CR3_ONEBIT    BIT(11)
0136 #define USART_CR3_OVRDIS    BIT(12)     /* F7 */
0137 #define USART_CR3_DDRE      BIT(13)     /* F7 */
0138 #define USART_CR3_DEM       BIT(14)     /* F7 */
0139 #define USART_CR3_DEP       BIT(15)     /* F7 */
0140 #define USART_CR3_SCARCNT_MASK  GENMASK(19, 17) /* F7 */
0141 #define USART_CR3_WUS_MASK  GENMASK(21, 20) /* H7 */
0142 #define USART_CR3_WUS_START_BIT BIT(21)     /* H7 */
0143 #define USART_CR3_WUFIE     BIT(22)     /* H7 */
0144 #define USART_CR3_TXFTIE    BIT(23)     /* H7 */
0145 #define USART_CR3_TCBGTIE   BIT(24)     /* H7 */
0146 #define USART_CR3_RXFTCFG_MASK  GENMASK(27, 25) /* H7 */
0147 #define USART_CR3_RXFTCFG_SHIFT 25      /* H7 */
0148 #define USART_CR3_RXFTIE    BIT(28)     /* H7 */
0149 #define USART_CR3_TXFTCFG_MASK  GENMASK(31, 29) /* H7 */
0150 #define USART_CR3_TXFTCFG_SHIFT 29      /* H7 */
0151
0152 /* USART_GTPR */
0153 #define USART_GTPR_PSC_MASK GENMASK(7, 0)
0154 #define USART_GTPR_GT_MASK  GENMASK(15, 8)
0155
0156 /* USART_RTOR */
0157 #define USART_RTOR_RTO_MASK GENMASK(23, 0)  /* F7 */
0158 #define USART_RTOR_BLEN_MASK    GENMASK(31, 24) /* F7 */
0159
0160 /* USART_RQR */
0161 #define USART_RQR_ABRRQ     BIT(0)      /* F7 */
0162 #define USART_RQR_SBKRQ     BIT(1)      /* F7 */
0163 #define USART_RQR_MMRQ      BIT(2)      /* F7 */
0164 #define USART_RQR_RXFRQ     BIT(3)      /* F7 */
0165 #define USART_RQR_TXFRQ     BIT(4)      /* F7 */
0166
0167 /* USART_ICR */
0168 #define USART_ICR_PECF      BIT(0)      /* F7 */
0169 #define USART_ICR_FECF      BIT(1)      /* F7 */
0170 #define USART_ICR_ORECF     BIT(3)      /* F7 */
0171 #define USART_ICR_IDLECF    BIT(4)      /* F7 */
0172 #define USART_ICR_TCCF      BIT(6)      /* F7 */
0173 #define USART_ICR_CTSCF     BIT(9)      /* F7 */
0174 #define USART_ICR_RTOCF     BIT(11)     /* F7 */
0175 #define USART_ICR_EOBCF     BIT(12)     /* F7 */
0176 #define USART_ICR_CMCF      BIT(17)     /* F7 */
0177 #define USART_ICR_WUCF      BIT(20)     /* H7 */
0178
0179 #define STM32_SERIAL_NAME "ttySTM"
0180 #define STM32_MAX_PORTS 8
0181
0182 #define RX_BUF_L 4096        /* dma rx buffer length     */
0183 #define RX_BUF_P (RX_BUF_L / 2)  /* dma rx buffer period     */
0184 #define TX_BUF_L RX_BUF_L    /* dma tx buffer length     */
0185
0186 #define STM32_USART_TIMEOUT_USEC USEC_PER_SEC /* 1s timeout in µs */
0187
0188 struct stm32_port {
0189     struct uart_port port;
0190     struct clk *clk;
0191     const struct stm32_usart_info *info;
0192     struct dma_chan *rx_ch;  /* dma rx channel            */
0193     dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
0194     unsigned char *rx_buf;   /* dma rx buffer cpu address */
0195     struct dma_chan *tx_ch;  /* dma tx channel            */
0196     dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
0197     unsigned char *tx_buf;   /* dma tx buffer cpu address */
0198     u32 cr1_irq;         /* USART_CR1_RXNEIE or RTOIE */
0199     u32 cr3_irq;         /* USART_CR3_RXFTIE */
0200     int last_res;
0201     bool tx_dma_busy;    /* dma tx transaction in progress */
0202     bool throttled;      /* port throttled            */
0203     bool hw_flow_control;
0204     bool swap;       /* swap RX & TX pins */
0205     bool fifoen;
0206     bool txdone;
0207     int rxftcfg;        /* RX FIFO threshold CFG      */
0208     int txftcfg;        /* TX FIFO threshold CFG      */
0209     bool wakeup_src;
0210     int rdr_mask;       /* receive data register mask */
0211     struct mctrl_gpios *gpios; /* modem control gpios */
0212     struct dma_tx_state rx_dma_state;
0213 };
0214
0215 static struct stm32_port stm32_ports[STM32_MAX_PORTS];
0216 static struct uart_driver stm32_usart_driver;