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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) Maxime Coquelin 2015
0004  * Copyright (C) STMicroelectronics SA 2017
0005  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
0006  *       Gerald Baeza <gerald.baeza@foss.st.com>
0007  *       Erwan Le Ray <erwan.leray@foss.st.com>
0008  *
0009  * Inspired by st-asc.c from STMicroelectronics (c)
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/console.h>
0014 #include <linux/delay.h>
0015 #include <linux/dma-direction.h>
0016 #include <linux/dmaengine.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/io.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/irq.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_platform.h>
0024 #include <linux/pinctrl/consumer.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/pm_runtime.h>
0027 #include <linux/pm_wakeirq.h>
0028 #include <linux/serial_core.h>
0029 #include <linux/serial.h>
0030 #include <linux/spinlock.h>
0031 #include <linux/sysrq.h>
0032 #include <linux/tty_flip.h>
0033 #include <linux/tty.h>
0034 
0035 #include "serial_mctrl_gpio.h"
0036 #include "stm32-usart.h"
0037 
0038 
0039 /* Register offsets */
0040 static struct stm32_usart_info stm32f4_info = {
0041     .ofs = {
0042         .isr    = 0x00,
0043         .rdr    = 0x04,
0044         .tdr    = 0x04,
0045         .brr    = 0x08,
0046         .cr1    = 0x0c,
0047         .cr2    = 0x10,
0048         .cr3    = 0x14,
0049         .gtpr   = 0x18,
0050         .rtor   = UNDEF_REG,
0051         .rqr    = UNDEF_REG,
0052         .icr    = UNDEF_REG,
0053     },
0054     .cfg = {
0055         .uart_enable_bit = 13,
0056         .has_7bits_data = false,
0057         .fifosize = 1,
0058     }
0059 };
0060 
0061 static struct stm32_usart_info stm32f7_info = {
0062     .ofs = {
0063         .cr1    = 0x00,
0064         .cr2    = 0x04,
0065         .cr3    = 0x08,
0066         .brr    = 0x0c,
0067         .gtpr   = 0x10,
0068         .rtor   = 0x14,
0069         .rqr    = 0x18,
0070         .isr    = 0x1c,
0071         .icr    = 0x20,
0072         .rdr    = 0x24,
0073         .tdr    = 0x28,
0074     },
0075     .cfg = {
0076         .uart_enable_bit = 0,
0077         .has_7bits_data = true,
0078         .has_swap = true,
0079         .fifosize = 1,
0080     }
0081 };
0082 
0083 static struct stm32_usart_info stm32h7_info = {
0084     .ofs = {
0085         .cr1    = 0x00,
0086         .cr2    = 0x04,
0087         .cr3    = 0x08,
0088         .brr    = 0x0c,
0089         .gtpr   = 0x10,
0090         .rtor   = 0x14,
0091         .rqr    = 0x18,
0092         .isr    = 0x1c,
0093         .icr    = 0x20,
0094         .rdr    = 0x24,
0095         .tdr    = 0x28,
0096     },
0097     .cfg = {
0098         .uart_enable_bit = 0,
0099         .has_7bits_data = true,
0100         .has_swap = true,
0101         .has_wakeup = true,
0102         .has_fifo = true,
0103         .fifosize = 16,
0104     }
0105 };
0106 
0107 static void stm32_usart_stop_tx(struct uart_port *port);
0108 static void stm32_usart_transmit_chars(struct uart_port *port);
0109 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
0110 
0111 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
0112 {
0113     return container_of(port, struct stm32_port, port);
0114 }
0115 
0116 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
0117 {
0118     u32 val;
0119 
0120     val = readl_relaxed(port->membase + reg);
0121     val |= bits;
0122     writel_relaxed(val, port->membase + reg);
0123 }
0124 
0125 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
0126 {
0127     u32 val;
0128 
0129     val = readl_relaxed(port->membase + reg);
0130     val &= ~bits;
0131     writel_relaxed(val, port->membase + reg);
0132 }
0133 
0134 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
0135                      u32 delay_DDE, u32 baud)
0136 {
0137     u32 rs485_deat_dedt;
0138     u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
0139     bool over8;
0140 
0141     *cr3 |= USART_CR3_DEM;
0142     over8 = *cr1 & USART_CR1_OVER8;
0143 
0144     *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
0145 
0146     if (over8)
0147         rs485_deat_dedt = delay_ADE * baud * 8;
0148     else
0149         rs485_deat_dedt = delay_ADE * baud * 16;
0150 
0151     rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
0152     rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
0153               rs485_deat_dedt_max : rs485_deat_dedt;
0154     rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
0155                USART_CR1_DEAT_MASK;
0156     *cr1 |= rs485_deat_dedt;
0157 
0158     if (over8)
0159         rs485_deat_dedt = delay_DDE * baud * 8;
0160     else
0161         rs485_deat_dedt = delay_DDE * baud * 16;
0162 
0163     rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
0164     rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
0165               rs485_deat_dedt_max : rs485_deat_dedt;
0166     rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
0167                USART_CR1_DEDT_MASK;
0168     *cr1 |= rs485_deat_dedt;
0169 }
0170 
0171 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios,
0172                     struct serial_rs485 *rs485conf)
0173 {
0174     struct stm32_port *stm32_port = to_stm32_port(port);
0175     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0176     const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
0177     u32 usartdiv, baud, cr1, cr3;
0178     bool over8;
0179 
0180     stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
0181 
0182     rs485conf->flags |= SER_RS485_RX_DURING_TX;
0183 
0184     if (rs485conf->flags & SER_RS485_ENABLED) {
0185         cr1 = readl_relaxed(port->membase + ofs->cr1);
0186         cr3 = readl_relaxed(port->membase + ofs->cr3);
0187         usartdiv = readl_relaxed(port->membase + ofs->brr);
0188         usartdiv = usartdiv & GENMASK(15, 0);
0189         over8 = cr1 & USART_CR1_OVER8;
0190 
0191         if (over8)
0192             usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
0193                    << USART_BRR_04_R_SHIFT;
0194 
0195         baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
0196         stm32_usart_config_reg_rs485(&cr1, &cr3,
0197                          rs485conf->delay_rts_before_send,
0198                          rs485conf->delay_rts_after_send,
0199                          baud);
0200 
0201         if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
0202             cr3 &= ~USART_CR3_DEP;
0203         else
0204             cr3 |= USART_CR3_DEP;
0205 
0206         writel_relaxed(cr3, port->membase + ofs->cr3);
0207         writel_relaxed(cr1, port->membase + ofs->cr1);
0208     } else {
0209         stm32_usart_clr_bits(port, ofs->cr3,
0210                      USART_CR3_DEM | USART_CR3_DEP);
0211         stm32_usart_clr_bits(port, ofs->cr1,
0212                      USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
0213     }
0214 
0215     stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
0216 
0217     return 0;
0218 }
0219 
0220 static int stm32_usart_init_rs485(struct uart_port *port,
0221                   struct platform_device *pdev)
0222 {
0223     struct serial_rs485 *rs485conf = &port->rs485;
0224 
0225     rs485conf->flags = 0;
0226     rs485conf->delay_rts_before_send = 0;
0227     rs485conf->delay_rts_after_send = 0;
0228 
0229     if (!pdev->dev.of_node)
0230         return -ENODEV;
0231 
0232     return uart_get_rs485_mode(port);
0233 }
0234 
0235 static bool stm32_usart_rx_dma_enabled(struct uart_port *port)
0236 {
0237     struct stm32_port *stm32_port = to_stm32_port(port);
0238     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0239 
0240     if (!stm32_port->rx_ch)
0241         return false;
0242 
0243     return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR);
0244 }
0245 
0246 /* Return true when data is pending (in pio mode), and false when no data is pending. */
0247 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
0248 {
0249     struct stm32_port *stm32_port = to_stm32_port(port);
0250     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0251 
0252     *sr = readl_relaxed(port->membase + ofs->isr);
0253     /* Get pending characters in RDR or FIFO */
0254     if (*sr & USART_SR_RXNE) {
0255         /* Get all pending characters from the RDR or the FIFO when using interrupts */
0256         if (!stm32_usart_rx_dma_enabled(port))
0257             return true;
0258 
0259         /* Handle only RX data errors when using DMA */
0260         if (*sr & USART_SR_ERR_MASK)
0261             return true;
0262     }
0263 
0264     return false;
0265 }
0266 
0267 static unsigned long stm32_usart_get_char_pio(struct uart_port *port)
0268 {
0269     struct stm32_port *stm32_port = to_stm32_port(port);
0270     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0271     unsigned long c;
0272 
0273     c = readl_relaxed(port->membase + ofs->rdr);
0274     /* Apply RDR data mask */
0275     c &= stm32_port->rdr_mask;
0276 
0277     return c;
0278 }
0279 
0280 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
0281 {
0282     struct stm32_port *stm32_port = to_stm32_port(port);
0283     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0284     unsigned long c;
0285     unsigned int size = 0;
0286     u32 sr;
0287     char flag;
0288 
0289     while (stm32_usart_pending_rx_pio(port, &sr)) {
0290         sr |= USART_SR_DUMMY_RX;
0291         flag = TTY_NORMAL;
0292 
0293         /*
0294          * Status bits has to be cleared before reading the RDR:
0295          * In FIFO mode, reading the RDR will pop the next data
0296          * (if any) along with its status bits into the SR.
0297          * Not doing so leads to misalignement between RDR and SR,
0298          * and clear status bits of the next rx data.
0299          *
0300          * Clear errors flags for stm32f7 and stm32h7 compatible
0301          * devices. On stm32f4 compatible devices, the error bit is
0302          * cleared by the sequence [read SR - read DR].
0303          */
0304         if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
0305             writel_relaxed(sr & USART_SR_ERR_MASK,
0306                        port->membase + ofs->icr);
0307 
0308         c = stm32_usart_get_char_pio(port);
0309         port->icount.rx++;
0310         size++;
0311         if (sr & USART_SR_ERR_MASK) {
0312             if (sr & USART_SR_ORE) {
0313                 port->icount.overrun++;
0314             } else if (sr & USART_SR_PE) {
0315                 port->icount.parity++;
0316             } else if (sr & USART_SR_FE) {
0317                 /* Break detection if character is null */
0318                 if (!c) {
0319                     port->icount.brk++;
0320                     if (uart_handle_break(port))
0321                         continue;
0322                 } else {
0323                     port->icount.frame++;
0324                 }
0325             }
0326 
0327             sr &= port->read_status_mask;
0328 
0329             if (sr & USART_SR_PE) {
0330                 flag = TTY_PARITY;
0331             } else if (sr & USART_SR_FE) {
0332                 if (!c)
0333                     flag = TTY_BREAK;
0334                 else
0335                     flag = TTY_FRAME;
0336             }
0337         }
0338 
0339         if (uart_prepare_sysrq_char(port, c))
0340             continue;
0341         uart_insert_char(port, sr, USART_SR_ORE, c, flag);
0342     }
0343 
0344     return size;
0345 }
0346 
0347 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size)
0348 {
0349     struct stm32_port *stm32_port = to_stm32_port(port);
0350     struct tty_port *ttyport = &stm32_port->port.state->port;
0351     unsigned char *dma_start;
0352     int dma_count, i;
0353 
0354     dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
0355 
0356     /*
0357      * Apply rdr_mask on buffer in order to mask parity bit.
0358      * This loop is useless in cs8 mode because DMA copies only
0359      * 8 bits and already ignores parity bit.
0360      */
0361     if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
0362         for (i = 0; i < dma_size; i++)
0363             *(dma_start + i) &= stm32_port->rdr_mask;
0364 
0365     dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size);
0366     port->icount.rx += dma_count;
0367     if (dma_count != dma_size)
0368         port->icount.buf_overrun++;
0369     stm32_port->last_res -= dma_count;
0370     if (stm32_port->last_res == 0)
0371         stm32_port->last_res = RX_BUF_L;
0372 }
0373 
0374 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port)
0375 {
0376     struct stm32_port *stm32_port = to_stm32_port(port);
0377     unsigned int dma_size, size = 0;
0378 
0379     /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */
0380     if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
0381         /* Conditional first part: from last_res to end of DMA buffer */
0382         dma_size = stm32_port->last_res;
0383         stm32_usart_push_buffer_dma(port, dma_size);
0384         size = dma_size;
0385     }
0386 
0387     dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
0388     stm32_usart_push_buffer_dma(port, dma_size);
0389     size += dma_size;
0390 
0391     return size;
0392 }
0393 
0394 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush)
0395 {
0396     struct stm32_port *stm32_port = to_stm32_port(port);
0397     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0398     enum dma_status rx_dma_status;
0399     u32 sr;
0400     unsigned int size = 0;
0401 
0402     if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) {
0403         rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
0404                             stm32_port->rx_ch->cookie,
0405                             &stm32_port->rx_dma_state);
0406         if (rx_dma_status == DMA_IN_PROGRESS) {
0407             /* Empty DMA buffer */
0408             size = stm32_usart_receive_chars_dma(port);
0409             sr = readl_relaxed(port->membase + ofs->isr);
0410             if (sr & USART_SR_ERR_MASK) {
0411                 /* Disable DMA request line */
0412                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
0413 
0414                 /* Switch to PIO mode to handle the errors */
0415                 size += stm32_usart_receive_chars_pio(port);
0416 
0417                 /* Switch back to DMA mode */
0418                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
0419             }
0420         } else {
0421             /* Disable RX DMA */
0422             dmaengine_terminate_async(stm32_port->rx_ch);
0423             stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
0424             /* Fall back to interrupt mode */
0425             dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
0426             size = stm32_usart_receive_chars_pio(port);
0427         }
0428     } else {
0429         size = stm32_usart_receive_chars_pio(port);
0430     }
0431 
0432     return size;
0433 }
0434 
0435 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
0436 {
0437     dmaengine_terminate_async(stm32_port->tx_ch);
0438     stm32_port->tx_dma_busy = false;
0439 }
0440 
0441 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
0442 {
0443     /*
0444      * We cannot use the function "dmaengine_tx_status" to know the
0445      * status of DMA. This function does not show if the "dma complete"
0446      * callback of the DMA transaction has been called. So we prefer
0447      * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
0448      * same time.
0449      */
0450     return stm32_port->tx_dma_busy;
0451 }
0452 
0453 static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
0454 {
0455     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0456 
0457     return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
0458 }
0459 
0460 static void stm32_usart_tx_dma_complete(void *arg)
0461 {
0462     struct uart_port *port = arg;
0463     struct stm32_port *stm32port = to_stm32_port(port);
0464     const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
0465     unsigned long flags;
0466 
0467     stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
0468     stm32_usart_tx_dma_terminate(stm32port);
0469 
0470     /* Let's see if we have pending data to send */
0471     spin_lock_irqsave(&port->lock, flags);
0472     stm32_usart_transmit_chars(port);
0473     spin_unlock_irqrestore(&port->lock, flags);
0474 }
0475 
0476 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
0477 {
0478     struct stm32_port *stm32_port = to_stm32_port(port);
0479     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0480 
0481     /*
0482      * Enables TX FIFO threashold irq when FIFO is enabled,
0483      * or TX empty irq when FIFO is disabled
0484      */
0485     if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
0486         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
0487     else
0488         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
0489 }
0490 
0491 static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
0492 {
0493     struct stm32_port *stm32_port = to_stm32_port(port);
0494     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0495 
0496     stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
0497 }
0498 
0499 static void stm32_usart_rx_dma_complete(void *arg)
0500 {
0501     struct uart_port *port = arg;
0502     struct tty_port *tport = &port->state->port;
0503     unsigned int size;
0504     unsigned long flags;
0505 
0506     spin_lock_irqsave(&port->lock, flags);
0507     size = stm32_usart_receive_chars(port, false);
0508     uart_unlock_and_check_sysrq_irqrestore(port, flags);
0509     if (size)
0510         tty_flip_buffer_push(tport);
0511 }
0512 
0513 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
0514 {
0515     struct stm32_port *stm32_port = to_stm32_port(port);
0516     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0517 
0518     if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
0519         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
0520     else
0521         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
0522 }
0523 
0524 static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
0525 {
0526     struct stm32_port *stm32_port = to_stm32_port(port);
0527     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0528 
0529     stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
0530 }
0531 
0532 static void stm32_usart_rs485_rts_enable(struct uart_port *port)
0533 {
0534     struct stm32_port *stm32_port = to_stm32_port(port);
0535     struct serial_rs485 *rs485conf = &port->rs485;
0536 
0537     if (stm32_port->hw_flow_control ||
0538         !(rs485conf->flags & SER_RS485_ENABLED))
0539         return;
0540 
0541     if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
0542         mctrl_gpio_set(stm32_port->gpios,
0543                    stm32_port->port.mctrl | TIOCM_RTS);
0544     } else {
0545         mctrl_gpio_set(stm32_port->gpios,
0546                    stm32_port->port.mctrl & ~TIOCM_RTS);
0547     }
0548 }
0549 
0550 static void stm32_usart_rs485_rts_disable(struct uart_port *port)
0551 {
0552     struct stm32_port *stm32_port = to_stm32_port(port);
0553     struct serial_rs485 *rs485conf = &port->rs485;
0554 
0555     if (stm32_port->hw_flow_control ||
0556         !(rs485conf->flags & SER_RS485_ENABLED))
0557         return;
0558 
0559     if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
0560         mctrl_gpio_set(stm32_port->gpios,
0561                    stm32_port->port.mctrl & ~TIOCM_RTS);
0562     } else {
0563         mctrl_gpio_set(stm32_port->gpios,
0564                    stm32_port->port.mctrl | TIOCM_RTS);
0565     }
0566 }
0567 
0568 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
0569 {
0570     struct stm32_port *stm32_port = to_stm32_port(port);
0571     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0572     struct circ_buf *xmit = &port->state->xmit;
0573 
0574     if (stm32_usart_tx_dma_enabled(stm32_port))
0575         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
0576 
0577     while (!uart_circ_empty(xmit)) {
0578         /* Check that TDR is empty before filling FIFO */
0579         if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
0580             break;
0581         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
0582         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0583         port->icount.tx++;
0584     }
0585 
0586     /* rely on TXE irq (mask or unmask) for sending remaining data */
0587     if (uart_circ_empty(xmit))
0588         stm32_usart_tx_interrupt_disable(port);
0589     else
0590         stm32_usart_tx_interrupt_enable(port);
0591 }
0592 
0593 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
0594 {
0595     struct stm32_port *stm32port = to_stm32_port(port);
0596     const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
0597     struct circ_buf *xmit = &port->state->xmit;
0598     struct dma_async_tx_descriptor *desc = NULL;
0599     unsigned int count;
0600 
0601     if (stm32_usart_tx_dma_started(stm32port)) {
0602         if (!stm32_usart_tx_dma_enabled(stm32port))
0603             stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
0604         return;
0605     }
0606 
0607     count = uart_circ_chars_pending(xmit);
0608 
0609     if (count > TX_BUF_L)
0610         count = TX_BUF_L;
0611 
0612     if (xmit->tail < xmit->head) {
0613         memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
0614     } else {
0615         size_t one = UART_XMIT_SIZE - xmit->tail;
0616         size_t two;
0617 
0618         if (one > count)
0619             one = count;
0620         two = count - one;
0621 
0622         memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
0623         if (two)
0624             memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
0625     }
0626 
0627     desc = dmaengine_prep_slave_single(stm32port->tx_ch,
0628                        stm32port->tx_dma_buf,
0629                        count,
0630                        DMA_MEM_TO_DEV,
0631                        DMA_PREP_INTERRUPT);
0632 
0633     if (!desc)
0634         goto fallback_err;
0635 
0636     /*
0637      * Set "tx_dma_busy" flag. This flag will be released when
0638      * dmaengine_terminate_async will be called. This flag helps
0639      * transmit_chars_dma not to start another DMA transaction
0640      * if the callback of the previous is not yet called.
0641      */
0642     stm32port->tx_dma_busy = true;
0643 
0644     desc->callback = stm32_usart_tx_dma_complete;
0645     desc->callback_param = port;
0646 
0647     /* Push current DMA TX transaction in the pending queue */
0648     if (dma_submit_error(dmaengine_submit(desc))) {
0649         /* dma no yet started, safe to free resources */
0650         stm32_usart_tx_dma_terminate(stm32port);
0651         goto fallback_err;
0652     }
0653 
0654     /* Issue pending DMA TX requests */
0655     dma_async_issue_pending(stm32port->tx_ch);
0656 
0657     stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
0658 
0659     xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
0660     port->icount.tx += count;
0661     return;
0662 
0663 fallback_err:
0664     stm32_usart_transmit_chars_pio(port);
0665 }
0666 
0667 static void stm32_usart_transmit_chars(struct uart_port *port)
0668 {
0669     struct stm32_port *stm32_port = to_stm32_port(port);
0670     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0671     struct circ_buf *xmit = &port->state->xmit;
0672     u32 isr;
0673     int ret;
0674 
0675     if (!stm32_port->hw_flow_control &&
0676         port->rs485.flags & SER_RS485_ENABLED) {
0677         stm32_port->txdone = false;
0678         stm32_usart_tc_interrupt_disable(port);
0679         stm32_usart_rs485_rts_enable(port);
0680     }
0681 
0682     if (port->x_char) {
0683         if (stm32_usart_tx_dma_started(stm32_port) &&
0684             stm32_usart_tx_dma_enabled(stm32_port))
0685             stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
0686 
0687         /* Check that TDR is empty before filling FIFO */
0688         ret =
0689         readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
0690                           isr,
0691                           (isr & USART_SR_TXE),
0692                           10, 1000);
0693         if (ret)
0694             dev_warn(port->dev, "1 character may be erased\n");
0695 
0696         writel_relaxed(port->x_char, port->membase + ofs->tdr);
0697         port->x_char = 0;
0698         port->icount.tx++;
0699         if (stm32_usart_tx_dma_started(stm32_port))
0700             stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
0701         return;
0702     }
0703 
0704     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0705         stm32_usart_tx_interrupt_disable(port);
0706         return;
0707     }
0708 
0709     if (ofs->icr == UNDEF_REG)
0710         stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
0711     else
0712         writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
0713 
0714     if (stm32_port->tx_ch)
0715         stm32_usart_transmit_chars_dma(port);
0716     else
0717         stm32_usart_transmit_chars_pio(port);
0718 
0719     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0720         uart_write_wakeup(port);
0721 
0722     if (uart_circ_empty(xmit)) {
0723         stm32_usart_tx_interrupt_disable(port);
0724         if (!stm32_port->hw_flow_control &&
0725             port->rs485.flags & SER_RS485_ENABLED) {
0726             stm32_port->txdone = true;
0727             stm32_usart_tc_interrupt_enable(port);
0728         }
0729     }
0730 }
0731 
0732 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
0733 {
0734     struct uart_port *port = ptr;
0735     struct tty_port *tport = &port->state->port;
0736     struct stm32_port *stm32_port = to_stm32_port(port);
0737     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0738     u32 sr;
0739     unsigned int size;
0740 
0741     sr = readl_relaxed(port->membase + ofs->isr);
0742 
0743     if (!stm32_port->hw_flow_control &&
0744         port->rs485.flags & SER_RS485_ENABLED &&
0745         (sr & USART_SR_TC)) {
0746         stm32_usart_tc_interrupt_disable(port);
0747         stm32_usart_rs485_rts_disable(port);
0748     }
0749 
0750     if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
0751         writel_relaxed(USART_ICR_RTOCF,
0752                    port->membase + ofs->icr);
0753 
0754     if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
0755         /* Clear wake up flag and disable wake up interrupt */
0756         writel_relaxed(USART_ICR_WUCF,
0757                    port->membase + ofs->icr);
0758         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
0759         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
0760             pm_wakeup_event(tport->tty->dev, 0);
0761     }
0762 
0763     /*
0764      * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
0765      * line has been masked by HW and rx data are stacking in FIFO.
0766      */
0767     if (!stm32_port->throttled) {
0768         if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) ||
0769             ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) {
0770             spin_lock(&port->lock);
0771             size = stm32_usart_receive_chars(port, false);
0772             uart_unlock_and_check_sysrq(port);
0773             if (size)
0774                 tty_flip_buffer_push(tport);
0775         }
0776     }
0777 
0778     if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
0779         spin_lock(&port->lock);
0780         stm32_usart_transmit_chars(port);
0781         spin_unlock(&port->lock);
0782     }
0783 
0784     if (stm32_usart_rx_dma_enabled(port))
0785         return IRQ_WAKE_THREAD;
0786     else
0787         return IRQ_HANDLED;
0788 }
0789 
0790 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
0791 {
0792     struct uart_port *port = ptr;
0793     struct tty_port *tport = &port->state->port;
0794     struct stm32_port *stm32_port = to_stm32_port(port);
0795     unsigned int size;
0796     unsigned long flags;
0797 
0798     /* Receiver timeout irq for DMA RX */
0799     if (!stm32_port->throttled) {
0800         spin_lock_irqsave(&port->lock, flags);
0801         size = stm32_usart_receive_chars(port, false);
0802         uart_unlock_and_check_sysrq_irqrestore(port, flags);
0803         if (size)
0804             tty_flip_buffer_push(tport);
0805     }
0806 
0807     return IRQ_HANDLED;
0808 }
0809 
0810 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
0811 {
0812     struct stm32_port *stm32_port = to_stm32_port(port);
0813     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0814 
0815     if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
0816         return TIOCSER_TEMT;
0817 
0818     return 0;
0819 }
0820 
0821 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0822 {
0823     struct stm32_port *stm32_port = to_stm32_port(port);
0824     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0825 
0826     if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
0827         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
0828     else
0829         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
0830 
0831     mctrl_gpio_set(stm32_port->gpios, mctrl);
0832 }
0833 
0834 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
0835 {
0836     struct stm32_port *stm32_port = to_stm32_port(port);
0837     unsigned int ret;
0838 
0839     /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
0840     ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
0841 
0842     return mctrl_gpio_get(stm32_port->gpios, &ret);
0843 }
0844 
0845 static void stm32_usart_enable_ms(struct uart_port *port)
0846 {
0847     mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
0848 }
0849 
0850 static void stm32_usart_disable_ms(struct uart_port *port)
0851 {
0852     mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
0853 }
0854 
0855 /* Transmit stop */
0856 static void stm32_usart_stop_tx(struct uart_port *port)
0857 {
0858     struct stm32_port *stm32_port = to_stm32_port(port);
0859     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0860 
0861     stm32_usart_tx_interrupt_disable(port);
0862     if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
0863         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
0864 
0865     stm32_usart_rs485_rts_disable(port);
0866 }
0867 
0868 /* There are probably characters waiting to be transmitted. */
0869 static void stm32_usart_start_tx(struct uart_port *port)
0870 {
0871     struct circ_buf *xmit = &port->state->xmit;
0872 
0873     if (uart_circ_empty(xmit) && !port->x_char) {
0874         stm32_usart_rs485_rts_disable(port);
0875         return;
0876     }
0877 
0878     stm32_usart_rs485_rts_enable(port);
0879 
0880     stm32_usart_transmit_chars(port);
0881 }
0882 
0883 /* Flush the transmit buffer. */
0884 static void stm32_usart_flush_buffer(struct uart_port *port)
0885 {
0886     struct stm32_port *stm32_port = to_stm32_port(port);
0887     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0888 
0889     if (stm32_port->tx_ch) {
0890         stm32_usart_tx_dma_terminate(stm32_port);
0891         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
0892     }
0893 }
0894 
0895 /* Throttle the remote when input buffer is about to overflow. */
0896 static void stm32_usart_throttle(struct uart_port *port)
0897 {
0898     struct stm32_port *stm32_port = to_stm32_port(port);
0899     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0900     unsigned long flags;
0901 
0902     spin_lock_irqsave(&port->lock, flags);
0903 
0904     /*
0905      * Disable DMA request line if enabled, so the RX data gets queued into the FIFO.
0906      * Hardware flow control is triggered when RX FIFO is full.
0907      */
0908     if (stm32_usart_rx_dma_enabled(port))
0909         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
0910 
0911     stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
0912     if (stm32_port->cr3_irq)
0913         stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
0914 
0915     stm32_port->throttled = true;
0916     spin_unlock_irqrestore(&port->lock, flags);
0917 }
0918 
0919 /* Unthrottle the remote, the input buffer can now accept data. */
0920 static void stm32_usart_unthrottle(struct uart_port *port)
0921 {
0922     struct stm32_port *stm32_port = to_stm32_port(port);
0923     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0924     unsigned long flags;
0925 
0926     spin_lock_irqsave(&port->lock, flags);
0927     stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
0928     if (stm32_port->cr3_irq)
0929         stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
0930 
0931     /*
0932      * Switch back to DMA mode (re-enable DMA request line).
0933      * Hardware flow control is stopped when FIFO is not full any more.
0934      */
0935     if (stm32_port->rx_ch)
0936         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
0937 
0938     stm32_port->throttled = false;
0939     spin_unlock_irqrestore(&port->lock, flags);
0940 }
0941 
0942 /* Receive stop */
0943 static void stm32_usart_stop_rx(struct uart_port *port)
0944 {
0945     struct stm32_port *stm32_port = to_stm32_port(port);
0946     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0947 
0948     /* Disable DMA request line. */
0949     if (stm32_port->rx_ch)
0950         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
0951 
0952     stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
0953     if (stm32_port->cr3_irq)
0954         stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
0955 }
0956 
0957 /* Handle breaks - ignored by us */
0958 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
0959 {
0960 }
0961 
0962 static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port)
0963 {
0964     struct stm32_port *stm32_port = to_stm32_port(port);
0965     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
0966     struct dma_async_tx_descriptor *desc;
0967     int ret;
0968 
0969     stm32_port->last_res = RX_BUF_L;
0970     /* Prepare a DMA cyclic transaction */
0971     desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
0972                      stm32_port->rx_dma_buf,
0973                      RX_BUF_L, RX_BUF_P,
0974                      DMA_DEV_TO_MEM,
0975                      DMA_PREP_INTERRUPT);
0976     if (!desc) {
0977         dev_err(port->dev, "rx dma prep cyclic failed\n");
0978         return -ENODEV;
0979     }
0980 
0981     desc->callback = stm32_usart_rx_dma_complete;
0982     desc->callback_param = port;
0983 
0984     /* Push current DMA transaction in the pending queue */
0985     ret = dma_submit_error(dmaengine_submit(desc));
0986     if (ret) {
0987         dmaengine_terminate_sync(stm32_port->rx_ch);
0988         return ret;
0989     }
0990 
0991     /* Issue pending DMA requests */
0992     dma_async_issue_pending(stm32_port->rx_ch);
0993 
0994     /*
0995      * DMA request line not re-enabled at resume when port is throttled.
0996      * It will be re-enabled by unthrottle ops.
0997      */
0998     if (!stm32_port->throttled)
0999         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
1000 
1001     return 0;
1002 }
1003 
1004 static int stm32_usart_startup(struct uart_port *port)
1005 {
1006     struct stm32_port *stm32_port = to_stm32_port(port);
1007     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1008     const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1009     const char *name = to_platform_device(port->dev)->name;
1010     u32 val;
1011     int ret;
1012 
1013     ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
1014                    stm32_usart_threaded_interrupt,
1015                    IRQF_ONESHOT | IRQF_NO_SUSPEND,
1016                    name, port);
1017     if (ret)
1018         return ret;
1019 
1020     if (stm32_port->swap) {
1021         val = readl_relaxed(port->membase + ofs->cr2);
1022         val |= USART_CR2_SWAP;
1023         writel_relaxed(val, port->membase + ofs->cr2);
1024     }
1025 
1026     /* RX FIFO Flush */
1027     if (ofs->rqr != UNDEF_REG)
1028         writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
1029 
1030     if (stm32_port->rx_ch) {
1031         ret = stm32_usart_start_rx_dma_cyclic(port);
1032         if (ret) {
1033             free_irq(port->irq, port);
1034             return ret;
1035         }
1036     }
1037 
1038     /* RX enabling */
1039     val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
1040     stm32_usart_set_bits(port, ofs->cr1, val);
1041 
1042     return 0;
1043 }
1044 
1045 static void stm32_usart_shutdown(struct uart_port *port)
1046 {
1047     struct stm32_port *stm32_port = to_stm32_port(port);
1048     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1049     const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1050     u32 val, isr;
1051     int ret;
1052 
1053     if (stm32_usart_tx_dma_enabled(stm32_port))
1054         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1055 
1056     if (stm32_usart_tx_dma_started(stm32_port))
1057         stm32_usart_tx_dma_terminate(stm32_port);
1058 
1059     /* Disable modem control interrupts */
1060     stm32_usart_disable_ms(port);
1061 
1062     val = USART_CR1_TXEIE | USART_CR1_TE;
1063     val |= stm32_port->cr1_irq | USART_CR1_RE;
1064     val |= BIT(cfg->uart_enable_bit);
1065     if (stm32_port->fifoen)
1066         val |= USART_CR1_FIFOEN;
1067 
1068     ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
1069                      isr, (isr & USART_SR_TC),
1070                      10, 100000);
1071 
1072     /* Send the TC error message only when ISR_TC is not set */
1073     if (ret)
1074         dev_err(port->dev, "Transmission is not complete\n");
1075 
1076     /* Disable RX DMA. */
1077     if (stm32_port->rx_ch)
1078         dmaengine_terminate_async(stm32_port->rx_ch);
1079 
1080     /* flush RX & TX FIFO */
1081     if (ofs->rqr != UNDEF_REG)
1082         writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1083                    port->membase + ofs->rqr);
1084 
1085     stm32_usart_clr_bits(port, ofs->cr1, val);
1086 
1087     free_irq(port->irq, port);
1088 }
1089 
1090 static void stm32_usart_set_termios(struct uart_port *port,
1091                     struct ktermios *termios,
1092                     struct ktermios *old)
1093 {
1094     struct stm32_port *stm32_port = to_stm32_port(port);
1095     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1096     const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1097     struct serial_rs485 *rs485conf = &port->rs485;
1098     unsigned int baud, bits;
1099     u32 usartdiv, mantissa, fraction, oversampling;
1100     tcflag_t cflag = termios->c_cflag;
1101     u32 cr1, cr2, cr3, isr;
1102     unsigned long flags;
1103     int ret;
1104 
1105     if (!stm32_port->hw_flow_control)
1106         cflag &= ~CRTSCTS;
1107 
1108     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
1109 
1110     spin_lock_irqsave(&port->lock, flags);
1111 
1112     ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
1113                         isr,
1114                         (isr & USART_SR_TC),
1115                         10, 100000);
1116 
1117     /* Send the TC error message only when ISR_TC is not set. */
1118     if (ret)
1119         dev_err(port->dev, "Transmission is not complete\n");
1120 
1121     /* Stop serial port and reset value */
1122     writel_relaxed(0, port->membase + ofs->cr1);
1123 
1124     /* flush RX & TX FIFO */
1125     if (ofs->rqr != UNDEF_REG)
1126         writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1127                    port->membase + ofs->rqr);
1128 
1129     cr1 = USART_CR1_TE | USART_CR1_RE;
1130     if (stm32_port->fifoen)
1131         cr1 |= USART_CR1_FIFOEN;
1132     cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1133 
1134     /* Tx and RX FIFO configuration */
1135     cr3 = readl_relaxed(port->membase + ofs->cr3);
1136     cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
1137     if (stm32_port->fifoen) {
1138         if (stm32_port->txftcfg >= 0)
1139             cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1140         if (stm32_port->rxftcfg >= 0)
1141             cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1142     }
1143 
1144     if (cflag & CSTOPB)
1145         cr2 |= USART_CR2_STOP_2B;
1146 
1147     bits = tty_get_char_size(cflag);
1148     stm32_port->rdr_mask = (BIT(bits) - 1);
1149 
1150     if (cflag & PARENB) {
1151         bits++;
1152         cr1 |= USART_CR1_PCE;
1153     }
1154 
1155     /*
1156      * Word length configuration:
1157      * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
1158      * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
1159      * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1160      * M0 and M1 already cleared by cr1 initialization.
1161      */
1162     if (bits == 9) {
1163         cr1 |= USART_CR1_M0;
1164     } else if ((bits == 7) && cfg->has_7bits_data) {
1165         cr1 |= USART_CR1_M1;
1166     } else if (bits != 8) {
1167         dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1168             , bits);
1169         cflag &= ~CSIZE;
1170         cflag |= CS8;
1171         termios->c_cflag = cflag;
1172         bits = 8;
1173         if (cflag & PARENB) {
1174             bits++;
1175             cr1 |= USART_CR1_M0;
1176         }
1177     }
1178 
1179     if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1180                        (stm32_port->fifoen &&
1181                     stm32_port->rxftcfg >= 0))) {
1182         if (cflag & CSTOPB)
1183             bits = bits + 3; /* 1 start bit + 2 stop bits */
1184         else
1185             bits = bits + 2; /* 1 start bit + 1 stop bit */
1186 
1187         /* RX timeout irq to occur after last stop bit + bits */
1188         stm32_port->cr1_irq = USART_CR1_RTOIE;
1189         writel_relaxed(bits, port->membase + ofs->rtor);
1190         cr2 |= USART_CR2_RTOEN;
1191         /*
1192          * Enable fifo threshold irq in two cases, either when there is no DMA, or when
1193          * wake up over usart, from low power until the DMA gets re-enabled by resume.
1194          */
1195         stm32_port->cr3_irq =  USART_CR3_RXFTIE;
1196     }
1197 
1198     cr1 |= stm32_port->cr1_irq;
1199     cr3 |= stm32_port->cr3_irq;
1200 
1201     if (cflag & PARODD)
1202         cr1 |= USART_CR1_PS;
1203 
1204     port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1205     if (cflag & CRTSCTS) {
1206         port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1207         cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
1208     }
1209 
1210     usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
1211 
1212     /*
1213      * The USART supports 16 or 8 times oversampling.
1214      * By default we prefer 16 times oversampling, so that the receiver
1215      * has a better tolerance to clock deviations.
1216      * 8 times oversampling is only used to achieve higher speeds.
1217      */
1218     if (usartdiv < 16) {
1219         oversampling = 8;
1220         cr1 |= USART_CR1_OVER8;
1221         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1222     } else {
1223         oversampling = 16;
1224         cr1 &= ~USART_CR1_OVER8;
1225         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1226     }
1227 
1228     mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
1229     fraction = usartdiv % oversampling;
1230     writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
1231 
1232     uart_update_timeout(port, cflag, baud);
1233 
1234     port->read_status_mask = USART_SR_ORE;
1235     if (termios->c_iflag & INPCK)
1236         port->read_status_mask |= USART_SR_PE | USART_SR_FE;
1237     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1238         port->read_status_mask |= USART_SR_FE;
1239 
1240     /* Characters to ignore */
1241     port->ignore_status_mask = 0;
1242     if (termios->c_iflag & IGNPAR)
1243         port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
1244     if (termios->c_iflag & IGNBRK) {
1245         port->ignore_status_mask |= USART_SR_FE;
1246         /*
1247          * If we're ignoring parity and break indicators,
1248          * ignore overruns too (for real raw support).
1249          */
1250         if (termios->c_iflag & IGNPAR)
1251             port->ignore_status_mask |= USART_SR_ORE;
1252     }
1253 
1254     /* Ignore all characters if CREAD is not set */
1255     if ((termios->c_cflag & CREAD) == 0)
1256         port->ignore_status_mask |= USART_SR_DUMMY_RX;
1257 
1258     if (stm32_port->rx_ch) {
1259         /*
1260          * Setup DMA to collect only valid data and enable error irqs.
1261          * This also enables break reception when using DMA.
1262          */
1263         cr1 |= USART_CR1_PEIE;
1264         cr3 |= USART_CR3_EIE;
1265         cr3 |= USART_CR3_DMAR;
1266         cr3 |= USART_CR3_DDRE;
1267     }
1268 
1269     if (rs485conf->flags & SER_RS485_ENABLED) {
1270         stm32_usart_config_reg_rs485(&cr1, &cr3,
1271                          rs485conf->delay_rts_before_send,
1272                          rs485conf->delay_rts_after_send,
1273                          baud);
1274         if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1275             cr3 &= ~USART_CR3_DEP;
1276             rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1277         } else {
1278             cr3 |= USART_CR3_DEP;
1279             rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1280         }
1281 
1282     } else {
1283         cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
1284         cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1285     }
1286 
1287     /* Configure wake up from low power on start bit detection */
1288     if (stm32_port->wakeup_src) {
1289         cr3 &= ~USART_CR3_WUS_MASK;
1290         cr3 |= USART_CR3_WUS_START_BIT;
1291     }
1292 
1293     writel_relaxed(cr3, port->membase + ofs->cr3);
1294     writel_relaxed(cr2, port->membase + ofs->cr2);
1295     writel_relaxed(cr1, port->membase + ofs->cr1);
1296 
1297     stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1298     spin_unlock_irqrestore(&port->lock, flags);
1299 
1300     /* Handle modem control interrupts */
1301     if (UART_ENABLE_MS(port, termios->c_cflag))
1302         stm32_usart_enable_ms(port);
1303     else
1304         stm32_usart_disable_ms(port);
1305 }
1306 
1307 static const char *stm32_usart_type(struct uart_port *port)
1308 {
1309     return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
1310 }
1311 
1312 static void stm32_usart_release_port(struct uart_port *port)
1313 {
1314 }
1315 
1316 static int stm32_usart_request_port(struct uart_port *port)
1317 {
1318     return 0;
1319 }
1320 
1321 static void stm32_usart_config_port(struct uart_port *port, int flags)
1322 {
1323     if (flags & UART_CONFIG_TYPE)
1324         port->type = PORT_STM32;
1325 }
1326 
1327 static int
1328 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
1329 {
1330     /* No user changeable parameters */
1331     return -EINVAL;
1332 }
1333 
1334 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
1335                unsigned int oldstate)
1336 {
1337     struct stm32_port *stm32port = container_of(port,
1338             struct stm32_port, port);
1339     const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1340     const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1341     unsigned long flags;
1342 
1343     switch (state) {
1344     case UART_PM_STATE_ON:
1345         pm_runtime_get_sync(port->dev);
1346         break;
1347     case UART_PM_STATE_OFF:
1348         spin_lock_irqsave(&port->lock, flags);
1349         stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1350         spin_unlock_irqrestore(&port->lock, flags);
1351         pm_runtime_put_sync(port->dev);
1352         break;
1353     }
1354 }
1355 
1356 #if defined(CONFIG_CONSOLE_POLL)
1357 
1358  /* Callbacks for characters polling in debug context (i.e. KGDB). */
1359 static int stm32_usart_poll_init(struct uart_port *port)
1360 {
1361     struct stm32_port *stm32_port = to_stm32_port(port);
1362 
1363     return clk_prepare_enable(stm32_port->clk);
1364 }
1365 
1366 static int stm32_usart_poll_get_char(struct uart_port *port)
1367 {
1368     struct stm32_port *stm32_port = to_stm32_port(port);
1369     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1370 
1371     if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1372         return NO_POLL_CHAR;
1373 
1374     return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1375 }
1376 
1377 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
1378 {
1379     stm32_usart_console_putchar(port, ch);
1380 }
1381 #endif /* CONFIG_CONSOLE_POLL */
1382 
1383 static const struct uart_ops stm32_uart_ops = {
1384     .tx_empty   = stm32_usart_tx_empty,
1385     .set_mctrl  = stm32_usart_set_mctrl,
1386     .get_mctrl  = stm32_usart_get_mctrl,
1387     .stop_tx    = stm32_usart_stop_tx,
1388     .start_tx   = stm32_usart_start_tx,
1389     .throttle   = stm32_usart_throttle,
1390     .unthrottle = stm32_usart_unthrottle,
1391     .stop_rx    = stm32_usart_stop_rx,
1392     .enable_ms  = stm32_usart_enable_ms,
1393     .break_ctl  = stm32_usart_break_ctl,
1394     .startup    = stm32_usart_startup,
1395     .shutdown   = stm32_usart_shutdown,
1396     .flush_buffer   = stm32_usart_flush_buffer,
1397     .set_termios    = stm32_usart_set_termios,
1398     .pm     = stm32_usart_pm,
1399     .type       = stm32_usart_type,
1400     .release_port   = stm32_usart_release_port,
1401     .request_port   = stm32_usart_request_port,
1402     .config_port    = stm32_usart_config_port,
1403     .verify_port    = stm32_usart_verify_port,
1404 #if defined(CONFIG_CONSOLE_POLL)
1405     .poll_init      = stm32_usart_poll_init,
1406     .poll_get_char  = stm32_usart_poll_get_char,
1407     .poll_put_char  = stm32_usart_poll_put_char,
1408 #endif /* CONFIG_CONSOLE_POLL */
1409 };
1410 
1411 /*
1412  * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1413  * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case,
1414  * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE.
1415  * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1.
1416  */
1417 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
1418 
1419 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1420                   int *ftcfg)
1421 {
1422     u32 bytes, i;
1423 
1424     /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */
1425     if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1426         bytes = 8;
1427 
1428     for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1429         if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1430             break;
1431     if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1432         i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1433 
1434     dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1435         stm32h7_usart_fifo_thresh_cfg[i]);
1436 
1437     /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */
1438     if (i)
1439         *ftcfg = i - 1;
1440     else
1441         *ftcfg = -EINVAL;
1442 }
1443 
1444 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1445 {
1446     clk_disable_unprepare(stm32port->clk);
1447 }
1448 
1449 static const struct serial_rs485 stm32_rs485_supported = {
1450     .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1451          SER_RS485_RX_DURING_TX,
1452     .delay_rts_before_send = 1,
1453     .delay_rts_after_send = 1,
1454 };
1455 
1456 static int stm32_usart_init_port(struct stm32_port *stm32port,
1457                  struct platform_device *pdev)
1458 {
1459     struct uart_port *port = &stm32port->port;
1460     struct resource *res;
1461     int ret, irq;
1462 
1463     irq = platform_get_irq(pdev, 0);
1464     if (irq < 0)
1465         return irq;
1466 
1467     port->iotype    = UPIO_MEM;
1468     port->flags = UPF_BOOT_AUTOCONF;
1469     port->ops   = &stm32_uart_ops;
1470     port->dev   = &pdev->dev;
1471     port->fifosize  = stm32port->info->cfg.fifosize;
1472     port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1473     port->irq = irq;
1474     port->rs485_config = stm32_usart_config_rs485;
1475     port->rs485_supported = stm32_rs485_supported;
1476 
1477     ret = stm32_usart_init_rs485(port, pdev);
1478     if (ret)
1479         return ret;
1480 
1481     stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1482         of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1483 
1484     stm32port->swap = stm32port->info->cfg.has_swap &&
1485         of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1486 
1487     stm32port->fifoen = stm32port->info->cfg.has_fifo;
1488     if (stm32port->fifoen) {
1489         stm32_usart_get_ftcfg(pdev, "rx-threshold",
1490                       &stm32port->rxftcfg);
1491         stm32_usart_get_ftcfg(pdev, "tx-threshold",
1492                       &stm32port->txftcfg);
1493     }
1494 
1495     port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1496     if (IS_ERR(port->membase))
1497         return PTR_ERR(port->membase);
1498     port->mapbase = res->start;
1499 
1500     spin_lock_init(&port->lock);
1501 
1502     stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1503     if (IS_ERR(stm32port->clk))
1504         return PTR_ERR(stm32port->clk);
1505 
1506     /* Ensure that clk rate is correct by enabling the clk */
1507     ret = clk_prepare_enable(stm32port->clk);
1508     if (ret)
1509         return ret;
1510 
1511     stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1512     if (!stm32port->port.uartclk) {
1513         ret = -EINVAL;
1514         goto err_clk;
1515     }
1516 
1517     stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1518     if (IS_ERR(stm32port->gpios)) {
1519         ret = PTR_ERR(stm32port->gpios);
1520         goto err_clk;
1521     }
1522 
1523     /*
1524      * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1525      * properties should not be specified.
1526      */
1527     if (stm32port->hw_flow_control) {
1528         if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1529             mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1530             dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1531             ret = -EINVAL;
1532             goto err_clk;
1533         }
1534     }
1535 
1536     return ret;
1537 
1538 err_clk:
1539     clk_disable_unprepare(stm32port->clk);
1540 
1541     return ret;
1542 }
1543 
1544 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1545 {
1546     struct device_node *np = pdev->dev.of_node;
1547     int id;
1548 
1549     if (!np)
1550         return NULL;
1551 
1552     id = of_alias_get_id(np, "serial");
1553     if (id < 0) {
1554         dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1555         return NULL;
1556     }
1557 
1558     if (WARN_ON(id >= STM32_MAX_PORTS))
1559         return NULL;
1560 
1561     stm32_ports[id].hw_flow_control =
1562         of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1563         of_property_read_bool (np, "uart-has-rtscts");
1564     stm32_ports[id].port.line = id;
1565     stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1566     stm32_ports[id].cr3_irq = 0;
1567     stm32_ports[id].last_res = RX_BUF_L;
1568     return &stm32_ports[id];
1569 }
1570 
1571 #ifdef CONFIG_OF
1572 static const struct of_device_id stm32_match[] = {
1573     { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1574     { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1575     { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1576     {},
1577 };
1578 
1579 MODULE_DEVICE_TABLE(of, stm32_match);
1580 #endif
1581 
1582 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1583                      struct platform_device *pdev)
1584 {
1585     if (stm32port->rx_buf)
1586         dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1587                   stm32port->rx_dma_buf);
1588 }
1589 
1590 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1591                        struct platform_device *pdev)
1592 {
1593     const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1594     struct uart_port *port = &stm32port->port;
1595     struct device *dev = &pdev->dev;
1596     struct dma_slave_config config;
1597     int ret;
1598 
1599     /*
1600      * Using DMA and threaded handler for the console could lead to
1601      * deadlocks.
1602      */
1603     if (uart_console(port))
1604         return -ENODEV;
1605 
1606     stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1607                            &stm32port->rx_dma_buf,
1608                            GFP_KERNEL);
1609     if (!stm32port->rx_buf)
1610         return -ENOMEM;
1611 
1612     /* Configure DMA channel */
1613     memset(&config, 0, sizeof(config));
1614     config.src_addr = port->mapbase + ofs->rdr;
1615     config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1616 
1617     ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1618     if (ret < 0) {
1619         dev_err(dev, "rx dma channel config failed\n");
1620         stm32_usart_of_dma_rx_remove(stm32port, pdev);
1621         return ret;
1622     }
1623 
1624     return 0;
1625 }
1626 
1627 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1628                      struct platform_device *pdev)
1629 {
1630     if (stm32port->tx_buf)
1631         dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1632                   stm32port->tx_dma_buf);
1633 }
1634 
1635 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1636                        struct platform_device *pdev)
1637 {
1638     const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1639     struct uart_port *port = &stm32port->port;
1640     struct device *dev = &pdev->dev;
1641     struct dma_slave_config config;
1642     int ret;
1643 
1644     stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1645                            &stm32port->tx_dma_buf,
1646                            GFP_KERNEL);
1647     if (!stm32port->tx_buf)
1648         return -ENOMEM;
1649 
1650     /* Configure DMA channel */
1651     memset(&config, 0, sizeof(config));
1652     config.dst_addr = port->mapbase + ofs->tdr;
1653     config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1654 
1655     ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1656     if (ret < 0) {
1657         dev_err(dev, "tx dma channel config failed\n");
1658         stm32_usart_of_dma_tx_remove(stm32port, pdev);
1659         return ret;
1660     }
1661 
1662     return 0;
1663 }
1664 
1665 static int stm32_usart_serial_probe(struct platform_device *pdev)
1666 {
1667     struct stm32_port *stm32port;
1668     int ret;
1669 
1670     stm32port = stm32_usart_of_get_port(pdev);
1671     if (!stm32port)
1672         return -ENODEV;
1673 
1674     stm32port->info = of_device_get_match_data(&pdev->dev);
1675     if (!stm32port->info)
1676         return -EINVAL;
1677 
1678     ret = stm32_usart_init_port(stm32port, pdev);
1679     if (ret)
1680         return ret;
1681 
1682     if (stm32port->wakeup_src) {
1683         device_set_wakeup_capable(&pdev->dev, true);
1684         ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1685         if (ret)
1686             goto err_deinit_port;
1687     }
1688 
1689     stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1690     if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) {
1691         ret = -EPROBE_DEFER;
1692         goto err_wakeirq;
1693     }
1694     /* Fall back in interrupt mode for any non-deferral error */
1695     if (IS_ERR(stm32port->rx_ch))
1696         stm32port->rx_ch = NULL;
1697 
1698     stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1699     if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1700         ret = -EPROBE_DEFER;
1701         goto err_dma_rx;
1702     }
1703     /* Fall back in interrupt mode for any non-deferral error */
1704     if (IS_ERR(stm32port->tx_ch))
1705         stm32port->tx_ch = NULL;
1706 
1707     if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1708         /* Fall back in interrupt mode */
1709         dma_release_channel(stm32port->rx_ch);
1710         stm32port->rx_ch = NULL;
1711     }
1712 
1713     if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1714         /* Fall back in interrupt mode */
1715         dma_release_channel(stm32port->tx_ch);
1716         stm32port->tx_ch = NULL;
1717     }
1718 
1719     if (!stm32port->rx_ch)
1720         dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1721     if (!stm32port->tx_ch)
1722         dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1723 
1724     platform_set_drvdata(pdev, &stm32port->port);
1725 
1726     pm_runtime_get_noresume(&pdev->dev);
1727     pm_runtime_set_active(&pdev->dev);
1728     pm_runtime_enable(&pdev->dev);
1729 
1730     ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1731     if (ret)
1732         goto err_port;
1733 
1734     pm_runtime_put_sync(&pdev->dev);
1735 
1736     return 0;
1737 
1738 err_port:
1739     pm_runtime_disable(&pdev->dev);
1740     pm_runtime_set_suspended(&pdev->dev);
1741     pm_runtime_put_noidle(&pdev->dev);
1742 
1743     if (stm32port->tx_ch) {
1744         stm32_usart_of_dma_tx_remove(stm32port, pdev);
1745         dma_release_channel(stm32port->tx_ch);
1746     }
1747 
1748     if (stm32port->rx_ch)
1749         stm32_usart_of_dma_rx_remove(stm32port, pdev);
1750 
1751 err_dma_rx:
1752     if (stm32port->rx_ch)
1753         dma_release_channel(stm32port->rx_ch);
1754 
1755 err_wakeirq:
1756     if (stm32port->wakeup_src)
1757         dev_pm_clear_wake_irq(&pdev->dev);
1758 
1759 err_deinit_port:
1760     if (stm32port->wakeup_src)
1761         device_set_wakeup_capable(&pdev->dev, false);
1762 
1763     stm32_usart_deinit_port(stm32port);
1764 
1765     return ret;
1766 }
1767 
1768 static int stm32_usart_serial_remove(struct platform_device *pdev)
1769 {
1770     struct uart_port *port = platform_get_drvdata(pdev);
1771     struct stm32_port *stm32_port = to_stm32_port(port);
1772     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1773     int err;
1774     u32 cr3;
1775 
1776     pm_runtime_get_sync(&pdev->dev);
1777     err = uart_remove_one_port(&stm32_usart_driver, port);
1778     if (err)
1779         return(err);
1780 
1781     pm_runtime_disable(&pdev->dev);
1782     pm_runtime_set_suspended(&pdev->dev);
1783     pm_runtime_put_noidle(&pdev->dev);
1784 
1785     stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1786     cr3 = readl_relaxed(port->membase + ofs->cr3);
1787     cr3 &= ~USART_CR3_EIE;
1788     cr3 &= ~USART_CR3_DMAR;
1789     cr3 &= ~USART_CR3_DDRE;
1790     writel_relaxed(cr3, port->membase + ofs->cr3);
1791 
1792     if (stm32_port->tx_ch) {
1793         stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1794         dma_release_channel(stm32_port->tx_ch);
1795     }
1796 
1797     if (stm32_port->rx_ch) {
1798         stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1799         dma_release_channel(stm32_port->rx_ch);
1800     }
1801 
1802     stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1803 
1804     if (stm32_port->wakeup_src) {
1805         dev_pm_clear_wake_irq(&pdev->dev);
1806         device_init_wakeup(&pdev->dev, false);
1807     }
1808 
1809     stm32_usart_deinit_port(stm32_port);
1810 
1811     return 0;
1812 }
1813 
1814 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1815 {
1816     struct stm32_port *stm32_port = to_stm32_port(port);
1817     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1818     u32 isr;
1819     int ret;
1820 
1821     ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1822                         (isr & USART_SR_TXE), 100,
1823                         STM32_USART_TIMEOUT_USEC);
1824     if (ret != 0) {
1825         dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
1826         return;
1827     }
1828     writel_relaxed(ch, port->membase + ofs->tdr);
1829 }
1830 
1831 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1832 static void stm32_usart_console_write(struct console *co, const char *s,
1833                       unsigned int cnt)
1834 {
1835     struct uart_port *port = &stm32_ports[co->index].port;
1836     struct stm32_port *stm32_port = to_stm32_port(port);
1837     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1838     const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1839     unsigned long flags;
1840     u32 old_cr1, new_cr1;
1841     int locked = 1;
1842 
1843     if (oops_in_progress)
1844         locked = spin_trylock_irqsave(&port->lock, flags);
1845     else
1846         spin_lock_irqsave(&port->lock, flags);
1847 
1848     /* Save and disable interrupts, enable the transmitter */
1849     old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1850     new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1851     new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1852     writel_relaxed(new_cr1, port->membase + ofs->cr1);
1853 
1854     uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1855 
1856     /* Restore interrupt state */
1857     writel_relaxed(old_cr1, port->membase + ofs->cr1);
1858 
1859     if (locked)
1860         spin_unlock_irqrestore(&port->lock, flags);
1861 }
1862 
1863 static int stm32_usart_console_setup(struct console *co, char *options)
1864 {
1865     struct stm32_port *stm32port;
1866     int baud = 9600;
1867     int bits = 8;
1868     int parity = 'n';
1869     int flow = 'n';
1870 
1871     if (co->index >= STM32_MAX_PORTS)
1872         return -ENODEV;
1873 
1874     stm32port = &stm32_ports[co->index];
1875 
1876     /*
1877      * This driver does not support early console initialization
1878      * (use ARM early printk support instead), so we only expect
1879      * this to be called during the uart port registration when the
1880      * driver gets probed and the port should be mapped at that point.
1881      */
1882     if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1883         return -ENXIO;
1884 
1885     if (options)
1886         uart_parse_options(options, &baud, &parity, &bits, &flow);
1887 
1888     return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1889 }
1890 
1891 static struct console stm32_console = {
1892     .name       = STM32_SERIAL_NAME,
1893     .device     = uart_console_device,
1894     .write      = stm32_usart_console_write,
1895     .setup      = stm32_usart_console_setup,
1896     .flags      = CON_PRINTBUFFER,
1897     .index      = -1,
1898     .data       = &stm32_usart_driver,
1899 };
1900 
1901 #define STM32_SERIAL_CONSOLE (&stm32_console)
1902 
1903 #else
1904 #define STM32_SERIAL_CONSOLE NULL
1905 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1906 
1907 #ifdef CONFIG_SERIAL_EARLYCON
1908 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1909 {
1910     struct stm32_usart_info *info = port->private_data;
1911 
1912     while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
1913         cpu_relax();
1914 
1915     writel_relaxed(ch, port->membase + info->ofs.tdr);
1916 }
1917 
1918 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count)
1919 {
1920     struct earlycon_device *device = console->data;
1921     struct uart_port *port = &device->port;
1922 
1923     uart_console_write(port, s, count, early_stm32_usart_console_putchar);
1924 }
1925 
1926 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options)
1927 {
1928     if (!(device->port.membase || device->port.iobase))
1929         return -ENODEV;
1930     device->port.private_data = &stm32h7_info;
1931     device->con->write = early_stm32_serial_write;
1932     return 0;
1933 }
1934 
1935 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options)
1936 {
1937     if (!(device->port.membase || device->port.iobase))
1938         return -ENODEV;
1939     device->port.private_data = &stm32f7_info;
1940     device->con->write = early_stm32_serial_write;
1941     return 0;
1942 }
1943 
1944 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options)
1945 {
1946     if (!(device->port.membase || device->port.iobase))
1947         return -ENODEV;
1948     device->port.private_data = &stm32f4_info;
1949     device->con->write = early_stm32_serial_write;
1950     return 0;
1951 }
1952 
1953 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
1954 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
1955 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
1956 #endif /* CONFIG_SERIAL_EARLYCON */
1957 
1958 static struct uart_driver stm32_usart_driver = {
1959     .driver_name    = DRIVER_NAME,
1960     .dev_name   = STM32_SERIAL_NAME,
1961     .major      = 0,
1962     .minor      = 0,
1963     .nr     = STM32_MAX_PORTS,
1964     .cons       = STM32_SERIAL_CONSOLE,
1965 };
1966 
1967 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1968                                bool enable)
1969 {
1970     struct stm32_port *stm32_port = to_stm32_port(port);
1971     const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1972     struct tty_port *tport = &port->state->port;
1973     int ret;
1974     unsigned int size;
1975     unsigned long flags;
1976 
1977     if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
1978         return 0;
1979 
1980     /*
1981      * Enable low-power wake-up and wake-up irq if argument is set to
1982      * "enable", disable low-power wake-up and wake-up irq otherwise
1983      */
1984     if (enable) {
1985         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1986         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1987         mctrl_gpio_enable_irq_wake(stm32_port->gpios);
1988 
1989         /*
1990          * When DMA is used for reception, it must be disabled before
1991          * entering low-power mode and re-enabled when exiting from
1992          * low-power mode.
1993          */
1994         if (stm32_port->rx_ch) {
1995             spin_lock_irqsave(&port->lock, flags);
1996             /* Avoid race with RX IRQ when DMAR is cleared */
1997             stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1998             /* Poll data from DMA RX buffer if any */
1999             size = stm32_usart_receive_chars(port, true);
2000             dmaengine_terminate_async(stm32_port->rx_ch);
2001             uart_unlock_and_check_sysrq_irqrestore(port, flags);
2002             if (size)
2003                 tty_flip_buffer_push(tport);
2004         }
2005 
2006         /* Poll data from RX FIFO if any */
2007         stm32_usart_receive_chars(port, false);
2008     } else {
2009         if (stm32_port->rx_ch) {
2010             ret = stm32_usart_start_rx_dma_cyclic(port);
2011             if (ret)
2012                 return ret;
2013         }
2014         mctrl_gpio_disable_irq_wake(stm32_port->gpios);
2015         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
2016         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
2017     }
2018 
2019     return 0;
2020 }
2021 
2022 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
2023 {
2024     struct uart_port *port = dev_get_drvdata(dev);
2025     int ret;
2026 
2027     uart_suspend_port(&stm32_usart_driver, port);
2028 
2029     if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2030         ret = stm32_usart_serial_en_wakeup(port, true);
2031         if (ret)
2032             return ret;
2033     }
2034 
2035     /*
2036      * When "no_console_suspend" is enabled, keep the pinctrl default state
2037      * and rely on bootloader stage to restore this state upon resume.
2038      * Otherwise, apply the idle or sleep states depending on wakeup
2039      * capabilities.
2040      */
2041     if (console_suspend_enabled || !uart_console(port)) {
2042         if (device_may_wakeup(dev) || device_wakeup_path(dev))
2043             pinctrl_pm_select_idle_state(dev);
2044         else
2045             pinctrl_pm_select_sleep_state(dev);
2046     }
2047 
2048     return 0;
2049 }
2050 
2051 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
2052 {
2053     struct uart_port *port = dev_get_drvdata(dev);
2054     int ret;
2055 
2056     pinctrl_pm_select_default_state(dev);
2057 
2058     if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2059         ret = stm32_usart_serial_en_wakeup(port, false);
2060         if (ret)
2061             return ret;
2062     }
2063 
2064     return uart_resume_port(&stm32_usart_driver, port);
2065 }
2066 
2067 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
2068 {
2069     struct uart_port *port = dev_get_drvdata(dev);
2070     struct stm32_port *stm32port = container_of(port,
2071             struct stm32_port, port);
2072 
2073     clk_disable_unprepare(stm32port->clk);
2074 
2075     return 0;
2076 }
2077 
2078 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
2079 {
2080     struct uart_port *port = dev_get_drvdata(dev);
2081     struct stm32_port *stm32port = container_of(port,
2082             struct stm32_port, port);
2083 
2084     return clk_prepare_enable(stm32port->clk);
2085 }
2086 
2087 static const struct dev_pm_ops stm32_serial_pm_ops = {
2088     SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
2089                stm32_usart_runtime_resume, NULL)
2090     SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
2091                 stm32_usart_serial_resume)
2092 };
2093 
2094 static struct platform_driver stm32_serial_driver = {
2095     .probe      = stm32_usart_serial_probe,
2096     .remove     = stm32_usart_serial_remove,
2097     .driver = {
2098         .name   = DRIVER_NAME,
2099         .pm = &stm32_serial_pm_ops,
2100         .of_match_table = of_match_ptr(stm32_match),
2101     },
2102 };
2103 
2104 static int __init stm32_usart_init(void)
2105 {
2106     static char banner[] __initdata = "STM32 USART driver initialized";
2107     int ret;
2108 
2109     pr_info("%s\n", banner);
2110 
2111     ret = uart_register_driver(&stm32_usart_driver);
2112     if (ret)
2113         return ret;
2114 
2115     ret = platform_driver_register(&stm32_serial_driver);
2116     if (ret)
2117         uart_unregister_driver(&stm32_usart_driver);
2118 
2119     return ret;
2120 }
2121 
2122 static void __exit stm32_usart_exit(void)
2123 {
2124     platform_driver_unregister(&stm32_serial_driver);
2125     uart_unregister_driver(&stm32_usart_driver);
2126 }
2127 
2128 module_init(stm32_usart_init);
2129 module_exit(stm32_usart_exit);
2130 
2131 MODULE_ALIAS("platform:" DRIVER_NAME);
2132 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
2133 MODULE_LICENSE("GPL v2");
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