tty/serial/sh-sci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #include <linux/bitops.h>
0003 #include <linux/serial_core.h>
0004 #include <linux/io.h>
0005
0006 #define SCI_MAJOR       204
0007 #define SCI_MINOR_START     8
0008
0009
0010 /*
0011  * SCI register subset common for all port types.
0012  * Not all registers will exist on all parts.
0013  */
0014 enum {
0015     SCSMR,              /* Serial Mode Register */
0016     SCBRR,              /* Bit Rate Register */
0017     SCSCR,              /* Serial Control Register */
0018     SCxSR,              /* Serial Status Register */
0019     SCFCR,              /* FIFO Control Register */
0020     SCFDR,              /* FIFO Data Count Register */
0021     SCxTDR,             /* Transmit (FIFO) Data Register */
0022     SCxRDR,             /* Receive (FIFO) Data Register */
0023     SCLSR,              /* Line Status Register */
0024     SCTFDR,             /* Transmit FIFO Data Count Register */
0025     SCRFDR,             /* Receive FIFO Data Count Register */
0026     SCSPTR,             /* Serial Port Register */
0027     HSSRR,              /* Sampling Rate Register */
0028     SCPCR,              /* Serial Port Control Register */
0029     SCPDR,              /* Serial Port Data Register */
0030     SCDL,               /* BRG Frequency Division Register */
0031     SCCKS,              /* BRG Clock Select Register */
0032     HSRTRGR,            /* Rx FIFO Data Count Trigger Register */
0033     HSTTRGR,            /* Tx FIFO Data Count Trigger Register */
0034     SEMR,               /* Serial extended mode register */
0035
0036     SCIx_NR_REGS,
0037 };
0038
0039
0040 /* SCSMR (Serial Mode Register) */
0041 #define SCSMR_C_A   BIT(7)  /* Communication Mode */
0042 #define SCSMR_CSYNC BIT(7)  /*   - Clocked synchronous mode */
0043 #define SCSMR_ASYNC 0   /*   - Asynchronous mode */
0044 #define SCSMR_CHR   BIT(6)  /* 7-bit Character Length */
0045 #define SCSMR_PE    BIT(5)  /* Parity Enable */
0046 #define SCSMR_ODD   BIT(4)  /* Odd Parity */
0047 #define SCSMR_STOP  BIT(3)  /* Stop Bit Length */
0048 #define SCSMR_CKS   0x0003  /* Clock Select */
0049
0050 /* Serial Mode Register, SCIFA/SCIFB only bits */
0051 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
0052 #define SCSMR_SRC_MASK  0x0700  /* Sampling Control */
0053 #define SCSMR_SRC_16    0x0000  /* Sampling rate 1/16 */
0054 #define SCSMR_SRC_5 0x0100  /* Sampling rate 1/5 */
0055 #define SCSMR_SRC_7 0x0200  /* Sampling rate 1/7 */
0056 #define SCSMR_SRC_11    0x0300  /* Sampling rate 1/11 */
0057 #define SCSMR_SRC_13    0x0400  /* Sampling rate 1/13 */
0058 #define SCSMR_SRC_17    0x0500  /* Sampling rate 1/17 */
0059 #define SCSMR_SRC_19    0x0600  /* Sampling rate 1/19 */
0060 #define SCSMR_SRC_27    0x0700  /* Sampling rate 1/27 */
0061
0062 /* Serial Control Register, SCIFA/SCIFB only bits */
0063 #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
0064 #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
0065
0066 /* Serial Control Register, HSCIF-only bits */
0067 #define HSSCR_TOT_SHIFT 14
0068
0069 /* SCxSR (Serial Status Register) on SCI */
0070 #define SCI_TDRE    BIT(7)  /* Transmit Data Register Empty */
0071 #define SCI_RDRF    BIT(6)  /* Receive Data Register Full */
0072 #define SCI_ORER    BIT(5)  /* Overrun Error */
0073 #define SCI_FER     BIT(4)  /* Framing Error */
0074 #define SCI_PER     BIT(3)  /* Parity Error */
0075 #define SCI_TEND    BIT(2)  /* Transmit End */
0076 #define SCI_RESERVED    0x03    /* All reserved bits */
0077
0078 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
0079
0080 #define SCI_RDxF_CLEAR  (u32)(~(SCI_RESERVED | SCI_RDRF))
0081 #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
0082 #define SCI_TDxE_CLEAR  (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
0083 #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
0084
0085 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
0086 #define SCIF_ER     BIT(7)  /* Receive Error */
0087 #define SCIF_TEND   BIT(6)  /* Transmission End */
0088 #define SCIF_TDFE   BIT(5)  /* Transmit FIFO Data Empty */
0089 #define SCIF_BRK    BIT(4)  /* Break Detect */
0090 #define SCIF_FER    BIT(3)  /* Framing Error */
0091 #define SCIF_PER    BIT(2)  /* Parity Error */
0092 #define SCIF_RDF    BIT(1)  /* Receive FIFO Data Full */
0093 #define SCIF_DR     BIT(0)  /* Receive Data Ready */
0094 /* SCIF only (optional) */
0095 #define SCIF_PERC   0xf000  /* Number of Parity Errors */
0096 #define SCIF_FERC   0x0f00  /* Number of Framing Errors */
0097 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
0098 #define SCIFA_ORER  BIT(9)  /* Overrun Error */
0099
0100 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
0101
0102 #define SCIF_RDxF_CLEAR     (u32)(~(SCIF_DR | SCIF_RDF))
0103 #define SCIF_ERROR_CLEAR    (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
0104 #define SCIF_TDxE_CLEAR     (u32)(~(SCIF_TDFE))
0105 #define SCIF_BREAK_CLEAR    (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
0106
0107 /* SCFCR (FIFO Control Register) */
0108 #define SCFCR_RTRG1 BIT(7)  /* Receive FIFO Data Count Trigger */
0109 #define SCFCR_RTRG0 BIT(6)
0110 #define SCFCR_TTRG1 BIT(5)  /* Transmit FIFO Data Count Trigger */
0111 #define SCFCR_TTRG0 BIT(4)
0112 #define SCFCR_MCE   BIT(3)  /* Modem Control Enable */
0113 #define SCFCR_TFRST BIT(2)  /* Transmit FIFO Data Register Reset */
0114 #define SCFCR_RFRST BIT(1)  /* Receive FIFO Data Register Reset */
0115 #define SCFCR_LOOP  BIT(0)  /* Loopback Test */
0116
0117 /* SCLSR (Line Status Register) on (H)SCIF */
0118 #define SCLSR_TO    BIT(2)  /* Timeout */
0119 #define SCLSR_ORER  BIT(0)  /* Overrun Error */
0120
0121 /* SCSPTR (Serial Port Register), optional */
0122 #define SCSPTR_RTSIO    BIT(7)  /* Serial Port RTS# Pin Input/Output */
0123 #define SCSPTR_RTSDT    BIT(6)  /* Serial Port RTS# Pin Data */
0124 #define SCSPTR_CTSIO    BIT(5)  /* Serial Port CTS# Pin Input/Output */
0125 #define SCSPTR_CTSDT    BIT(4)  /* Serial Port CTS# Pin Data */
0126 #define SCSPTR_SCKIO    BIT(3)  /* Serial Port Clock Pin Input/Output */
0127 #define SCSPTR_SCKDT    BIT(2)  /* Serial Port Clock Pin Data */
0128 #define SCSPTR_SPB2IO   BIT(1)  /* Serial Port Break Input/Output */
0129 #define SCSPTR_SPB2DT   BIT(0)  /* Serial Port Break Data */
0130
0131 /* HSSRR HSCIF */
0132 #define HSCIF_SRE   BIT(15) /* Sampling Rate Register Enable */
0133 #define HSCIF_SRDE  BIT(14) /* Sampling Point Register Enable */
0134
0135 #define HSCIF_SRHP_SHIFT    8
0136 #define HSCIF_SRHP_MASK     0x0f00
0137
0138 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
0139 #define SCPCR_RTSC  BIT(4)  /* Serial Port RTS# Pin / Output Pin */
0140 #define SCPCR_CTSC  BIT(3)  /* Serial Port CTS# Pin / Input Pin */
0141 #define SCPCR_SCKC  BIT(2)  /* Serial Port SCK Pin / Output Pin */
0142 #define SCPCR_RXDC  BIT(1)  /* Serial Port RXD Pin / Input Pin */
0143 #define SCPCR_TXDC  BIT(0)  /* Serial Port TXD Pin / Output Pin */
0144
0145 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
0146 #define SCPDR_RTSD  BIT(4)  /* Serial Port RTS# Output Pin Data */
0147 #define SCPDR_CTSD  BIT(3)  /* Serial Port CTS# Input Pin Data */
0148 #define SCPDR_SCKD  BIT(2)  /* Serial Port SCK Output Pin Data */
0149 #define SCPDR_RXDD  BIT(1)  /* Serial Port RXD Input Pin Data */
0150 #define SCPDR_TXDD  BIT(0)  /* Serial Port TXD Output Pin Data */
0151
0152 /*
0153  * BRG Clock Select Register (Some SCIF and HSCIF)
0154  * The Baud Rate Generator for external clock can provide a clock source for
0155  * the sampling clock. It outputs either its frequency divided clock, or the
0156  * (undivided) (H)SCK external clock.
0157  */
0158 #define SCCKS_CKS   BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
0159 #define SCCKS_XIN   BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
0160
0161 #define SCxSR_TEND(port)    (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
0162 #define SCxSR_RDxF(port)    (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_DR | SCIF_RDF)
0163 #define SCxSR_TDxE(port)    (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
0164 #define SCxSR_FER(port)     (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
0165 #define SCxSR_PER(port)     (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
0166 #define SCxSR_BRK(port)     (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
0167
0168 #define SCxSR_ERRORS(port)  (to_sci_port(port)->params->error_mask)
0169
0170 #define SCxSR_RDxF_CLEAR(port) \
0171     (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
0172 #define SCxSR_ERROR_CLEAR(port) \
0173     (to_sci_port(port)->params->error_clear)
0174 #define SCxSR_TDxE_CLEAR(port) \
0175     (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
0176 #define SCxSR_BREAK_CLEAR(port) \
0177     (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)