tty/serial/sh-sci.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
0004  *
0005  *  Copyright (C) 2002 - 2011  Paul Mundt
0006  *  Copyright (C) 2015 Glider bvba
0007  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
0008  *
0009  * based off of the old drivers/char/sh-sci.c by:
0010  *
0011  *   Copyright (C) 1999, 2000  Niibe Yutaka
0012  *   Copyright (C) 2000  Sugioka Toshinobu
0013  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
0014  *   Modified to support SecureEdge. David McCullough (2002)
0015  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
0016  *   Removed SH7300 support (Jul 2007).
0017  */
0018 #undef DEBUG
0019
0020 #include <linux/clk.h>
0021 #include <linux/console.h>
0022 #include <linux/ctype.h>
0023 #include <linux/cpufreq.h>
0024 #include <linux/delay.h>
0025 #include <linux/dmaengine.h>
0026 #include <linux/dma-mapping.h>
0027 #include <linux/err.h>
0028 #include <linux/errno.h>
0029 #include <linux/init.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/ioport.h>
0032 #include <linux/ktime.h>
0033 #include <linux/major.h>
0034 #include <linux/module.h>
0035 #include <linux/mm.h>
0036 #include <linux/of.h>
0037 #include <linux/of_device.h>
0038 #include <linux/platform_device.h>
0039 #include <linux/pm_runtime.h>
0040 #include <linux/reset.h>
0041 #include <linux/scatterlist.h>
0042 #include <linux/serial.h>
0043 #include <linux/serial_sci.h>
0044 #include <linux/sh_dma.h>
0045 #include <linux/slab.h>
0046 #include <linux/string.h>
0047 #include <linux/sysrq.h>
0048 #include <linux/timer.h>
0049 #include <linux/tty.h>
0050 #include <linux/tty_flip.h>
0051
0052 #ifdef CONFIG_SUPERH
0053 #include <asm/sh_bios.h>
0054 #include <asm/platform_early.h>
0055 #endif
0056
0057 #include "serial_mctrl_gpio.h"
0058 #include "sh-sci.h"
0059
0060 /* Offsets into the sci_port->irqs array */
0061 enum {
0062     SCIx_ERI_IRQ,
0063     SCIx_RXI_IRQ,
0064     SCIx_TXI_IRQ,
0065     SCIx_BRI_IRQ,
0066     SCIx_DRI_IRQ,
0067     SCIx_TEI_IRQ,
0068     SCIx_NR_IRQS,
0069
0070     SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
0071 };
0072
0073 #define SCIx_IRQ_IS_MUXED(port)         \
0074     ((port)->irqs[SCIx_ERI_IRQ] ==  \
0075      (port)->irqs[SCIx_RXI_IRQ]) || \
0076     ((port)->irqs[SCIx_ERI_IRQ] &&  \
0077      ((port)->irqs[SCIx_RXI_IRQ] < 0))
0078
0079 enum SCI_CLKS {
0080     SCI_FCK,        /* Functional Clock */
0081     SCI_SCK,        /* Optional External Clock */
0082     SCI_BRG_INT,        /* Optional BRG Internal Clock Source */
0083     SCI_SCIF_CLK,       /* Optional BRG External Clock Source */
0084     SCI_NUM_CLKS
0085 };
0086
0087 /* Bit x set means sampling rate x + 1 is supported */
0088 #define SCI_SR(x)       BIT((x) - 1)
0089 #define SCI_SR_RANGE(x, y)  GENMASK((y) - 1, (x) - 1)
0090
0091 #define SCI_SR_SCIFAB       SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
0092                 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
0093                 SCI_SR(19) | SCI_SR(27)
0094
0095 #define min_sr(_port)       ffs((_port)->sampling_rate_mask)
0096 #define max_sr(_port)       fls((_port)->sampling_rate_mask)
0097
0098 /* Iterate over all supported sampling rates, from high to low */
0099 #define for_each_sr(_sr, _port)                     \
0100     for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)    \
0101         if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
0102
0103 struct plat_sci_reg {
0104     u8 offset, size;
0105 };
0106
0107 struct sci_port_params {
0108     const struct plat_sci_reg regs[SCIx_NR_REGS];
0109     unsigned int fifosize;
0110     unsigned int overrun_reg;
0111     unsigned int overrun_mask;
0112     unsigned int sampling_rate_mask;
0113     unsigned int error_mask;
0114     unsigned int error_clear;
0115 };
0116
0117 struct sci_port {
0118     struct uart_port    port;
0119
0120     /* Platform configuration */
0121     const struct sci_port_params *params;
0122     const struct plat_sci_port *cfg;
0123     unsigned int        sampling_rate_mask;
0124     resource_size_t     reg_size;
0125     struct mctrl_gpios  *gpios;
0126
0127     /* Clocks */
0128     struct clk      *clks[SCI_NUM_CLKS];
0129     unsigned long       clk_rates[SCI_NUM_CLKS];
0130
0131     int         irqs[SCIx_NR_IRQS];
0132     char            *irqstr[SCIx_NR_IRQS];
0133
0134     struct dma_chan         *chan_tx;
0135     struct dma_chan         *chan_rx;
0136
0137 #ifdef CONFIG_SERIAL_SH_SCI_DMA
0138     struct dma_chan         *chan_tx_saved;
0139     struct dma_chan         *chan_rx_saved;
0140     dma_cookie_t            cookie_tx;
0141     dma_cookie_t            cookie_rx[2];
0142     dma_cookie_t            active_rx;
0143     dma_addr_t          tx_dma_addr;
0144     unsigned int            tx_dma_len;
0145     struct scatterlist      sg_rx[2];
0146     void                *rx_buf[2];
0147     size_t              buf_len_rx;
0148     struct work_struct      work_tx;
0149     struct hrtimer          rx_timer;
0150     unsigned int            rx_timeout; /* microseconds */
0151 #endif
0152     unsigned int            rx_frame;
0153     int             rx_trigger;
0154     struct timer_list       rx_fifo_timer;
0155     int             rx_fifo_timeout;
0156     u16             hscif_tot;
0157
0158     bool has_rtscts;
0159     bool autorts;
0160 };
0161
0162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
0163
0164 static struct sci_port sci_ports[SCI_NPORTS];
0165 static unsigned long sci_ports_in_use;
0166 static struct uart_driver sci_uart_driver;
0167
0168 static inline struct sci_port *
0169 to_sci_port(struct uart_port *uart)
0170 {
0171     return container_of(uart, struct sci_port, port);
0172 }
0173
0174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
0175     /*
0176      * Common SCI definitions, dependent on the port's regshift
0177      * value.
0178      */
0179     [SCIx_SCI_REGTYPE] = {
0180         .regs = {
0181             [SCSMR]     = { 0x00,  8 },
0182             [SCBRR]     = { 0x01,  8 },
0183             [SCSCR]     = { 0x02,  8 },
0184             [SCxTDR]    = { 0x03,  8 },
0185             [SCxSR]     = { 0x04,  8 },
0186             [SCxRDR]    = { 0x05,  8 },
0187         },
0188         .fifosize = 1,
0189         .overrun_reg = SCxSR,
0190         .overrun_mask = SCI_ORER,
0191         .sampling_rate_mask = SCI_SR(32),
0192         .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
0193         .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
0194     },
0195
0196     /*
0197      * Common definitions for legacy IrDA ports.
0198      */
0199     [SCIx_IRDA_REGTYPE] = {
0200         .regs = {
0201             [SCSMR]     = { 0x00,  8 },
0202             [SCBRR]     = { 0x02,  8 },
0203             [SCSCR]     = { 0x04,  8 },
0204             [SCxTDR]    = { 0x06,  8 },
0205             [SCxSR]     = { 0x08, 16 },
0206             [SCxRDR]    = { 0x0a,  8 },
0207             [SCFCR]     = { 0x0c,  8 },
0208             [SCFDR]     = { 0x0e, 16 },
0209         },
0210         .fifosize = 1,
0211         .overrun_reg = SCxSR,
0212         .overrun_mask = SCI_ORER,
0213         .sampling_rate_mask = SCI_SR(32),
0214         .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
0215         .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
0216     },
0217
0218     /*
0219      * Common SCIFA definitions.
0220      */
0221     [SCIx_SCIFA_REGTYPE] = {
0222         .regs = {
0223             [SCSMR]     = { 0x00, 16 },
0224             [SCBRR]     = { 0x04,  8 },
0225             [SCSCR]     = { 0x08, 16 },
0226             [SCxTDR]    = { 0x20,  8 },
0227             [SCxSR]     = { 0x14, 16 },
0228             [SCxRDR]    = { 0x24,  8 },
0229             [SCFCR]     = { 0x18, 16 },
0230             [SCFDR]     = { 0x1c, 16 },
0231             [SCPCR]     = { 0x30, 16 },
0232             [SCPDR]     = { 0x34, 16 },
0233         },
0234         .fifosize = 64,
0235         .overrun_reg = SCxSR,
0236         .overrun_mask = SCIFA_ORER,
0237         .sampling_rate_mask = SCI_SR_SCIFAB,
0238         .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
0239         .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
0240     },
0241
0242     /*
0243      * Common SCIFB definitions.
0244      */
0245     [SCIx_SCIFB_REGTYPE] = {
0246         .regs = {
0247             [SCSMR]     = { 0x00, 16 },
0248             [SCBRR]     = { 0x04,  8 },
0249             [SCSCR]     = { 0x08, 16 },
0250             [SCxTDR]    = { 0x40,  8 },
0251             [SCxSR]     = { 0x14, 16 },
0252             [SCxRDR]    = { 0x60,  8 },
0253             [SCFCR]     = { 0x18, 16 },
0254             [SCTFDR]    = { 0x38, 16 },
0255             [SCRFDR]    = { 0x3c, 16 },
0256             [SCPCR]     = { 0x30, 16 },
0257             [SCPDR]     = { 0x34, 16 },
0258         },
0259         .fifosize = 256,
0260         .overrun_reg = SCxSR,
0261         .overrun_mask = SCIFA_ORER,
0262         .sampling_rate_mask = SCI_SR_SCIFAB,
0263         .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
0264         .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
0265     },
0266
0267     /*
0268      * Common SH-2(A) SCIF definitions for ports with FIFO data
0269      * count registers.
0270      */
0271     [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
0272         .regs = {
0273             [SCSMR]     = { 0x00, 16 },
0274             [SCBRR]     = { 0x04,  8 },
0275             [SCSCR]     = { 0x08, 16 },
0276             [SCxTDR]    = { 0x0c,  8 },
0277             [SCxSR]     = { 0x10, 16 },
0278             [SCxRDR]    = { 0x14,  8 },
0279             [SCFCR]     = { 0x18, 16 },
0280             [SCFDR]     = { 0x1c, 16 },
0281             [SCSPTR]    = { 0x20, 16 },
0282             [SCLSR]     = { 0x24, 16 },
0283         },
0284         .fifosize = 16,
0285         .overrun_reg = SCLSR,
0286         .overrun_mask = SCLSR_ORER,
0287         .sampling_rate_mask = SCI_SR(32),
0288         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0289         .error_clear = SCIF_ERROR_CLEAR,
0290     },
0291
0292     /*
0293      * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
0294      * It looks like a normal SCIF with FIFO data, but with a
0295      * compressed address space. Also, the break out of interrupts
0296      * are different: ERI/BRI, RXI, TXI, TEI, DRI.
0297      */
0298     [SCIx_RZ_SCIFA_REGTYPE] = {
0299         .regs = {
0300             [SCSMR]     = { 0x00, 16 },
0301             [SCBRR]     = { 0x02,  8 },
0302             [SCSCR]     = { 0x04, 16 },
0303             [SCxTDR]    = { 0x06,  8 },
0304             [SCxSR]     = { 0x08, 16 },
0305             [SCxRDR]    = { 0x0A,  8 },
0306             [SCFCR]     = { 0x0C, 16 },
0307             [SCFDR]     = { 0x0E, 16 },
0308             [SCSPTR]    = { 0x10, 16 },
0309             [SCLSR]     = { 0x12, 16 },
0310             [SEMR]      = { 0x14, 8 },
0311         },
0312         .fifosize = 16,
0313         .overrun_reg = SCLSR,
0314         .overrun_mask = SCLSR_ORER,
0315         .sampling_rate_mask = SCI_SR(32),
0316         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0317         .error_clear = SCIF_ERROR_CLEAR,
0318     },
0319
0320     /*
0321      * Common SH-3 SCIF definitions.
0322      */
0323     [SCIx_SH3_SCIF_REGTYPE] = {
0324         .regs = {
0325             [SCSMR]     = { 0x00,  8 },
0326             [SCBRR]     = { 0x02,  8 },
0327             [SCSCR]     = { 0x04,  8 },
0328             [SCxTDR]    = { 0x06,  8 },
0329             [SCxSR]     = { 0x08, 16 },
0330             [SCxRDR]    = { 0x0a,  8 },
0331             [SCFCR]     = { 0x0c,  8 },
0332             [SCFDR]     = { 0x0e, 16 },
0333         },
0334         .fifosize = 16,
0335         .overrun_reg = SCLSR,
0336         .overrun_mask = SCLSR_ORER,
0337         .sampling_rate_mask = SCI_SR(32),
0338         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0339         .error_clear = SCIF_ERROR_CLEAR,
0340     },
0341
0342     /*
0343      * Common SH-4(A) SCIF(B) definitions.
0344      */
0345     [SCIx_SH4_SCIF_REGTYPE] = {
0346         .regs = {
0347             [SCSMR]     = { 0x00, 16 },
0348             [SCBRR]     = { 0x04,  8 },
0349             [SCSCR]     = { 0x08, 16 },
0350             [SCxTDR]    = { 0x0c,  8 },
0351             [SCxSR]     = { 0x10, 16 },
0352             [SCxRDR]    = { 0x14,  8 },
0353             [SCFCR]     = { 0x18, 16 },
0354             [SCFDR]     = { 0x1c, 16 },
0355             [SCSPTR]    = { 0x20, 16 },
0356             [SCLSR]     = { 0x24, 16 },
0357         },
0358         .fifosize = 16,
0359         .overrun_reg = SCLSR,
0360         .overrun_mask = SCLSR_ORER,
0361         .sampling_rate_mask = SCI_SR(32),
0362         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0363         .error_clear = SCIF_ERROR_CLEAR,
0364     },
0365
0366     /*
0367      * Common SCIF definitions for ports with a Baud Rate Generator for
0368      * External Clock (BRG).
0369      */
0370     [SCIx_SH4_SCIF_BRG_REGTYPE] = {
0371         .regs = {
0372             [SCSMR]     = { 0x00, 16 },
0373             [SCBRR]     = { 0x04,  8 },
0374             [SCSCR]     = { 0x08, 16 },
0375             [SCxTDR]    = { 0x0c,  8 },
0376             [SCxSR]     = { 0x10, 16 },
0377             [SCxRDR]    = { 0x14,  8 },
0378             [SCFCR]     = { 0x18, 16 },
0379             [SCFDR]     = { 0x1c, 16 },
0380             [SCSPTR]    = { 0x20, 16 },
0381             [SCLSR]     = { 0x24, 16 },
0382             [SCDL]      = { 0x30, 16 },
0383             [SCCKS]     = { 0x34, 16 },
0384         },
0385         .fifosize = 16,
0386         .overrun_reg = SCLSR,
0387         .overrun_mask = SCLSR_ORER,
0388         .sampling_rate_mask = SCI_SR(32),
0389         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0390         .error_clear = SCIF_ERROR_CLEAR,
0391     },
0392
0393     /*
0394      * Common HSCIF definitions.
0395      */
0396     [SCIx_HSCIF_REGTYPE] = {
0397         .regs = {
0398             [SCSMR]     = { 0x00, 16 },
0399             [SCBRR]     = { 0x04,  8 },
0400             [SCSCR]     = { 0x08, 16 },
0401             [SCxTDR]    = { 0x0c,  8 },
0402             [SCxSR]     = { 0x10, 16 },
0403             [SCxRDR]    = { 0x14,  8 },
0404             [SCFCR]     = { 0x18, 16 },
0405             [SCFDR]     = { 0x1c, 16 },
0406             [SCSPTR]    = { 0x20, 16 },
0407             [SCLSR]     = { 0x24, 16 },
0408             [HSSRR]     = { 0x40, 16 },
0409             [SCDL]      = { 0x30, 16 },
0410             [SCCKS]     = { 0x34, 16 },
0411             [HSRTRGR]   = { 0x54, 16 },
0412             [HSTTRGR]   = { 0x58, 16 },
0413         },
0414         .fifosize = 128,
0415         .overrun_reg = SCLSR,
0416         .overrun_mask = SCLSR_ORER,
0417         .sampling_rate_mask = SCI_SR_RANGE(8, 32),
0418         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0419         .error_clear = SCIF_ERROR_CLEAR,
0420     },
0421
0422     /*
0423      * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
0424      * register.
0425      */
0426     [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
0427         .regs = {
0428             [SCSMR]     = { 0x00, 16 },
0429             [SCBRR]     = { 0x04,  8 },
0430             [SCSCR]     = { 0x08, 16 },
0431             [SCxTDR]    = { 0x0c,  8 },
0432             [SCxSR]     = { 0x10, 16 },
0433             [SCxRDR]    = { 0x14,  8 },
0434             [SCFCR]     = { 0x18, 16 },
0435             [SCFDR]     = { 0x1c, 16 },
0436             [SCLSR]     = { 0x24, 16 },
0437         },
0438         .fifosize = 16,
0439         .overrun_reg = SCLSR,
0440         .overrun_mask = SCLSR_ORER,
0441         .sampling_rate_mask = SCI_SR(32),
0442         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0443         .error_clear = SCIF_ERROR_CLEAR,
0444     },
0445
0446     /*
0447      * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
0448      * count registers.
0449      */
0450     [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
0451         .regs = {
0452             [SCSMR]     = { 0x00, 16 },
0453             [SCBRR]     = { 0x04,  8 },
0454             [SCSCR]     = { 0x08, 16 },
0455             [SCxTDR]    = { 0x0c,  8 },
0456             [SCxSR]     = { 0x10, 16 },
0457             [SCxRDR]    = { 0x14,  8 },
0458             [SCFCR]     = { 0x18, 16 },
0459             [SCFDR]     = { 0x1c, 16 },
0460             [SCTFDR]    = { 0x1c, 16 }, /* aliased to SCFDR */
0461             [SCRFDR]    = { 0x20, 16 },
0462             [SCSPTR]    = { 0x24, 16 },
0463             [SCLSR]     = { 0x28, 16 },
0464         },
0465         .fifosize = 16,
0466         .overrun_reg = SCLSR,
0467         .overrun_mask = SCLSR_ORER,
0468         .sampling_rate_mask = SCI_SR(32),
0469         .error_mask = SCIF_DEFAULT_ERROR_MASK,
0470         .error_clear = SCIF_ERROR_CLEAR,
0471     },
0472
0473     /*
0474      * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
0475      * registers.
0476      */
0477     [SCIx_SH7705_SCIF_REGTYPE] = {
0478         .regs = {
0479             [SCSMR]     = { 0x00, 16 },
0480             [SCBRR]     = { 0x04,  8 },
0481             [SCSCR]     = { 0x08, 16 },
0482             [SCxTDR]    = { 0x20,  8 },
0483             [SCxSR]     = { 0x14, 16 },
0484             [SCxRDR]    = { 0x24,  8 },
0485             [SCFCR]     = { 0x18, 16 },
0486             [SCFDR]     = { 0x1c, 16 },
0487         },
0488         .fifosize = 64,
0489         .overrun_reg = SCxSR,
0490         .overrun_mask = SCIFA_ORER,
0491         .sampling_rate_mask = SCI_SR(16),
0492         .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
0493         .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
0494     },
0495 };
0496
0497 #define sci_getreg(up, offset)      (&to_sci_port(up)->params->regs[offset])
0498
0499 /*
0500  * The "offset" here is rather misleading, in that it refers to an enum
0501  * value relative to the port mapping rather than the fixed offset
0502  * itself, which needs to be manually retrieved from the platform's
0503  * register map for the given port.
0504  */
0505 static unsigned int sci_serial_in(struct uart_port *p, int offset)
0506 {
0507     const struct plat_sci_reg *reg = sci_getreg(p, offset);
0508
0509     if (reg->size == 8)
0510         return ioread8(p->membase + (reg->offset << p->regshift));
0511     else if (reg->size == 16)
0512         return ioread16(p->membase + (reg->offset << p->regshift));
0513     else
0514         WARN(1, "Invalid register access\n");
0515
0516     return 0;
0517 }
0518
0519 static void sci_serial_out(struct uart_port *p, int offset, int value)
0520 {
0521     const struct plat_sci_reg *reg = sci_getreg(p, offset);
0522
0523     if (reg->size == 8)
0524         iowrite8(value, p->membase + (reg->offset << p->regshift));
0525     else if (reg->size == 16)
0526         iowrite16(value, p->membase + (reg->offset << p->regshift));
0527     else
0528         WARN(1, "Invalid register access\n");
0529 }
0530
0531 static void sci_port_enable(struct sci_port *sci_port)
0532 {
0533     unsigned int i;
0534
0535     if (!sci_port->port.dev)
0536         return;
0537
0538     pm_runtime_get_sync(sci_port->port.dev);
0539
0540     for (i = 0; i < SCI_NUM_CLKS; i++) {
0541         clk_prepare_enable(sci_port->clks[i]);
0542         sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
0543     }
0544     sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
0545 }
0546
0547 static void sci_port_disable(struct sci_port *sci_port)
0548 {
0549     unsigned int i;
0550
0551     if (!sci_port->port.dev)
0552         return;
0553
0554     for (i = SCI_NUM_CLKS; i-- > 0; )
0555         clk_disable_unprepare(sci_port->clks[i]);
0556
0557     pm_runtime_put_sync(sci_port->port.dev);
0558 }
0559
0560 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
0561 {
0562     /*
0563      * Not all ports (such as SCIFA) will support REIE. Rather than
0564      * special-casing the port type, we check the port initialization
0565      * IRQ enable mask to see whether the IRQ is desired at all. If
0566      * it's unset, it's logically inferred that there's no point in
0567      * testing for it.
0568      */
0569     return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
0570 }
0571
0572 static void sci_start_tx(struct uart_port *port)
0573 {
0574     struct sci_port *s = to_sci_port(port);
0575     unsigned short ctrl;
0576
0577 #ifdef CONFIG_SERIAL_SH_SCI_DMA
0578     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
0579         u16 new, scr = serial_port_in(port, SCSCR);
0580         if (s->chan_tx)
0581             new = scr | SCSCR_TDRQE;
0582         else
0583             new = scr & ~SCSCR_TDRQE;
0584         if (new != scr)
0585             serial_port_out(port, SCSCR, new);
0586     }
0587
0588     if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
0589         dma_submit_error(s->cookie_tx)) {
0590         s->cookie_tx = 0;
0591         schedule_work(&s->work_tx);
0592     }
0593 #endif
0594
0595     if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
0596         /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
0597         ctrl = serial_port_in(port, SCSCR);
0598         serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
0599     }
0600 }
0601
0602 static void sci_stop_tx(struct uart_port *port)
0603 {
0604     unsigned short ctrl;
0605
0606     /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
0607     ctrl = serial_port_in(port, SCSCR);
0608
0609     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
0610         ctrl &= ~SCSCR_TDRQE;
0611
0612     ctrl &= ~SCSCR_TIE;
0613
0614     serial_port_out(port, SCSCR, ctrl);
0615
0616 #ifdef CONFIG_SERIAL_SH_SCI_DMA
0617     if (to_sci_port(port)->chan_tx &&
0618         !dma_submit_error(to_sci_port(port)->cookie_tx)) {
0619         dmaengine_terminate_async(to_sci_port(port)->chan_tx);
0620         to_sci_port(port)->cookie_tx = -EINVAL;
0621     }
0622 #endif
0623 }
0624
0625 static void sci_start_rx(struct uart_port *port)
0626 {
0627     unsigned short ctrl;
0628
0629     ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
0630
0631     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
0632         ctrl &= ~SCSCR_RDRQE;
0633
0634     serial_port_out(port, SCSCR, ctrl);
0635 }
0636
0637 static void sci_stop_rx(struct uart_port *port)
0638 {
0639     unsigned short ctrl;
0640
0641     ctrl = serial_port_in(port, SCSCR);
0642
0643     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
0644         ctrl &= ~SCSCR_RDRQE;
0645
0646     ctrl &= ~port_rx_irq_mask(port);
0647
0648     serial_port_out(port, SCSCR, ctrl);
0649 }
0650
0651 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
0652 {
0653     if (port->type == PORT_SCI) {
0654         /* Just store the mask */
0655         serial_port_out(port, SCxSR, mask);
0656     } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
0657         /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
0658         /* Only clear the status bits we want to clear */
0659         serial_port_out(port, SCxSR,
0660                 serial_port_in(port, SCxSR) & mask);
0661     } else {
0662         /* Store the mask, clear parity/framing errors */
0663         serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
0664     }
0665 }
0666
0667 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
0668     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
0669
0670 #ifdef CONFIG_CONSOLE_POLL
0671 static int sci_poll_get_char(struct uart_port *port)
0672 {
0673     unsigned short status;
0674     int c;
0675
0676     do {
0677         status = serial_port_in(port, SCxSR);
0678         if (status & SCxSR_ERRORS(port)) {
0679             sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
0680             continue;
0681         }
0682         break;
0683     } while (1);
0684
0685     if (!(status & SCxSR_RDxF(port)))
0686         return NO_POLL_CHAR;
0687
0688     c = serial_port_in(port, SCxRDR);
0689
0690     /* Dummy read */
0691     serial_port_in(port, SCxSR);
0692     sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
0693
0694     return c;
0695 }
0696 #endif
0697
0698 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
0699 {
0700     unsigned short status;
0701
0702     do {
0703         status = serial_port_in(port, SCxSR);
0704     } while (!(status & SCxSR_TDxE(port)));
0705
0706     serial_port_out(port, SCxTDR, c);
0707     sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
0708 }
0709 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
0710       CONFIG_SERIAL_SH_SCI_EARLYCON */
0711
0712 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
0713 {
0714     struct sci_port *s = to_sci_port(port);
0715
0716     /*
0717      * Use port-specific handler if provided.
0718      */
0719     if (s->cfg->ops && s->cfg->ops->init_pins) {
0720         s->cfg->ops->init_pins(port, cflag);
0721         return;
0722     }
0723
0724     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
0725         u16 data = serial_port_in(port, SCPDR);
0726         u16 ctrl = serial_port_in(port, SCPCR);
0727
0728         /* Enable RXD and TXD pin functions */
0729         ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
0730         if (to_sci_port(port)->has_rtscts) {
0731             /* RTS# is output, active low, unless autorts */
0732             if (!(port->mctrl & TIOCM_RTS)) {
0733                 ctrl |= SCPCR_RTSC;
0734                 data |= SCPDR_RTSD;
0735             } else if (!s->autorts) {
0736                 ctrl |= SCPCR_RTSC;
0737                 data &= ~SCPDR_RTSD;
0738             } else {
0739                 /* Enable RTS# pin function */
0740                 ctrl &= ~SCPCR_RTSC;
0741             }
0742             /* Enable CTS# pin function */
0743             ctrl &= ~SCPCR_CTSC;
0744         }
0745         serial_port_out(port, SCPDR, data);
0746         serial_port_out(port, SCPCR, ctrl);
0747     } else if (sci_getreg(port, SCSPTR)->size) {
0748         u16 status = serial_port_in(port, SCSPTR);
0749
0750         /* RTS# is always output; and active low, unless autorts */
0751         status |= SCSPTR_RTSIO;
0752         if (!(port->mctrl & TIOCM_RTS))
0753             status |= SCSPTR_RTSDT;
0754         else if (!s->autorts)
0755             status &= ~SCSPTR_RTSDT;
0756         /* CTS# and SCK are inputs */
0757         status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
0758         serial_port_out(port, SCSPTR, status);
0759     }
0760 }
0761
0762 static int sci_txfill(struct uart_port *port)
0763 {
0764     struct sci_port *s = to_sci_port(port);
0765     unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
0766     const struct plat_sci_reg *reg;
0767
0768     reg = sci_getreg(port, SCTFDR);
0769     if (reg->size)
0770         return serial_port_in(port, SCTFDR) & fifo_mask;
0771
0772     reg = sci_getreg(port, SCFDR);
0773     if (reg->size)
0774         return serial_port_in(port, SCFDR) >> 8;
0775
0776     return !(serial_port_in(port, SCxSR) & SCI_TDRE);
0777 }
0778
0779 static int sci_txroom(struct uart_port *port)
0780 {
0781     return port->fifosize - sci_txfill(port);
0782 }
0783
0784 static int sci_rxfill(struct uart_port *port)
0785 {
0786     struct sci_port *s = to_sci_port(port);
0787     unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
0788     const struct plat_sci_reg *reg;
0789
0790     reg = sci_getreg(port, SCRFDR);
0791     if (reg->size)
0792         return serial_port_in(port, SCRFDR) & fifo_mask;
0793
0794     reg = sci_getreg(port, SCFDR);
0795     if (reg->size)
0796         return serial_port_in(port, SCFDR) & fifo_mask;
0797
0798     return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
0799 }
0800
0801 /* ********************************************************************** *
0802  *                   the interrupt related routines                       *
0803  * ********************************************************************** */
0804
0805 static void sci_transmit_chars(struct uart_port *port)
0806 {
0807     struct circ_buf *xmit = &port->state->xmit;
0808     unsigned int stopped = uart_tx_stopped(port);
0809     unsigned short status;
0810     unsigned short ctrl;
0811     int count;
0812
0813     status = serial_port_in(port, SCxSR);
0814     if (!(status & SCxSR_TDxE(port))) {
0815         ctrl = serial_port_in(port, SCSCR);
0816         if (uart_circ_empty(xmit))
0817             ctrl &= ~SCSCR_TIE;
0818         else
0819             ctrl |= SCSCR_TIE;
0820         serial_port_out(port, SCSCR, ctrl);
0821         return;
0822     }
0823
0824     count = sci_txroom(port);
0825
0826     do {
0827         unsigned char c;
0828
0829         if (port->x_char) {
0830             c = port->x_char;
0831             port->x_char = 0;
0832         } else if (!uart_circ_empty(xmit) && !stopped) {
0833             c = xmit->buf[xmit->tail];
0834             xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0835         } else {
0836             break;
0837         }
0838
0839         serial_port_out(port, SCxTDR, c);
0840
0841         port->icount.tx++;
0842     } while (--count > 0);
0843
0844     sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
0845
0846     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0847         uart_write_wakeup(port);
0848     if (uart_circ_empty(xmit))
0849         sci_stop_tx(port);
0850
0851 }
0852
0853 static void sci_receive_chars(struct uart_port *port)
0854 {
0855     struct tty_port *tport = &port->state->port;
0856     int i, count, copied = 0;
0857     unsigned short status;
0858     unsigned char flag;
0859
0860     status = serial_port_in(port, SCxSR);
0861     if (!(status & SCxSR_RDxF(port)))
0862         return;
0863
0864     while (1) {
0865         /* Don't copy more bytes than there is room for in the buffer */
0866         count = tty_buffer_request_room(tport, sci_rxfill(port));
0867
0868         /* If for any reason we can't copy more data, we're done! */
0869         if (count == 0)
0870             break;
0871
0872         if (port->type == PORT_SCI) {
0873             char c = serial_port_in(port, SCxRDR);
0874             if (uart_handle_sysrq_char(port, c))
0875                 count = 0;
0876             else
0877                 tty_insert_flip_char(tport, c, TTY_NORMAL);
0878         } else {
0879             for (i = 0; i < count; i++) {
0880                 char c;
0881
0882                 if (port->type == PORT_SCIF ||
0883                     port->type == PORT_HSCIF) {
0884                     status = serial_port_in(port, SCxSR);
0885                     c = serial_port_in(port, SCxRDR);
0886                 } else {
0887                     c = serial_port_in(port, SCxRDR);
0888                     status = serial_port_in(port, SCxSR);
0889                 }
0890                 if (uart_handle_sysrq_char(port, c)) {
0891                     count--; i--;
0892                     continue;
0893                 }
0894
0895                 /* Store data and status */
0896                 if (status & SCxSR_FER(port)) {
0897                     flag = TTY_FRAME;
0898                     port->icount.frame++;
0899                 } else if (status & SCxSR_PER(port)) {
0900                     flag = TTY_PARITY;
0901                     port->icount.parity++;
0902                 } else
0903                     flag = TTY_NORMAL;
0904
0905                 tty_insert_flip_char(tport, c, flag);
0906             }
0907         }
0908
0909         serial_port_in(port, SCxSR); /* dummy read */
0910         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
0911
0912         copied += count;
0913         port->icount.rx += count;
0914     }
0915
0916     if (copied) {
0917         /* Tell the rest of the system the news. New characters! */
0918         tty_flip_buffer_push(tport);
0919     } else {
0920         /* TTY buffers full; read from RX reg to prevent lockup */
0921         serial_port_in(port, SCxRDR);
0922         serial_port_in(port, SCxSR); /* dummy read */
0923         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
0924     }
0925 }
0926
0927 static int sci_handle_errors(struct uart_port *port)
0928 {
0929     int copied = 0;
0930     unsigned short status = serial_port_in(port, SCxSR);
0931     struct tty_port *tport = &port->state->port;
0932     struct sci_port *s = to_sci_port(port);
0933
0934     /* Handle overruns */
0935     if (status & s->params->overrun_mask) {
0936         port->icount.overrun++;
0937
0938         /* overrun error */
0939         if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
0940             copied++;
0941     }
0942
0943     if (status & SCxSR_FER(port)) {
0944         /* frame error */
0945         port->icount.frame++;
0946
0947         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
0948             copied++;
0949     }
0950
0951     if (status & SCxSR_PER(port)) {
0952         /* parity error */
0953         port->icount.parity++;
0954
0955         if (tty_insert_flip_char(tport, 0, TTY_PARITY))
0956             copied++;
0957     }
0958
0959     if (copied)
0960         tty_flip_buffer_push(tport);
0961
0962     return copied;
0963 }
0964
0965 static int sci_handle_fifo_overrun(struct uart_port *port)
0966 {
0967     struct tty_port *tport = &port->state->port;
0968     struct sci_port *s = to_sci_port(port);
0969     const struct plat_sci_reg *reg;
0970     int copied = 0;
0971     u16 status;
0972
0973     reg = sci_getreg(port, s->params->overrun_reg);
0974     if (!reg->size)
0975         return 0;
0976
0977     status = serial_port_in(port, s->params->overrun_reg);
0978     if (status & s->params->overrun_mask) {
0979         status &= ~s->params->overrun_mask;
0980         serial_port_out(port, s->params->overrun_reg, status);
0981
0982         port->icount.overrun++;
0983
0984         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0985         tty_flip_buffer_push(tport);
0986         copied++;
0987     }
0988
0989     return copied;
0990 }
0991
0992 static int sci_handle_breaks(struct uart_port *port)
0993 {
0994     int copied = 0;
0995     unsigned short status = serial_port_in(port, SCxSR);
0996     struct tty_port *tport = &port->state->port;
0997
0998     if (uart_handle_break(port))
0999         return 0;
1000
1001     if (status & SCxSR_BRK(port)) {
1002         port->icount.brk++;
1003
1004         /* Notify of BREAK */
1005         if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1006             copied++;
1007     }
1008
1009     if (copied)
1010         tty_flip_buffer_push(tport);
1011
1012     copied += sci_handle_fifo_overrun(port);
1013
1014     return copied;
1015 }
1016
1017 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1018 {
1019     unsigned int bits;
1020
1021     if (rx_trig >= port->fifosize)
1022         rx_trig = port->fifosize - 1;
1023     if (rx_trig < 1)
1024         rx_trig = 1;
1025
1026     /* HSCIF can be set to an arbitrary level. */
1027     if (sci_getreg(port, HSRTRGR)->size) {
1028         serial_port_out(port, HSRTRGR, rx_trig);
1029         return rx_trig;
1030     }
1031
1032     switch (port->type) {
1033     case PORT_SCIF:
1034         if (rx_trig < 4) {
1035             bits = 0;
1036             rx_trig = 1;
1037         } else if (rx_trig < 8) {
1038             bits = SCFCR_RTRG0;
1039             rx_trig = 4;
1040         } else if (rx_trig < 14) {
1041             bits = SCFCR_RTRG1;
1042             rx_trig = 8;
1043         } else {
1044             bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1045             rx_trig = 14;
1046         }
1047         break;
1048     case PORT_SCIFA:
1049     case PORT_SCIFB:
1050         if (rx_trig < 16) {
1051             bits = 0;
1052             rx_trig = 1;
1053         } else if (rx_trig < 32) {
1054             bits = SCFCR_RTRG0;
1055             rx_trig = 16;
1056         } else if (rx_trig < 48) {
1057             bits = SCFCR_RTRG1;
1058             rx_trig = 32;
1059         } else {
1060             bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1061             rx_trig = 48;
1062         }
1063         break;
1064     default:
1065         WARN(1, "unknown FIFO configuration");
1066         return 1;
1067     }
1068
1069     serial_port_out(port, SCFCR,
1070         (serial_port_in(port, SCFCR) &
1071         ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1072
1073     return rx_trig;
1074 }
1075
1076 static int scif_rtrg_enabled(struct uart_port *port)
1077 {
1078     if (sci_getreg(port, HSRTRGR)->size)
1079         return serial_port_in(port, HSRTRGR) != 0;
1080     else
1081         return (serial_port_in(port, SCFCR) &
1082             (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1083 }
1084
1085 static void rx_fifo_timer_fn(struct timer_list *t)
1086 {
1087     struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1088     struct uart_port *port = &s->port;
1089
1090     dev_dbg(port->dev, "Rx timed out\n");
1091     scif_set_rtrg(port, 1);
1092 }
1093
1094 static ssize_t rx_fifo_trigger_show(struct device *dev,
1095                     struct device_attribute *attr, char *buf)
1096 {
1097     struct uart_port *port = dev_get_drvdata(dev);
1098     struct sci_port *sci = to_sci_port(port);
1099
1100     return sprintf(buf, "%d\n", sci->rx_trigger);
1101 }
1102
1103 static ssize_t rx_fifo_trigger_store(struct device *dev,
1104                      struct device_attribute *attr,
1105                      const char *buf, size_t count)
1106 {
1107     struct uart_port *port = dev_get_drvdata(dev);
1108     struct sci_port *sci = to_sci_port(port);
1109     int ret;
1110     long r;
1111
1112     ret = kstrtol(buf, 0, &r);
1113     if (ret)
1114         return ret;
1115
1116     sci->rx_trigger = scif_set_rtrg(port, r);
1117     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1118         scif_set_rtrg(port, 1);
1119
1120     return count;
1121 }
1122
1123 static DEVICE_ATTR_RW(rx_fifo_trigger);
1124
1125 static ssize_t rx_fifo_timeout_show(struct device *dev,
1126                    struct device_attribute *attr,
1127                    char *buf)
1128 {
1129     struct uart_port *port = dev_get_drvdata(dev);
1130     struct sci_port *sci = to_sci_port(port);
1131     int v;
1132
1133     if (port->type == PORT_HSCIF)
1134         v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1135     else
1136         v = sci->rx_fifo_timeout;
1137
1138     return sprintf(buf, "%d\n", v);
1139 }
1140
1141 static ssize_t rx_fifo_timeout_store(struct device *dev,
1142                 struct device_attribute *attr,
1143                 const char *buf,
1144                 size_t count)
1145 {
1146     struct uart_port *port = dev_get_drvdata(dev);
1147     struct sci_port *sci = to_sci_port(port);
1148     int ret;
1149     long r;
1150
1151     ret = kstrtol(buf, 0, &r);
1152     if (ret)
1153         return ret;
1154
1155     if (port->type == PORT_HSCIF) {
1156         if (r < 0 || r > 3)
1157             return -EINVAL;
1158         sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1159     } else {
1160         sci->rx_fifo_timeout = r;
1161         scif_set_rtrg(port, 1);
1162         if (r > 0)
1163             timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1164     }
1165
1166     return count;
1167 }
1168
1169 static DEVICE_ATTR_RW(rx_fifo_timeout);
1170
1171
1172 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1173 static void sci_dma_tx_complete(void *arg)
1174 {
1175     struct sci_port *s = arg;
1176     struct uart_port *port = &s->port;
1177     struct circ_buf *xmit = &port->state->xmit;
1178     unsigned long flags;
1179
1180     dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1181
1182     spin_lock_irqsave(&port->lock, flags);
1183
1184     xmit->tail += s->tx_dma_len;
1185     xmit->tail &= UART_XMIT_SIZE - 1;
1186
1187     port->icount.tx += s->tx_dma_len;
1188
1189     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1190         uart_write_wakeup(port);
1191
1192     if (!uart_circ_empty(xmit)) {
1193         s->cookie_tx = 0;
1194         schedule_work(&s->work_tx);
1195     } else {
1196         s->cookie_tx = -EINVAL;
1197         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1198             u16 ctrl = serial_port_in(port, SCSCR);
1199             serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1200         }
1201     }
1202
1203     spin_unlock_irqrestore(&port->lock, flags);
1204 }
1205
1206 /* Locking: called with port lock held */
1207 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1208 {
1209     struct uart_port *port = &s->port;
1210     struct tty_port *tport = &port->state->port;
1211     int copied;
1212
1213     copied = tty_insert_flip_string(tport, buf, count);
1214     if (copied < count)
1215         port->icount.buf_overrun++;
1216
1217     port->icount.rx += copied;
1218
1219     return copied;
1220 }
1221
1222 static int sci_dma_rx_find_active(struct sci_port *s)
1223 {
1224     unsigned int i;
1225
1226     for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1227         if (s->active_rx == s->cookie_rx[i])
1228             return i;
1229
1230     return -1;
1231 }
1232
1233 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1234 {
1235     unsigned int i;
1236
1237     s->chan_rx = NULL;
1238     for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1239         s->cookie_rx[i] = -EINVAL;
1240     s->active_rx = 0;
1241 }
1242
1243 static void sci_dma_rx_release(struct sci_port *s)
1244 {
1245     struct dma_chan *chan = s->chan_rx_saved;
1246
1247     s->chan_rx_saved = NULL;
1248     sci_dma_rx_chan_invalidate(s);
1249     dmaengine_terminate_sync(chan);
1250     dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1251               sg_dma_address(&s->sg_rx[0]));
1252     dma_release_channel(chan);
1253 }
1254
1255 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1256 {
1257     long sec = usec / 1000000;
1258     long nsec = (usec % 1000000) * 1000;
1259     ktime_t t = ktime_set(sec, nsec);
1260
1261     hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1262 }
1263
1264 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1265 {
1266     struct uart_port *port = &s->port;
1267     u16 scr;
1268
1269     /* Direct new serial port interrupts back to CPU */
1270     scr = serial_port_in(port, SCSCR);
1271     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1272         scr &= ~SCSCR_RDRQE;
1273         enable_irq(s->irqs[SCIx_RXI_IRQ]);
1274     }
1275     serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1276 }
1277
1278 static void sci_dma_rx_complete(void *arg)
1279 {
1280     struct sci_port *s = arg;
1281     struct dma_chan *chan = s->chan_rx;
1282     struct uart_port *port = &s->port;
1283     struct dma_async_tx_descriptor *desc;
1284     unsigned long flags;
1285     int active, count = 0;
1286
1287     dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1288         s->active_rx);
1289
1290     spin_lock_irqsave(&port->lock, flags);
1291
1292     active = sci_dma_rx_find_active(s);
1293     if (active >= 0)
1294         count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1295
1296     start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1297
1298     if (count)
1299         tty_flip_buffer_push(&port->state->port);
1300
1301     desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1302                        DMA_DEV_TO_MEM,
1303                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1304     if (!desc)
1305         goto fail;
1306
1307     desc->callback = sci_dma_rx_complete;
1308     desc->callback_param = s;
1309     s->cookie_rx[active] = dmaengine_submit(desc);
1310     if (dma_submit_error(s->cookie_rx[active]))
1311         goto fail;
1312
1313     s->active_rx = s->cookie_rx[!active];
1314
1315     dma_async_issue_pending(chan);
1316
1317     spin_unlock_irqrestore(&port->lock, flags);
1318     dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1319         __func__, s->cookie_rx[active], active, s->active_rx);
1320     return;
1321
1322 fail:
1323     spin_unlock_irqrestore(&port->lock, flags);
1324     dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1325     /* Switch to PIO */
1326     spin_lock_irqsave(&port->lock, flags);
1327     dmaengine_terminate_async(chan);
1328     sci_dma_rx_chan_invalidate(s);
1329     sci_dma_rx_reenable_irq(s);
1330     spin_unlock_irqrestore(&port->lock, flags);
1331 }
1332
1333 static void sci_dma_tx_release(struct sci_port *s)
1334 {
1335     struct dma_chan *chan = s->chan_tx_saved;
1336
1337     cancel_work_sync(&s->work_tx);
1338     s->chan_tx_saved = s->chan_tx = NULL;
1339     s->cookie_tx = -EINVAL;
1340     dmaengine_terminate_sync(chan);
1341     dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1342              DMA_TO_DEVICE);
1343     dma_release_channel(chan);
1344 }
1345
1346 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1347 {
1348     struct dma_chan *chan = s->chan_rx;
1349     struct uart_port *port = &s->port;
1350     unsigned long flags;
1351     int i;
1352
1353     for (i = 0; i < 2; i++) {
1354         struct scatterlist *sg = &s->sg_rx[i];
1355         struct dma_async_tx_descriptor *desc;
1356
1357         desc = dmaengine_prep_slave_sg(chan,
1358             sg, 1, DMA_DEV_TO_MEM,
1359             DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1360         if (!desc)
1361             goto fail;
1362
1363         desc->callback = sci_dma_rx_complete;
1364         desc->callback_param = s;
1365         s->cookie_rx[i] = dmaengine_submit(desc);
1366         if (dma_submit_error(s->cookie_rx[i]))
1367             goto fail;
1368
1369     }
1370
1371     s->active_rx = s->cookie_rx[0];
1372
1373     dma_async_issue_pending(chan);
1374     return 0;
1375
1376 fail:
1377     /* Switch to PIO */
1378     if (!port_lock_held)
1379         spin_lock_irqsave(&port->lock, flags);
1380     if (i)
1381         dmaengine_terminate_async(chan);
1382     sci_dma_rx_chan_invalidate(s);
1383     sci_start_rx(port);
1384     if (!port_lock_held)
1385         spin_unlock_irqrestore(&port->lock, flags);
1386     return -EAGAIN;
1387 }
1388
1389 static void sci_dma_tx_work_fn(struct work_struct *work)
1390 {
1391     struct sci_port *s = container_of(work, struct sci_port, work_tx);
1392     struct dma_async_tx_descriptor *desc;
1393     struct dma_chan *chan = s->chan_tx;
1394     struct uart_port *port = &s->port;
1395     struct circ_buf *xmit = &port->state->xmit;
1396     unsigned long flags;
1397     dma_addr_t buf;
1398     int head, tail;
1399
1400     /*
1401      * DMA is idle now.
1402      * Port xmit buffer is already mapped, and it is one page... Just adjust
1403      * offsets and lengths. Since it is a circular buffer, we have to
1404      * transmit till the end, and then the rest. Take the port lock to get a
1405      * consistent xmit buffer state.
1406      */
1407     spin_lock_irq(&port->lock);
1408     head = xmit->head;
1409     tail = xmit->tail;
1410     buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1411     s->tx_dma_len = min_t(unsigned int,
1412         CIRC_CNT(head, tail, UART_XMIT_SIZE),
1413         CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1414     if (!s->tx_dma_len) {
1415         /* Transmit buffer has been flushed */
1416         spin_unlock_irq(&port->lock);
1417         return;
1418     }
1419
1420     desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1421                        DMA_MEM_TO_DEV,
1422                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1423     if (!desc) {
1424         spin_unlock_irq(&port->lock);
1425         dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1426         goto switch_to_pio;
1427     }
1428
1429     dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1430                    DMA_TO_DEVICE);
1431
1432     desc->callback = sci_dma_tx_complete;
1433     desc->callback_param = s;
1434     s->cookie_tx = dmaengine_submit(desc);
1435     if (dma_submit_error(s->cookie_tx)) {
1436         spin_unlock_irq(&port->lock);
1437         dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1438         goto switch_to_pio;
1439     }
1440
1441     spin_unlock_irq(&port->lock);
1442     dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1443         __func__, xmit->buf, tail, head, s->cookie_tx);
1444
1445     dma_async_issue_pending(chan);
1446     return;
1447
1448 switch_to_pio:
1449     spin_lock_irqsave(&port->lock, flags);
1450     s->chan_tx = NULL;
1451     sci_start_tx(port);
1452     spin_unlock_irqrestore(&port->lock, flags);
1453     return;
1454 }
1455
1456 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1457 {
1458     struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1459     struct dma_chan *chan = s->chan_rx;
1460     struct uart_port *port = &s->port;
1461     struct dma_tx_state state;
1462     enum dma_status status;
1463     unsigned long flags;
1464     unsigned int read;
1465     int active, count;
1466
1467     dev_dbg(port->dev, "DMA Rx timed out\n");
1468
1469     spin_lock_irqsave(&port->lock, flags);
1470
1471     active = sci_dma_rx_find_active(s);
1472     if (active < 0) {
1473         spin_unlock_irqrestore(&port->lock, flags);
1474         return HRTIMER_NORESTART;
1475     }
1476
1477     status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1478     if (status == DMA_COMPLETE) {
1479         spin_unlock_irqrestore(&port->lock, flags);
1480         dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1481             s->active_rx, active);
1482
1483         /* Let packet complete handler take care of the packet */
1484         return HRTIMER_NORESTART;
1485     }
1486
1487     dmaengine_pause(chan);
1488
1489     /*
1490      * sometimes DMA transfer doesn't stop even if it is stopped and
1491      * data keeps on coming until transaction is complete so check
1492      * for DMA_COMPLETE again
1493      * Let packet complete handler take care of the packet
1494      */
1495     status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1496     if (status == DMA_COMPLETE) {
1497         spin_unlock_irqrestore(&port->lock, flags);
1498         dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1499         return HRTIMER_NORESTART;
1500     }
1501
1502     /* Handle incomplete DMA receive */
1503     dmaengine_terminate_async(s->chan_rx);
1504     read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1505
1506     if (read) {
1507         count = sci_dma_rx_push(s, s->rx_buf[active], read);
1508         if (count)
1509             tty_flip_buffer_push(&port->state->port);
1510     }
1511
1512     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1513         sci_dma_rx_submit(s, true);
1514
1515     sci_dma_rx_reenable_irq(s);
1516
1517     spin_unlock_irqrestore(&port->lock, flags);
1518
1519     return HRTIMER_NORESTART;
1520 }
1521
1522 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1523                          enum dma_transfer_direction dir)
1524 {
1525     struct dma_chan *chan;
1526     struct dma_slave_config cfg;
1527     int ret;
1528
1529     chan = dma_request_slave_channel(port->dev,
1530                      dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1531     if (!chan) {
1532         dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1533         return NULL;
1534     }
1535
1536     memset(&cfg, 0, sizeof(cfg));
1537     cfg.direction = dir;
1538     if (dir == DMA_MEM_TO_DEV) {
1539         cfg.dst_addr = port->mapbase +
1540             (sci_getreg(port, SCxTDR)->offset << port->regshift);
1541         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1542     } else {
1543         cfg.src_addr = port->mapbase +
1544             (sci_getreg(port, SCxRDR)->offset << port->regshift);
1545         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1546     }
1547
1548     ret = dmaengine_slave_config(chan, &cfg);
1549     if (ret) {
1550         dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1551         dma_release_channel(chan);
1552         return NULL;
1553     }
1554
1555     return chan;
1556 }
1557
1558 static void sci_request_dma(struct uart_port *port)
1559 {
1560     struct sci_port *s = to_sci_port(port);
1561     struct dma_chan *chan;
1562
1563     dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1564
1565     /*
1566      * DMA on console may interfere with Kernel log messages which use
1567      * plain putchar(). So, simply don't use it with a console.
1568      */
1569     if (uart_console(port))
1570         return;
1571
1572     if (!port->dev->of_node)
1573         return;
1574
1575     s->cookie_tx = -EINVAL;
1576
1577     /*
1578      * Don't request a dma channel if no channel was specified
1579      * in the device tree.
1580      */
1581     if (!of_find_property(port->dev->of_node, "dmas", NULL))
1582         return;
1583
1584     chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1585     dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1586     if (chan) {
1587         /* UART circular tx buffer is an aligned page. */
1588         s->tx_dma_addr = dma_map_single(chan->device->dev,
1589                         port->state->xmit.buf,
1590                         UART_XMIT_SIZE,
1591                         DMA_TO_DEVICE);
1592         if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1593             dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1594             dma_release_channel(chan);
1595         } else {
1596             dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1597                 __func__, UART_XMIT_SIZE,
1598                 port->state->xmit.buf, &s->tx_dma_addr);
1599
1600             INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1601             s->chan_tx_saved = s->chan_tx = chan;
1602         }
1603     }
1604
1605     chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1606     dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1607     if (chan) {
1608         unsigned int i;
1609         dma_addr_t dma;
1610         void *buf;
1611
1612         s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1613         buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1614                      &dma, GFP_KERNEL);
1615         if (!buf) {
1616             dev_warn(port->dev,
1617                  "Failed to allocate Rx dma buffer, using PIO\n");
1618             dma_release_channel(chan);
1619             return;
1620         }
1621
1622         for (i = 0; i < 2; i++) {
1623             struct scatterlist *sg = &s->sg_rx[i];
1624
1625             sg_init_table(sg, 1);
1626             s->rx_buf[i] = buf;
1627             sg_dma_address(sg) = dma;
1628             sg_dma_len(sg) = s->buf_len_rx;
1629
1630             buf += s->buf_len_rx;
1631             dma += s->buf_len_rx;
1632         }
1633
1634         hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1635         s->rx_timer.function = sci_dma_rx_timer_fn;
1636
1637         s->chan_rx_saved = s->chan_rx = chan;
1638
1639         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1640             sci_dma_rx_submit(s, false);
1641     }
1642 }
1643
1644 static void sci_free_dma(struct uart_port *port)
1645 {
1646     struct sci_port *s = to_sci_port(port);
1647
1648     if (s->chan_tx_saved)
1649         sci_dma_tx_release(s);
1650     if (s->chan_rx_saved)
1651         sci_dma_rx_release(s);
1652 }
1653
1654 static void sci_flush_buffer(struct uart_port *port)
1655 {
1656     struct sci_port *s = to_sci_port(port);
1657
1658     /*
1659      * In uart_flush_buffer(), the xmit circular buffer has just been
1660      * cleared, so we have to reset tx_dma_len accordingly, and stop any
1661      * pending transfers
1662      */
1663     s->tx_dma_len = 0;
1664     if (s->chan_tx) {
1665         dmaengine_terminate_async(s->chan_tx);
1666         s->cookie_tx = -EINVAL;
1667     }
1668 }
1669 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1670 static inline void sci_request_dma(struct uart_port *port)
1671 {
1672 }
1673
1674 static inline void sci_free_dma(struct uart_port *port)
1675 {
1676 }
1677
1678 #define sci_flush_buffer    NULL
1679 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1680
1681 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1682 {
1683     struct uart_port *port = ptr;
1684     struct sci_port *s = to_sci_port(port);
1685
1686 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1687     if (s->chan_rx) {
1688         u16 scr = serial_port_in(port, SCSCR);
1689         u16 ssr = serial_port_in(port, SCxSR);
1690
1691         /* Disable future Rx interrupts */
1692         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1693             disable_irq_nosync(irq);
1694             scr |= SCSCR_RDRQE;
1695         } else {
1696             if (sci_dma_rx_submit(s, false) < 0)
1697                 goto handle_pio;
1698
1699             scr &= ~SCSCR_RIE;
1700         }
1701         serial_port_out(port, SCSCR, scr);
1702         /* Clear current interrupt */
1703         serial_port_out(port, SCxSR,
1704                 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1705         dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1706             jiffies, s->rx_timeout);
1707         start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1708
1709         return IRQ_HANDLED;
1710     }
1711
1712 handle_pio:
1713 #endif
1714
1715     if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1716         if (!scif_rtrg_enabled(port))
1717             scif_set_rtrg(port, s->rx_trigger);
1718
1719         mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1720               s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1721     }
1722
1723     /* I think sci_receive_chars has to be called irrespective
1724      * of whether the I_IXOFF is set, otherwise, how is the interrupt
1725      * to be disabled?
1726      */
1727     sci_receive_chars(port);
1728
1729     return IRQ_HANDLED;
1730 }
1731
1732 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1733 {
1734     struct uart_port *port = ptr;
1735     unsigned long flags;
1736
1737     spin_lock_irqsave(&port->lock, flags);
1738     sci_transmit_chars(port);
1739     spin_unlock_irqrestore(&port->lock, flags);
1740
1741     return IRQ_HANDLED;
1742 }
1743
1744 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1745 {
1746     struct uart_port *port = ptr;
1747
1748     /* Handle BREAKs */
1749     sci_handle_breaks(port);
1750
1751     /* drop invalid character received before break was detected */
1752     serial_port_in(port, SCxRDR);
1753
1754     sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1755
1756     return IRQ_HANDLED;
1757 }
1758
1759 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1760 {
1761     struct uart_port *port = ptr;
1762     struct sci_port *s = to_sci_port(port);
1763
1764     if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1765         /* Break and Error interrupts are muxed */
1766         unsigned short ssr_status = serial_port_in(port, SCxSR);
1767
1768         /* Break Interrupt */
1769         if (ssr_status & SCxSR_BRK(port))
1770             sci_br_interrupt(irq, ptr);
1771
1772         /* Break only? */
1773         if (!(ssr_status & SCxSR_ERRORS(port)))
1774             return IRQ_HANDLED;
1775     }
1776
1777     /* Handle errors */
1778     if (port->type == PORT_SCI) {
1779         if (sci_handle_errors(port)) {
1780             /* discard character in rx buffer */
1781             serial_port_in(port, SCxSR);
1782             sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1783         }
1784     } else {
1785         sci_handle_fifo_overrun(port);
1786         if (!s->chan_rx)
1787             sci_receive_chars(port);
1788     }
1789
1790     sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1791
1792     /* Kick the transmission */
1793     if (!s->chan_tx)
1794         sci_tx_interrupt(irq, ptr);
1795
1796     return IRQ_HANDLED;
1797 }
1798
1799 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1800 {
1801     unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1802     struct uart_port *port = ptr;
1803     struct sci_port *s = to_sci_port(port);
1804     irqreturn_t ret = IRQ_NONE;
1805
1806     ssr_status = serial_port_in(port, SCxSR);
1807     scr_status = serial_port_in(port, SCSCR);
1808     if (s->params->overrun_reg == SCxSR)
1809         orer_status = ssr_status;
1810     else if (sci_getreg(port, s->params->overrun_reg)->size)
1811         orer_status = serial_port_in(port, s->params->overrun_reg);
1812
1813     err_enabled = scr_status & port_rx_irq_mask(port);
1814
1815     /* Tx Interrupt */
1816     if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1817         !s->chan_tx)
1818         ret = sci_tx_interrupt(irq, ptr);
1819
1820     /*
1821      * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1822      * DR flags
1823      */
1824     if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1825         (scr_status & SCSCR_RIE))
1826         ret = sci_rx_interrupt(irq, ptr);
1827
1828     /* Error Interrupt */
1829     if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1830         ret = sci_er_interrupt(irq, ptr);
1831
1832     /* Break Interrupt */
1833     if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1834         (ssr_status & SCxSR_BRK(port)) && err_enabled)
1835         ret = sci_br_interrupt(irq, ptr);
1836
1837     /* Overrun Interrupt */
1838     if (orer_status & s->params->overrun_mask) {
1839         sci_handle_fifo_overrun(port);
1840         ret = IRQ_HANDLED;
1841     }
1842
1843     return ret;
1844 }
1845
1846 static const struct sci_irq_desc {
1847     const char  *desc;
1848     irq_handler_t   handler;
1849 } sci_irq_desc[] = {
1850     /*
1851      * Split out handlers, the default case.
1852      */
1853     [SCIx_ERI_IRQ] = {
1854         .desc = "rx err",
1855         .handler = sci_er_interrupt,
1856     },
1857
1858     [SCIx_RXI_IRQ] = {
1859         .desc = "rx full",
1860         .handler = sci_rx_interrupt,
1861     },
1862
1863     [SCIx_TXI_IRQ] = {
1864         .desc = "tx empty",
1865         .handler = sci_tx_interrupt,
1866     },
1867
1868     [SCIx_BRI_IRQ] = {
1869         .desc = "break",
1870         .handler = sci_br_interrupt,
1871     },
1872
1873     [SCIx_DRI_IRQ] = {
1874         .desc = "rx ready",
1875         .handler = sci_rx_interrupt,
1876     },
1877
1878     [SCIx_TEI_IRQ] = {
1879         .desc = "tx end",
1880         .handler = sci_tx_interrupt,
1881     },
1882
1883     /*
1884      * Special muxed handler.
1885      */
1886     [SCIx_MUX_IRQ] = {
1887         .desc = "mux",
1888         .handler = sci_mpxed_interrupt,
1889     },
1890 };
1891
1892 static int sci_request_irq(struct sci_port *port)
1893 {
1894     struct uart_port *up = &port->port;
1895     int i, j, w, ret = 0;
1896
1897     for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1898         const struct sci_irq_desc *desc;
1899         int irq;
1900
1901         /* Check if already registered (muxed) */
1902         for (w = 0; w < i; w++)
1903             if (port->irqs[w] == port->irqs[i])
1904                 w = i + 1;
1905         if (w > i)
1906             continue;
1907
1908         if (SCIx_IRQ_IS_MUXED(port)) {
1909             i = SCIx_MUX_IRQ;
1910             irq = up->irq;
1911         } else {
1912             irq = port->irqs[i];
1913
1914             /*
1915              * Certain port types won't support all of the
1916              * available interrupt sources.
1917              */
1918             if (unlikely(irq < 0))
1919                 continue;
1920         }
1921
1922         desc = sci_irq_desc + i;
1923         port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1924                         dev_name(up->dev), desc->desc);
1925         if (!port->irqstr[j]) {
1926             ret = -ENOMEM;
1927             goto out_nomem;
1928         }
1929
1930         ret = request_irq(irq, desc->handler, up->irqflags,
1931                   port->irqstr[j], port);
1932         if (unlikely(ret)) {
1933             dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1934             goto out_noirq;
1935         }
1936     }
1937
1938     return 0;
1939
1940 out_noirq:
1941     while (--i >= 0)
1942         free_irq(port->irqs[i], port);
1943
1944 out_nomem:
1945     while (--j >= 0)
1946         kfree(port->irqstr[j]);
1947
1948     return ret;
1949 }
1950
1951 static void sci_free_irq(struct sci_port *port)
1952 {
1953     int i, j;
1954
1955     /*
1956      * Intentionally in reverse order so we iterate over the muxed
1957      * IRQ first.
1958      */
1959     for (i = 0; i < SCIx_NR_IRQS; i++) {
1960         int irq = port->irqs[i];
1961
1962         /*
1963          * Certain port types won't support all of the available
1964          * interrupt sources.
1965          */
1966         if (unlikely(irq < 0))
1967             continue;
1968
1969         /* Check if already freed (irq was muxed) */
1970         for (j = 0; j < i; j++)
1971             if (port->irqs[j] == irq)
1972                 j = i + 1;
1973         if (j > i)
1974             continue;
1975
1976         free_irq(port->irqs[i], port);
1977         kfree(port->irqstr[i]);
1978
1979         if (SCIx_IRQ_IS_MUXED(port)) {
1980             /* If there's only one IRQ, we're done. */
1981             return;
1982         }
1983     }
1984 }
1985
1986 static unsigned int sci_tx_empty(struct uart_port *port)
1987 {
1988     unsigned short status = serial_port_in(port, SCxSR);
1989     unsigned short in_tx_fifo = sci_txfill(port);
1990
1991     return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1992 }
1993
1994 static void sci_set_rts(struct uart_port *port, bool state)
1995 {
1996     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1997         u16 data = serial_port_in(port, SCPDR);
1998
1999         /* Active low */
2000         if (state)
2001             data &= ~SCPDR_RTSD;
2002         else
2003             data |= SCPDR_RTSD;
2004         serial_port_out(port, SCPDR, data);
2005
2006         /* RTS# is output */
2007         serial_port_out(port, SCPCR,
2008                 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2009     } else if (sci_getreg(port, SCSPTR)->size) {
2010         u16 ctrl = serial_port_in(port, SCSPTR);
2011
2012         /* Active low */
2013         if (state)
2014             ctrl &= ~SCSPTR_RTSDT;
2015         else
2016             ctrl |= SCSPTR_RTSDT;
2017         serial_port_out(port, SCSPTR, ctrl);
2018     }
2019 }
2020
2021 static bool sci_get_cts(struct uart_port *port)
2022 {
2023     if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2024         /* Active low */
2025         return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2026     } else if (sci_getreg(port, SCSPTR)->size) {
2027         /* Active low */
2028         return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2029     }
2030
2031     return true;
2032 }
2033
2034 /*
2035  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2036  * CTS/RTS is supported in hardware by at least one port and controlled
2037  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2038  * handled via the ->init_pins() op, which is a bit of a one-way street,
2039  * lacking any ability to defer pin control -- this will later be
2040  * converted over to the GPIO framework).
2041  *
2042  * Other modes (such as loopback) are supported generically on certain
2043  * port types, but not others. For these it's sufficient to test for the
2044  * existence of the support register and simply ignore the port type.
2045  */
2046 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2047 {
2048     struct sci_port *s = to_sci_port(port);
2049
2050     if (mctrl & TIOCM_LOOP) {
2051         const struct plat_sci_reg *reg;
2052
2053         /*
2054          * Standard loopback mode for SCFCR ports.
2055          */
2056         reg = sci_getreg(port, SCFCR);
2057         if (reg->size)
2058             serial_port_out(port, SCFCR,
2059                     serial_port_in(port, SCFCR) |
2060                     SCFCR_LOOP);
2061     }
2062
2063     mctrl_gpio_set(s->gpios, mctrl);
2064
2065     if (!s->has_rtscts)
2066         return;
2067
2068     if (!(mctrl & TIOCM_RTS)) {
2069         /* Disable Auto RTS */
2070         serial_port_out(port, SCFCR,
2071                 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2072
2073         /* Clear RTS */
2074         sci_set_rts(port, 0);
2075     } else if (s->autorts) {
2076         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2077             /* Enable RTS# pin function */
2078             serial_port_out(port, SCPCR,
2079                 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2080         }
2081
2082         /* Enable Auto RTS */
2083         serial_port_out(port, SCFCR,
2084                 serial_port_in(port, SCFCR) | SCFCR_MCE);
2085     } else {
2086         /* Set RTS */
2087         sci_set_rts(port, 1);
2088     }
2089 }
2090
2091 static unsigned int sci_get_mctrl(struct uart_port *port)
2092 {
2093     struct sci_port *s = to_sci_port(port);
2094     struct mctrl_gpios *gpios = s->gpios;
2095     unsigned int mctrl = 0;
2096
2097     mctrl_gpio_get(gpios, &mctrl);
2098
2099     /*
2100      * CTS/RTS is handled in hardware when supported, while nothing
2101      * else is wired up.
2102      */
2103     if (s->autorts) {
2104         if (sci_get_cts(port))
2105             mctrl |= TIOCM_CTS;
2106     } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2107         mctrl |= TIOCM_CTS;
2108     }
2109     if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2110         mctrl |= TIOCM_DSR;
2111     if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2112         mctrl |= TIOCM_CAR;
2113
2114     return mctrl;
2115 }
2116
2117 static void sci_enable_ms(struct uart_port *port)
2118 {
2119     mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2120 }
2121
2122 static void sci_break_ctl(struct uart_port *port, int break_state)
2123 {
2124     unsigned short scscr, scsptr;
2125     unsigned long flags;
2126
2127     /* check whether the port has SCSPTR */
2128     if (!sci_getreg(port, SCSPTR)->size) {
2129         /*
2130          * Not supported by hardware. Most parts couple break and rx
2131          * interrupts together, with break detection always enabled.
2132          */
2133         return;
2134     }
2135
2136     spin_lock_irqsave(&port->lock, flags);
2137     scsptr = serial_port_in(port, SCSPTR);
2138     scscr = serial_port_in(port, SCSCR);
2139
2140     if (break_state == -1) {
2141         scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2142         scscr &= ~SCSCR_TE;
2143     } else {
2144         scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2145         scscr |= SCSCR_TE;
2146     }
2147
2148     serial_port_out(port, SCSPTR, scsptr);
2149     serial_port_out(port, SCSCR, scscr);
2150     spin_unlock_irqrestore(&port->lock, flags);
2151 }
2152
2153 static int sci_startup(struct uart_port *port)
2154 {
2155     struct sci_port *s = to_sci_port(port);
2156     int ret;
2157
2158     dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2159
2160     sci_request_dma(port);
2161
2162     ret = sci_request_irq(s);
2163     if (unlikely(ret < 0)) {
2164         sci_free_dma(port);
2165         return ret;
2166     }
2167
2168     return 0;
2169 }
2170
2171 static void sci_shutdown(struct uart_port *port)
2172 {
2173     struct sci_port *s = to_sci_port(port);
2174     unsigned long flags;
2175     u16 scr;
2176
2177     dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2178
2179     s->autorts = false;
2180     mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2181
2182     spin_lock_irqsave(&port->lock, flags);
2183     sci_stop_rx(port);
2184     sci_stop_tx(port);
2185     /*
2186      * Stop RX and TX, disable related interrupts, keep clock source
2187      * and HSCIF TOT bits
2188      */
2189     scr = serial_port_in(port, SCSCR);
2190     serial_port_out(port, SCSCR, scr &
2191             (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2192     spin_unlock_irqrestore(&port->lock, flags);
2193
2194 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2195     if (s->chan_rx_saved) {
2196         dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2197             port->line);
2198         hrtimer_cancel(&s->rx_timer);
2199     }
2200 #endif
2201
2202     if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2203         del_timer_sync(&s->rx_fifo_timer);
2204     sci_free_irq(s);
2205     sci_free_dma(port);
2206 }
2207
2208 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2209             unsigned int *srr)
2210 {
2211     unsigned long freq = s->clk_rates[SCI_SCK];
2212     int err, min_err = INT_MAX;
2213     unsigned int sr;
2214
2215     if (s->port.type != PORT_HSCIF)
2216         freq *= 2;
2217
2218     for_each_sr(sr, s) {
2219         err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2220         if (abs(err) >= abs(min_err))
2221             continue;
2222
2223         min_err = err;
2224         *srr = sr - 1;
2225
2226         if (!err)
2227             break;
2228     }
2229
2230     dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2231         *srr + 1);
2232     return min_err;
2233 }
2234
2235 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2236             unsigned long freq, unsigned int *dlr,
2237             unsigned int *srr)
2238 {
2239     int err, min_err = INT_MAX;
2240     unsigned int sr, dl;
2241
2242     if (s->port.type != PORT_HSCIF)
2243         freq *= 2;
2244
2245     for_each_sr(sr, s) {
2246         dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2247         dl = clamp(dl, 1U, 65535U);
2248
2249         err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2250         if (abs(err) >= abs(min_err))
2251             continue;
2252
2253         min_err = err;
2254         *dlr = dl;
2255         *srr = sr - 1;
2256
2257         if (!err)
2258             break;
2259     }
2260
2261     dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2262         min_err, *dlr, *srr + 1);
2263     return min_err;
2264 }
2265
2266 /* calculate sample rate, BRR, and clock select */
2267 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2268               unsigned int *brr, unsigned int *srr,
2269               unsigned int *cks)
2270 {
2271     unsigned long freq = s->clk_rates[SCI_FCK];
2272     unsigned int sr, br, prediv, scrate, c;
2273     int err, min_err = INT_MAX;
2274
2275     if (s->port.type != PORT_HSCIF)
2276         freq *= 2;
2277
2278     /*
2279      * Find the combination of sample rate and clock select with the
2280      * smallest deviation from the desired baud rate.
2281      * Prefer high sample rates to maximise the receive margin.
2282      *
2283      * M: Receive margin (%)
2284      * N: Ratio of bit rate to clock (N = sampling rate)
2285      * D: Clock duty (D = 0 to 1.0)
2286      * L: Frame length (L = 9 to 12)
2287      * F: Absolute value of clock frequency deviation
2288      *
2289      *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2290      *      (|D - 0.5| / N * (1 + F))|
2291      *  NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2292      */
2293     for_each_sr(sr, s) {
2294         for (c = 0; c <= 3; c++) {
2295             /* integerized formulas from HSCIF documentation */
2296             prediv = sr << (2 * c + 1);
2297
2298             /*
2299              * We need to calculate:
2300              *
2301              *     br = freq / (prediv * bps) clamped to [1..256]
2302              *     err = freq / (br * prediv) - bps
2303              *
2304              * Watch out for overflow when calculating the desired
2305              * sampling clock rate!
2306              */
2307             if (bps > UINT_MAX / prediv)
2308                 break;
2309
2310             scrate = prediv * bps;
2311             br = DIV_ROUND_CLOSEST(freq, scrate);
2312             br = clamp(br, 1U, 256U);
2313
2314             err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2315             if (abs(err) >= abs(min_err))
2316                 continue;
2317
2318             min_err = err;
2319             *brr = br - 1;
2320             *srr = sr - 1;
2321             *cks = c;
2322
2323             if (!err)
2324                 goto found;
2325         }
2326     }
2327
2328 found:
2329     dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2330         min_err, *brr, *srr + 1, *cks);
2331     return min_err;
2332 }
2333
2334 static void sci_reset(struct uart_port *port)
2335 {
2336     const struct plat_sci_reg *reg;
2337     unsigned int status;
2338     struct sci_port *s = to_sci_port(port);
2339
2340     serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2341
2342     reg = sci_getreg(port, SCFCR);
2343     if (reg->size)
2344         serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2345
2346     sci_clear_SCxSR(port,
2347             SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2348             SCxSR_BREAK_CLEAR(port));
2349     if (sci_getreg(port, SCLSR)->size) {
2350         status = serial_port_in(port, SCLSR);
2351         status &= ~(SCLSR_TO | SCLSR_ORER);
2352         serial_port_out(port, SCLSR, status);
2353     }
2354
2355     if (s->rx_trigger > 1) {
2356         if (s->rx_fifo_timeout) {
2357             scif_set_rtrg(port, 1);
2358             timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2359         } else {
2360             if (port->type == PORT_SCIFA ||
2361                 port->type == PORT_SCIFB)
2362                 scif_set_rtrg(port, 1);
2363             else
2364                 scif_set_rtrg(port, s->rx_trigger);
2365         }
2366     }
2367 }
2368
2369 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2370                 struct ktermios *old)
2371 {
2372     unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2373     unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2374     unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2375     struct sci_port *s = to_sci_port(port);
2376     const struct plat_sci_reg *reg;
2377     int min_err = INT_MAX, err;
2378     unsigned long max_freq = 0;
2379     int best_clk = -1;
2380     unsigned long flags;
2381
2382     if ((termios->c_cflag & CSIZE) == CS7) {
2383         smr_val |= SCSMR_CHR;
2384     } else {
2385         termios->c_cflag &= ~CSIZE;
2386         termios->c_cflag |= CS8;
2387     }
2388     if (termios->c_cflag & PARENB)
2389         smr_val |= SCSMR_PE;
2390     if (termios->c_cflag & PARODD)
2391         smr_val |= SCSMR_PE | SCSMR_ODD;
2392     if (termios->c_cflag & CSTOPB)
2393         smr_val |= SCSMR_STOP;
2394
2395     /*
2396      * earlyprintk comes here early on with port->uartclk set to zero.
2397      * the clock framework is not up and running at this point so here
2398      * we assume that 115200 is the maximum baud rate. please note that
2399      * the baud rate is not programmed during earlyprintk - it is assumed
2400      * that the previous boot loader has enabled required clocks and
2401      * setup the baud rate generator hardware for us already.
2402      */
2403     if (!port->uartclk) {
2404         baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2405         goto done;
2406     }
2407
2408     for (i = 0; i < SCI_NUM_CLKS; i++)
2409         max_freq = max(max_freq, s->clk_rates[i]);
2410
2411     baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2412     if (!baud)
2413         goto done;
2414
2415     /*
2416      * There can be multiple sources for the sampling clock.  Find the one
2417      * that gives us the smallest deviation from the desired baud rate.
2418      */
2419
2420     /* Optional Undivided External Clock */
2421     if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2422         port->type != PORT_SCIFB) {
2423         err = sci_sck_calc(s, baud, &srr1);
2424         if (abs(err) < abs(min_err)) {
2425             best_clk = SCI_SCK;
2426             scr_val = SCSCR_CKE1;
2427             sccks = SCCKS_CKS;
2428             min_err = err;
2429             srr = srr1;
2430             if (!err)
2431                 goto done;
2432         }
2433     }
2434
2435     /* Optional BRG Frequency Divided External Clock */
2436     if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2437         err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2438                    &srr1);
2439         if (abs(err) < abs(min_err)) {
2440             best_clk = SCI_SCIF_CLK;
2441             scr_val = SCSCR_CKE1;
2442             sccks = 0;
2443             min_err = err;
2444             dl = dl1;
2445             srr = srr1;
2446             if (!err)
2447                 goto done;
2448         }
2449     }
2450
2451     /* Optional BRG Frequency Divided Internal Clock */
2452     if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2453         err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2454                    &srr1);
2455         if (abs(err) < abs(min_err)) {
2456             best_clk = SCI_BRG_INT;
2457             scr_val = SCSCR_CKE1;
2458             sccks = SCCKS_XIN;
2459             min_err = err;
2460             dl = dl1;
2461             srr = srr1;
2462             if (!min_err)
2463                 goto done;
2464         }
2465     }
2466
2467     /* Divided Functional Clock using standard Bit Rate Register */
2468     err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2469     if (abs(err) < abs(min_err)) {
2470         best_clk = SCI_FCK;
2471         scr_val = 0;
2472         min_err = err;
2473         brr = brr1;
2474         srr = srr1;
2475         cks = cks1;
2476     }
2477
2478 done:
2479     if (best_clk >= 0)
2480         dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2481             s->clks[best_clk], baud, min_err);
2482
2483     sci_port_enable(s);
2484
2485     /*
2486      * Program the optional External Baud Rate Generator (BRG) first.
2487      * It controls the mux to select (H)SCK or frequency divided clock.
2488      */
2489     if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2490         serial_port_out(port, SCDL, dl);
2491         serial_port_out(port, SCCKS, sccks);
2492     }
2493
2494     spin_lock_irqsave(&port->lock, flags);
2495
2496     sci_reset(port);
2497
2498     uart_update_timeout(port, termios->c_cflag, baud);
2499
2500     /* byte size and parity */
2501     bits = tty_get_frame_size(termios->c_cflag);
2502
2503     if (sci_getreg(port, SEMR)->size)
2504         serial_port_out(port, SEMR, 0);
2505
2506     if (best_clk >= 0) {
2507         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2508             switch (srr + 1) {
2509             case 5:  smr_val |= SCSMR_SRC_5;  break;
2510             case 7:  smr_val |= SCSMR_SRC_7;  break;
2511             case 11: smr_val |= SCSMR_SRC_11; break;
2512             case 13: smr_val |= SCSMR_SRC_13; break;
2513             case 16: smr_val |= SCSMR_SRC_16; break;
2514             case 17: smr_val |= SCSMR_SRC_17; break;
2515             case 19: smr_val |= SCSMR_SRC_19; break;
2516             case 27: smr_val |= SCSMR_SRC_27; break;
2517             }
2518         smr_val |= cks;
2519         serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2520         serial_port_out(port, SCSMR, smr_val);
2521         serial_port_out(port, SCBRR, brr);
2522         if (sci_getreg(port, HSSRR)->size) {
2523             unsigned int hssrr = srr | HSCIF_SRE;
2524             /* Calculate deviation from intended rate at the
2525              * center of the last stop bit in sampling clocks.
2526              */
2527             int last_stop = bits * 2 - 1;
2528             int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2529                               (int)(srr + 1),
2530                               2 * (int)baud);
2531
2532             if (abs(deviation) >= 2) {
2533                 /* At least two sampling clocks off at the
2534                  * last stop bit; we can increase the error
2535                  * margin by shifting the sampling point.
2536                  */
2537                 int shift = clamp(deviation / 2, -8, 7);
2538
2539                 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2540                      HSCIF_SRHP_MASK;
2541                 hssrr |= HSCIF_SRDE;
2542             }
2543             serial_port_out(port, HSSRR, hssrr);
2544         }
2545
2546         /* Wait one bit interval */
2547         udelay((1000000 + (baud - 1)) / baud);
2548     } else {
2549         /* Don't touch the bit rate configuration */
2550         scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2551         smr_val |= serial_port_in(port, SCSMR) &
2552                (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2553         serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2554         serial_port_out(port, SCSMR, smr_val);
2555     }
2556
2557     sci_init_pins(port, termios->c_cflag);
2558
2559     port->status &= ~UPSTAT_AUTOCTS;
2560     s->autorts = false;
2561     reg = sci_getreg(port, SCFCR);
2562     if (reg->size) {
2563         unsigned short ctrl = serial_port_in(port, SCFCR);
2564
2565         if ((port->flags & UPF_HARD_FLOW) &&
2566             (termios->c_cflag & CRTSCTS)) {
2567             /* There is no CTS interrupt to restart the hardware */
2568             port->status |= UPSTAT_AUTOCTS;
2569             /* MCE is enabled when RTS is raised */
2570             s->autorts = true;
2571         }
2572
2573         /*
2574          * As we've done a sci_reset() above, ensure we don't
2575          * interfere with the FIFOs while toggling MCE. As the
2576          * reset values could still be set, simply mask them out.
2577          */
2578         ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2579
2580         serial_port_out(port, SCFCR, ctrl);
2581     }
2582     if (port->flags & UPF_HARD_FLOW) {
2583         /* Refresh (Auto) RTS */
2584         sci_set_mctrl(port, port->mctrl);
2585     }
2586
2587     scr_val |= SCSCR_RE | SCSCR_TE |
2588            (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2589     serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2590     if ((srr + 1 == 5) &&
2591         (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2592         /*
2593          * In asynchronous mode, when the sampling rate is 1/5, first
2594          * received data may become invalid on some SCIFA and SCIFB.
2595          * To avoid this problem wait more than 1 serial data time (1
2596          * bit time x serial data number) after setting SCSCR.RE = 1.
2597          */
2598         udelay(DIV_ROUND_UP(10 * 1000000, baud));
2599     }
2600
2601     /* Calculate delay for 2 DMA buffers (4 FIFO). */
2602     s->rx_frame = (10000 * bits) / (baud / 100);
2603 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2604     s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2605 #endif
2606
2607     if ((termios->c_cflag & CREAD) != 0)
2608         sci_start_rx(port);
2609
2610     spin_unlock_irqrestore(&port->lock, flags);
2611
2612     sci_port_disable(s);
2613
2614     if (UART_ENABLE_MS(port, termios->c_cflag))
2615         sci_enable_ms(port);
2616 }
2617
2618 static void sci_pm(struct uart_port *port, unsigned int state,
2619            unsigned int oldstate)
2620 {
2621     struct sci_port *sci_port = to_sci_port(port);
2622
2623     switch (state) {
2624     case UART_PM_STATE_OFF:
2625         sci_port_disable(sci_port);
2626         break;
2627     default:
2628         sci_port_enable(sci_port);
2629         break;
2630     }
2631 }
2632
2633 static const char *sci_type(struct uart_port *port)
2634 {
2635     switch (port->type) {
2636     case PORT_IRDA:
2637         return "irda";
2638     case PORT_SCI:
2639         return "sci";
2640     case PORT_SCIF:
2641         return "scif";
2642     case PORT_SCIFA:
2643         return "scifa";
2644     case PORT_SCIFB:
2645         return "scifb";
2646     case PORT_HSCIF:
2647         return "hscif";
2648     }
2649
2650     return NULL;
2651 }
2652
2653 static int sci_remap_port(struct uart_port *port)
2654 {
2655     struct sci_port *sport = to_sci_port(port);
2656
2657     /*
2658      * Nothing to do if there's already an established membase.
2659      */
2660     if (port->membase)
2661         return 0;
2662
2663     if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2664         port->membase = ioremap(port->mapbase, sport->reg_size);
2665         if (unlikely(!port->membase)) {
2666             dev_err(port->dev, "can't remap port#%d\n", port->line);
2667             return -ENXIO;
2668         }
2669     } else {
2670         /*
2671          * For the simple (and majority of) cases where we don't
2672          * need to do any remapping, just cast the cookie
2673          * directly.
2674          */
2675         port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2676     }
2677
2678     return 0;
2679 }
2680
2681 static void sci_release_port(struct uart_port *port)
2682 {
2683     struct sci_port *sport = to_sci_port(port);
2684
2685     if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2686         iounmap(port->membase);
2687         port->membase = NULL;
2688     }
2689
2690     release_mem_region(port->mapbase, sport->reg_size);
2691 }
2692
2693 static int sci_request_port(struct uart_port *port)
2694 {
2695     struct resource *res;
2696     struct sci_port *sport = to_sci_port(port);
2697     int ret;
2698
2699     res = request_mem_region(port->mapbase, sport->reg_size,
2700                  dev_name(port->dev));
2701     if (unlikely(res == NULL)) {
2702         dev_err(port->dev, "request_mem_region failed.");
2703         return -EBUSY;
2704     }
2705
2706     ret = sci_remap_port(port);
2707     if (unlikely(ret != 0)) {
2708         release_resource(res);
2709         return ret;
2710     }
2711
2712     return 0;
2713 }
2714
2715 static void sci_config_port(struct uart_port *port, int flags)
2716 {
2717     if (flags & UART_CONFIG_TYPE) {
2718         struct sci_port *sport = to_sci_port(port);
2719
2720         port->type = sport->cfg->type;
2721         sci_request_port(port);
2722     }
2723 }
2724
2725 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2726 {
2727     if (ser->baud_base < 2400)
2728         /* No paper tape reader for Mitch.. */
2729         return -EINVAL;
2730
2731     return 0;
2732 }
2733
2734 static const struct uart_ops sci_uart_ops = {
2735     .tx_empty   = sci_tx_empty,
2736     .set_mctrl  = sci_set_mctrl,
2737     .get_mctrl  = sci_get_mctrl,
2738     .start_tx   = sci_start_tx,
2739     .stop_tx    = sci_stop_tx,
2740     .stop_rx    = sci_stop_rx,
2741     .enable_ms  = sci_enable_ms,
2742     .break_ctl  = sci_break_ctl,
2743     .startup    = sci_startup,
2744     .shutdown   = sci_shutdown,
2745     .flush_buffer   = sci_flush_buffer,
2746     .set_termios    = sci_set_termios,
2747     .pm     = sci_pm,
2748     .type       = sci_type,
2749     .release_port   = sci_release_port,
2750     .request_port   = sci_request_port,
2751     .config_port    = sci_config_port,
2752     .verify_port    = sci_verify_port,
2753 #ifdef CONFIG_CONSOLE_POLL
2754     .poll_get_char  = sci_poll_get_char,
2755     .poll_put_char  = sci_poll_put_char,
2756 #endif
2757 };
2758
2759 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2760 {
2761     const char *clk_names[] = {
2762         [SCI_FCK] = "fck",
2763         [SCI_SCK] = "sck",
2764         [SCI_BRG_INT] = "brg_int",
2765         [SCI_SCIF_CLK] = "scif_clk",
2766     };
2767     struct clk *clk;
2768     unsigned int i;
2769
2770     if (sci_port->cfg->type == PORT_HSCIF)
2771         clk_names[SCI_SCK] = "hsck";
2772
2773     for (i = 0; i < SCI_NUM_CLKS; i++) {
2774         clk = devm_clk_get_optional(dev, clk_names[i]);
2775         if (IS_ERR(clk))
2776             return PTR_ERR(clk);
2777
2778         if (!clk && i == SCI_FCK) {
2779             /*
2780              * Not all SH platforms declare a clock lookup entry
2781              * for SCI devices, in which case we need to get the
2782              * global "peripheral_clk" clock.
2783              */
2784             clk = devm_clk_get(dev, "peripheral_clk");
2785             if (IS_ERR(clk))
2786                 return dev_err_probe(dev, PTR_ERR(clk),
2787                              "failed to get %s\n",
2788                              clk_names[i]);
2789         }
2790
2791         if (!clk)
2792             dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2793         else
2794             dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2795                 clk, clk_get_rate(clk));
2796         sci_port->clks[i] = clk;
2797     }
2798     return 0;
2799 }
2800
2801 static const struct sci_port_params *
2802 sci_probe_regmap(const struct plat_sci_port *cfg)
2803 {
2804     unsigned int regtype;
2805
2806     if (cfg->regtype != SCIx_PROBE_REGTYPE)
2807         return &sci_port_params[cfg->regtype];
2808
2809     switch (cfg->type) {
2810     case PORT_SCI:
2811         regtype = SCIx_SCI_REGTYPE;
2812         break;
2813     case PORT_IRDA:
2814         regtype = SCIx_IRDA_REGTYPE;
2815         break;
2816     case PORT_SCIFA:
2817         regtype = SCIx_SCIFA_REGTYPE;
2818         break;
2819     case PORT_SCIFB:
2820         regtype = SCIx_SCIFB_REGTYPE;
2821         break;
2822     case PORT_SCIF:
2823         /*
2824          * The SH-4 is a bit of a misnomer here, although that's
2825          * where this particular port layout originated. This
2826          * configuration (or some slight variation thereof)
2827          * remains the dominant model for all SCIFs.
2828          */
2829         regtype = SCIx_SH4_SCIF_REGTYPE;
2830         break;
2831     case PORT_HSCIF:
2832         regtype = SCIx_HSCIF_REGTYPE;
2833         break;
2834     default:
2835         pr_err("Can't probe register map for given port\n");
2836         return NULL;
2837     }
2838
2839     return &sci_port_params[regtype];
2840 }
2841
2842 static int sci_init_single(struct platform_device *dev,
2843                struct sci_port *sci_port, unsigned int index,
2844                const struct plat_sci_port *p, bool early)
2845 {
2846     struct uart_port *port = &sci_port->port;
2847     const struct resource *res;
2848     unsigned int i;
2849     int ret;
2850
2851     sci_port->cfg   = p;
2852
2853     port->ops   = &sci_uart_ops;
2854     port->iotype    = UPIO_MEM;
2855     port->line  = index;
2856     port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2857
2858     res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2859     if (res == NULL)
2860         return -ENOMEM;
2861
2862     port->mapbase = res->start;
2863     sci_port->reg_size = resource_size(res);
2864
2865     for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2866         if (i)
2867             sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2868         else
2869             sci_port->irqs[i] = platform_get_irq(dev, i);
2870     }
2871
2872     /* The SCI generates several interrupts. They can be muxed together or
2873      * connected to different interrupt lines. In the muxed case only one
2874      * interrupt resource is specified as there is only one interrupt ID.
2875      * In the non-muxed case, up to 6 interrupt signals might be generated
2876      * from the SCI, however those signals might have their own individual
2877      * interrupt ID numbers, or muxed together with another interrupt.
2878      */
2879     if (sci_port->irqs[0] < 0)
2880         return -ENXIO;
2881
2882     if (sci_port->irqs[1] < 0)
2883         for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2884             sci_port->irqs[i] = sci_port->irqs[0];
2885
2886     sci_port->params = sci_probe_regmap(p);
2887     if (unlikely(sci_port->params == NULL))
2888         return -EINVAL;
2889
2890     switch (p->type) {
2891     case PORT_SCIFB:
2892         sci_port->rx_trigger = 48;
2893         break;
2894     case PORT_HSCIF:
2895         sci_port->rx_trigger = 64;
2896         break;
2897     case PORT_SCIFA:
2898         sci_port->rx_trigger = 32;
2899         break;
2900     case PORT_SCIF:
2901         if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2902             /* RX triggering not implemented for this IP */
2903             sci_port->rx_trigger = 1;
2904         else
2905             sci_port->rx_trigger = 8;
2906         break;
2907     default:
2908         sci_port->rx_trigger = 1;
2909         break;
2910     }
2911
2912     sci_port->rx_fifo_timeout = 0;
2913     sci_port->hscif_tot = 0;
2914
2915     /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2916      * match the SoC datasheet, this should be investigated. Let platform
2917      * data override the sampling rate for now.
2918      */
2919     sci_port->sampling_rate_mask = p->sampling_rate
2920                      ? SCI_SR(p->sampling_rate)
2921                      : sci_port->params->sampling_rate_mask;
2922
2923     if (!early) {
2924         ret = sci_init_clocks(sci_port, &dev->dev);
2925         if (ret < 0)
2926             return ret;
2927
2928         port->dev = &dev->dev;
2929
2930         pm_runtime_enable(&dev->dev);
2931     }
2932
2933     port->type      = p->type;
2934     port->flags     = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2935     port->fifosize      = sci_port->params->fifosize;
2936
2937     if (port->type == PORT_SCI) {
2938         if (sci_port->reg_size >= 0x20)
2939             port->regshift = 2;
2940         else
2941             port->regshift = 1;
2942     }
2943
2944     /*
2945      * The UART port needs an IRQ value, so we peg this to the RX IRQ
2946      * for the multi-IRQ ports, which is where we are primarily
2947      * concerned with the shutdown path synchronization.
2948      *
2949      * For the muxed case there's nothing more to do.
2950      */
2951     port->irq       = sci_port->irqs[SCIx_RXI_IRQ];
2952     port->irqflags      = 0;
2953
2954     port->serial_in     = sci_serial_in;
2955     port->serial_out    = sci_serial_out;
2956
2957     return 0;
2958 }
2959
2960 static void sci_cleanup_single(struct sci_port *port)
2961 {
2962     pm_runtime_disable(port->port.dev);
2963 }
2964
2965 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2966     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2967 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
2968 {
2969     sci_poll_put_char(port, ch);
2970 }
2971
2972 /*
2973  *  Print a string to the serial port trying not to disturb
2974  *  any possible real use of the port...
2975  */
2976 static void serial_console_write(struct console *co, const char *s,
2977                  unsigned count)
2978 {
2979     struct sci_port *sci_port = &sci_ports[co->index];
2980     struct uart_port *port = &sci_port->port;
2981     unsigned short bits, ctrl, ctrl_temp;
2982     unsigned long flags;
2983     int locked = 1;
2984
2985     if (port->sysrq)
2986         locked = 0;
2987     else if (oops_in_progress)
2988         locked = spin_trylock_irqsave(&port->lock, flags);
2989     else
2990         spin_lock_irqsave(&port->lock, flags);
2991
2992     /* first save SCSCR then disable interrupts, keep clock source */
2993     ctrl = serial_port_in(port, SCSCR);
2994     ctrl_temp = SCSCR_RE | SCSCR_TE |
2995             (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2996             (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2997     serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2998
2999     uart_console_write(port, s, count, serial_console_putchar);
3000
3001     /* wait until fifo is empty and last bit has been transmitted */
3002     bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3003     while ((serial_port_in(port, SCxSR) & bits) != bits)
3004         cpu_relax();
3005
3006     /* restore the SCSCR */
3007     serial_port_out(port, SCSCR, ctrl);
3008
3009     if (locked)
3010         spin_unlock_irqrestore(&port->lock, flags);
3011 }
3012
3013 static int serial_console_setup(struct console *co, char *options)
3014 {
3015     struct sci_port *sci_port;
3016     struct uart_port *port;
3017     int baud = 115200;
3018     int bits = 8;
3019     int parity = 'n';
3020     int flow = 'n';
3021     int ret;
3022
3023     /*
3024      * Refuse to handle any bogus ports.
3025      */
3026     if (co->index < 0 || co->index >= SCI_NPORTS)
3027         return -ENODEV;
3028
3029     sci_port = &sci_ports[co->index];
3030     port = &sci_port->port;
3031
3032     /*
3033      * Refuse to handle uninitialized ports.
3034      */
3035     if (!port->ops)
3036         return -ENODEV;
3037
3038     ret = sci_remap_port(port);
3039     if (unlikely(ret != 0))
3040         return ret;
3041
3042     if (options)
3043         uart_parse_options(options, &baud, &parity, &bits, &flow);
3044
3045     return uart_set_options(port, co, baud, parity, bits, flow);
3046 }
3047
3048 static struct console serial_console = {
3049     .name       = "ttySC",
3050     .device     = uart_console_device,
3051     .write      = serial_console_write,
3052     .setup      = serial_console_setup,
3053     .flags      = CON_PRINTBUFFER,
3054     .index      = -1,
3055     .data       = &sci_uart_driver,
3056 };
3057
3058 #ifdef CONFIG_SUPERH
3059 static struct console early_serial_console = {
3060     .name           = "early_ttySC",
3061     .write          = serial_console_write,
3062     .flags          = CON_PRINTBUFFER,
3063     .index      = -1,
3064 };
3065
3066 static char early_serial_buf[32];
3067
3068 static int sci_probe_earlyprintk(struct platform_device *pdev)
3069 {
3070     const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3071
3072     if (early_serial_console.data)
3073         return -EEXIST;
3074
3075     early_serial_console.index = pdev->id;
3076
3077     sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3078
3079     serial_console_setup(&early_serial_console, early_serial_buf);
3080
3081     if (!strstr(early_serial_buf, "keep"))
3082         early_serial_console.flags |= CON_BOOT;
3083
3084     register_console(&early_serial_console);
3085     return 0;
3086 }
3087 #endif
3088
3089 #define SCI_CONSOLE (&serial_console)
3090
3091 #else
3092 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3093 {
3094     return -EINVAL;
3095 }
3096
3097 #define SCI_CONSOLE NULL
3098
3099 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3100
3101 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3102
3103 static DEFINE_MUTEX(sci_uart_registration_lock);
3104 static struct uart_driver sci_uart_driver = {
3105     .owner      = THIS_MODULE,
3106     .driver_name    = "sci",
3107     .dev_name   = "ttySC",
3108     .major      = SCI_MAJOR,
3109     .minor      = SCI_MINOR_START,
3110     .nr     = SCI_NPORTS,
3111     .cons       = SCI_CONSOLE,
3112 };
3113
3114 static int sci_remove(struct platform_device *dev)
3115 {
3116     struct sci_port *port = platform_get_drvdata(dev);
3117     unsigned int type = port->port.type;    /* uart_remove_... clears it */
3118
3119     sci_ports_in_use &= ~BIT(port->port.line);
3120     uart_remove_one_port(&sci_uart_driver, &port->port);
3121
3122     sci_cleanup_single(port);
3123
3124     if (port->port.fifosize > 1)
3125         device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3126     if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3127         device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3128
3129     return 0;
3130 }
3131
3132
3133 #define SCI_OF_DATA(type, regtype)  (void *)((type) << 16 | (regtype))
3134 #define SCI_OF_TYPE(data)       ((unsigned long)(data) >> 16)
3135 #define SCI_OF_REGTYPE(data)        ((unsigned long)(data) & 0xffff)
3136
3137 static const struct of_device_id of_sci_match[] = {
3138     /* SoC-specific types */
3139     {
3140         .compatible = "renesas,scif-r7s72100",
3141         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3142     },
3143     {
3144         .compatible = "renesas,scif-r7s9210",
3145         .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3146     },
3147     {
3148         .compatible = "renesas,scif-r9a07g044",
3149         .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3150     },
3151     /* Family-specific types */
3152     {
3153         .compatible = "renesas,rcar-gen1-scif",
3154         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3155     }, {
3156         .compatible = "renesas,rcar-gen2-scif",
3157         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3158     }, {
3159         .compatible = "renesas,rcar-gen3-scif",
3160         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3161     }, {
3162         .compatible = "renesas,rcar-gen4-scif",
3163         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3164     },
3165     /* Generic types */
3166     {
3167         .compatible = "renesas,scif",
3168         .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3169     }, {
3170         .compatible = "renesas,scifa",
3171         .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3172     }, {
3173         .compatible = "renesas,scifb",
3174         .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3175     }, {
3176         .compatible = "renesas,hscif",
3177         .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3178     }, {
3179         .compatible = "renesas,sci",
3180         .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3181     }, {
3182         /* Terminator */
3183     },
3184 };
3185 MODULE_DEVICE_TABLE(of, of_sci_match);
3186
3187 static void sci_reset_control_assert(void *data)
3188 {
3189     reset_control_assert(data);
3190 }
3191
3192 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3193                       unsigned int *dev_id)
3194 {
3195     struct device_node *np = pdev->dev.of_node;
3196     struct reset_control *rstc;
3197     struct plat_sci_port *p;
3198     struct sci_port *sp;
3199     const void *data;
3200     int id, ret;
3201
3202     if (!IS_ENABLED(CONFIG_OF) || !np)
3203         return ERR_PTR(-EINVAL);
3204
3205     data = of_device_get_match_data(&pdev->dev);
3206
3207     rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3208     if (IS_ERR(rstc))
3209         return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3210                          "failed to get reset ctrl\n"));
3211
3212     ret = reset_control_deassert(rstc);
3213     if (ret) {
3214         dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3215         return ERR_PTR(ret);
3216     }
3217
3218     ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3219     if (ret) {
3220         dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3221             ret);
3222         return ERR_PTR(ret);
3223     }
3224
3225     p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3226     if (!p)
3227         return ERR_PTR(-ENOMEM);
3228
3229     /* Get the line number from the aliases node. */
3230     id = of_alias_get_id(np, "serial");
3231     if (id < 0 && ~sci_ports_in_use)
3232         id = ffz(sci_ports_in_use);
3233     if (id < 0) {
3234         dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3235         return ERR_PTR(-EINVAL);
3236     }
3237     if (id >= ARRAY_SIZE(sci_ports)) {
3238         dev_err(&pdev->dev, "serial%d out of range\n", id);
3239         return ERR_PTR(-EINVAL);
3240     }
3241
3242     sp = &sci_ports[id];
3243     *dev_id = id;
3244
3245     p->type = SCI_OF_TYPE(data);
3246     p->regtype = SCI_OF_REGTYPE(data);
3247
3248     sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3249
3250     return p;
3251 }
3252
3253 static int sci_probe_single(struct platform_device *dev,
3254                       unsigned int index,
3255                       struct plat_sci_port *p,
3256                       struct sci_port *sciport)
3257 {
3258     int ret;
3259
3260     /* Sanity check */
3261     if (unlikely(index >= SCI_NPORTS)) {
3262         dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3263                index+1, SCI_NPORTS);
3264         dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3265         return -EINVAL;
3266     }
3267     BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3268     if (sci_ports_in_use & BIT(index))
3269         return -EBUSY;
3270
3271     mutex_lock(&sci_uart_registration_lock);
3272     if (!sci_uart_driver.state) {
3273         ret = uart_register_driver(&sci_uart_driver);
3274         if (ret) {
3275             mutex_unlock(&sci_uart_registration_lock);
3276             return ret;
3277         }
3278     }
3279     mutex_unlock(&sci_uart_registration_lock);
3280
3281     ret = sci_init_single(dev, sciport, index, p, false);
3282     if (ret)
3283         return ret;
3284
3285     sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3286     if (IS_ERR(sciport->gpios))
3287         return PTR_ERR(sciport->gpios);
3288
3289     if (sciport->has_rtscts) {
3290         if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3291             mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3292             dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3293             return -EINVAL;
3294         }
3295         sciport->port.flags |= UPF_HARD_FLOW;
3296     }
3297
3298     ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3299     if (ret) {
3300         sci_cleanup_single(sciport);
3301         return ret;
3302     }
3303
3304     return 0;
3305 }
3306
3307 static int sci_probe(struct platform_device *dev)
3308 {
3309     struct plat_sci_port *p;
3310     struct sci_port *sp;
3311     unsigned int dev_id;
3312     int ret;
3313
3314     /*
3315      * If we've come here via earlyprintk initialization, head off to
3316      * the special early probe. We don't have sufficient device state
3317      * to make it beyond this yet.
3318      */
3319 #ifdef CONFIG_SUPERH
3320     if (is_sh_early_platform_device(dev))
3321         return sci_probe_earlyprintk(dev);
3322 #endif
3323
3324     if (dev->dev.of_node) {
3325         p = sci_parse_dt(dev, &dev_id);
3326         if (IS_ERR(p))
3327             return PTR_ERR(p);
3328     } else {
3329         p = dev->dev.platform_data;
3330         if (p == NULL) {
3331             dev_err(&dev->dev, "no platform data supplied\n");
3332             return -EINVAL;
3333         }
3334
3335         dev_id = dev->id;
3336     }
3337
3338     sp = &sci_ports[dev_id];
3339     platform_set_drvdata(dev, sp);
3340
3341     ret = sci_probe_single(dev, dev_id, p, sp);
3342     if (ret)
3343         return ret;
3344
3345     if (sp->port.fifosize > 1) {
3346         ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3347         if (ret)
3348             return ret;
3349     }
3350     if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3351         sp->port.type == PORT_HSCIF) {
3352         ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3353         if (ret) {
3354             if (sp->port.fifosize > 1) {
3355                 device_remove_file(&dev->dev,
3356                            &dev_attr_rx_fifo_trigger);
3357             }
3358             return ret;
3359         }
3360     }
3361
3362 #ifdef CONFIG_SH_STANDARD_BIOS
3363     sh_bios_gdb_detach();
3364 #endif
3365
3366     sci_ports_in_use |= BIT(dev_id);
3367     return 0;
3368 }
3369
3370 static __maybe_unused int sci_suspend(struct device *dev)
3371 {
3372     struct sci_port *sport = dev_get_drvdata(dev);
3373
3374     if (sport)
3375         uart_suspend_port(&sci_uart_driver, &sport->port);
3376
3377     return 0;
3378 }
3379
3380 static __maybe_unused int sci_resume(struct device *dev)
3381 {
3382     struct sci_port *sport = dev_get_drvdata(dev);
3383
3384     if (sport)
3385         uart_resume_port(&sci_uart_driver, &sport->port);
3386
3387     return 0;
3388 }
3389
3390 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3391
3392 static struct platform_driver sci_driver = {
3393     .probe      = sci_probe,
3394     .remove     = sci_remove,
3395     .driver     = {
3396         .name   = "sh-sci",
3397         .pm = &sci_dev_pm_ops,
3398         .of_match_table = of_match_ptr(of_sci_match),
3399     },
3400 };
3401
3402 static int __init sci_init(void)
3403 {
3404     pr_info("%s\n", banner);
3405
3406     return platform_driver_register(&sci_driver);
3407 }
3408
3409 static void __exit sci_exit(void)
3410 {
3411     platform_driver_unregister(&sci_driver);
3412
3413     if (sci_uart_driver.state)
3414         uart_unregister_driver(&sci_uart_driver);
3415 }
3416
3417 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3418 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3419                early_serial_buf, ARRAY_SIZE(early_serial_buf));
3420 #endif
3421 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3422 static struct plat_sci_port port_cfg __initdata;
3423
3424 static int __init early_console_setup(struct earlycon_device *device,
3425                       int type)
3426 {
3427     if (!device->port.membase)
3428         return -ENODEV;
3429
3430     device->port.serial_in = sci_serial_in;
3431     device->port.serial_out = sci_serial_out;
3432     device->port.type = type;
3433     memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3434     port_cfg.type = type;
3435     sci_ports[0].cfg = &port_cfg;
3436     sci_ports[0].params = sci_probe_regmap(&port_cfg);
3437     port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3438     sci_serial_out(&sci_ports[0].port, SCSCR,
3439                SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3440
3441     device->con->write = serial_console_write;
3442     return 0;
3443 }
3444 static int __init sci_early_console_setup(struct earlycon_device *device,
3445                       const char *opt)
3446 {
3447     return early_console_setup(device, PORT_SCI);
3448 }
3449 static int __init scif_early_console_setup(struct earlycon_device *device,
3450                       const char *opt)
3451 {
3452     return early_console_setup(device, PORT_SCIF);
3453 }
3454 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3455                       const char *opt)
3456 {
3457     port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3458     return early_console_setup(device, PORT_SCIF);
3459 }
3460
3461 static int __init scifa_early_console_setup(struct earlycon_device *device,
3462                       const char *opt)
3463 {
3464     return early_console_setup(device, PORT_SCIFA);
3465 }
3466 static int __init scifb_early_console_setup(struct earlycon_device *device,
3467                       const char *opt)
3468 {
3469     return early_console_setup(device, PORT_SCIFB);
3470 }
3471 static int __init hscif_early_console_setup(struct earlycon_device *device,
3472                       const char *opt)
3473 {
3474     return early_console_setup(device, PORT_HSCIF);
3475 }
3476
3477 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3478 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3479 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3480 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3481 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3482 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3483 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3484 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3485
3486 module_init(sci_init);
3487 module_exit(sci_exit);
3488
3489 MODULE_LICENSE("GPL");
3490 MODULE_ALIAS("platform:sh-sci");
3491 MODULE_AUTHOR("Paul Mundt");
3492 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");