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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * serial_tegra.c
0004  *
0005  * High-speed serial driver for NVIDIA Tegra SoCs
0006  *
0007  * Copyright (c) 2012-2019, NVIDIA CORPORATION.  All rights reserved.
0008  *
0009  * Author: Laxman Dewangan <ldewangan@nvidia.com>
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/debugfs.h>
0014 #include <linux/delay.h>
0015 #include <linux/dmaengine.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/dmapool.h>
0018 #include <linux/err.h>
0019 #include <linux/io.h>
0020 #include <linux/irq.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/pagemap.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/reset.h>
0027 #include <linux/serial.h>
0028 #include <linux/serial_8250.h>
0029 #include <linux/serial_core.h>
0030 #include <linux/serial_reg.h>
0031 #include <linux/slab.h>
0032 #include <linux/string.h>
0033 #include <linux/termios.h>
0034 #include <linux/tty.h>
0035 #include <linux/tty_flip.h>
0036 
0037 #define TEGRA_UART_TYPE             "TEGRA_UART"
0038 #define TX_EMPTY_STATUS             (UART_LSR_TEMT | UART_LSR_THRE)
0039 #define BYTES_TO_ALIGN(x)           ((unsigned long)(x) & 0x3)
0040 
0041 #define TEGRA_UART_RX_DMA_BUFFER_SIZE       4096
0042 #define TEGRA_UART_LSR_TXFIFO_FULL      0x100
0043 #define TEGRA_UART_IER_EORD         0x20
0044 #define TEGRA_UART_MCR_RTS_EN           0x40
0045 #define TEGRA_UART_MCR_CTS_EN           0x20
0046 #define TEGRA_UART_LSR_ANY          (UART_LSR_OE | UART_LSR_BI | \
0047                         UART_LSR_PE | UART_LSR_FE)
0048 #define TEGRA_UART_IRDA_CSR         0x08
0049 #define TEGRA_UART_SIR_ENABLED          0x80
0050 
0051 #define TEGRA_UART_TX_PIO           1
0052 #define TEGRA_UART_TX_DMA           2
0053 #define TEGRA_UART_MIN_DMA          16
0054 #define TEGRA_UART_FIFO_SIZE            32
0055 
0056 /*
0057  * Tx fifo trigger level setting in tegra uart is in
0058  * reverse way then conventional uart.
0059  */
0060 #define TEGRA_UART_TX_TRIG_16B          0x00
0061 #define TEGRA_UART_TX_TRIG_8B           0x10
0062 #define TEGRA_UART_TX_TRIG_4B           0x20
0063 #define TEGRA_UART_TX_TRIG_1B           0x30
0064 
0065 #define TEGRA_UART_MAXIMUM          8
0066 
0067 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
0068 #define TEGRA_UART_DEFAULT_BAUD         115200
0069 #define TEGRA_UART_DEFAULT_LSR          UART_LCR_WLEN8
0070 
0071 /* Tx transfer mode */
0072 #define TEGRA_TX_PIO                1
0073 #define TEGRA_TX_DMA                2
0074 
0075 #define TEGRA_UART_FCR_IIR_FIFO_EN      0x40
0076 
0077 /**
0078  * struct tegra_uart_chip_data: SOC specific data.
0079  *
0080  * @tx_fifo_full_status: Status flag available for checking tx fifo full.
0081  * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
0082  *          Tegra30 does not allow this.
0083  * @support_clk_src_div: Clock source support the clock divider.
0084  * @fifo_mode_enable_status: Is FIFO mode enabled?
0085  * @uart_max_port: Maximum number of UART ports
0086  * @max_dma_burst_bytes: Maximum size of DMA bursts
0087  * @error_tolerance_low_range: Lowest number in the error tolerance range
0088  * @error_tolerance_high_range: Highest number in the error tolerance range
0089  */
0090 struct tegra_uart_chip_data {
0091     bool    tx_fifo_full_status;
0092     bool    allow_txfifo_reset_fifo_mode;
0093     bool    support_clk_src_div;
0094     bool    fifo_mode_enable_status;
0095     int uart_max_port;
0096     int max_dma_burst_bytes;
0097     int error_tolerance_low_range;
0098     int error_tolerance_high_range;
0099 };
0100 
0101 struct tegra_baud_tolerance {
0102     u32 lower_range_baud;
0103     u32 upper_range_baud;
0104     s32 tolerance;
0105 };
0106 
0107 struct tegra_uart_port {
0108     struct uart_port            uport;
0109     const struct tegra_uart_chip_data   *cdata;
0110 
0111     struct clk              *uart_clk;
0112     struct reset_control            *rst;
0113     unsigned int                current_baud;
0114 
0115     /* Register shadow */
0116     unsigned long               fcr_shadow;
0117     unsigned long               mcr_shadow;
0118     unsigned long               lcr_shadow;
0119     unsigned long               ier_shadow;
0120     bool                    rts_active;
0121 
0122     int                 tx_in_progress;
0123     unsigned int                tx_bytes;
0124 
0125     bool                    enable_modem_interrupt;
0126 
0127     bool                    rx_timeout;
0128     int                 rx_in_progress;
0129     int                 symb_bit;
0130 
0131     struct dma_chan             *rx_dma_chan;
0132     struct dma_chan             *tx_dma_chan;
0133     dma_addr_t              rx_dma_buf_phys;
0134     dma_addr_t              tx_dma_buf_phys;
0135     unsigned char               *rx_dma_buf_virt;
0136     unsigned char               *tx_dma_buf_virt;
0137     struct dma_async_tx_descriptor      *tx_dma_desc;
0138     struct dma_async_tx_descriptor      *rx_dma_desc;
0139     dma_cookie_t                tx_cookie;
0140     dma_cookie_t                rx_cookie;
0141     unsigned int                tx_bytes_requested;
0142     unsigned int                rx_bytes_requested;
0143     struct tegra_baud_tolerance     *baud_tolerance;
0144     int                 n_adjustable_baud_rates;
0145     int                 required_rate;
0146     int                 configured_rate;
0147     bool                    use_rx_pio;
0148     bool                    use_tx_pio;
0149     bool                    rx_dma_active;
0150 };
0151 
0152 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
0153 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
0154 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
0155                     bool dma_to_memory);
0156 
0157 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
0158         unsigned long reg)
0159 {
0160     return readl(tup->uport.membase + (reg << tup->uport.regshift));
0161 }
0162 
0163 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
0164     unsigned long reg)
0165 {
0166     writel(val, tup->uport.membase + (reg << tup->uport.regshift));
0167 }
0168 
0169 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
0170 {
0171     return container_of(u, struct tegra_uart_port, uport);
0172 }
0173 
0174 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
0175 {
0176     struct tegra_uart_port *tup = to_tegra_uport(u);
0177 
0178     /*
0179      * RI - Ring detector is active
0180      * CD/DCD/CAR - Carrier detect is always active. For some reason
0181      *  linux has different names for carrier detect.
0182      * DSR - Data Set ready is active as the hardware doesn't support it.
0183      *  Don't know if the linux support this yet?
0184      * CTS - Clear to send. Always set to active, as the hardware handles
0185      *  CTS automatically.
0186      */
0187     if (tup->enable_modem_interrupt)
0188         return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
0189     return TIOCM_CTS;
0190 }
0191 
0192 static void set_rts(struct tegra_uart_port *tup, bool active)
0193 {
0194     unsigned long mcr;
0195 
0196     mcr = tup->mcr_shadow;
0197     if (active)
0198         mcr |= TEGRA_UART_MCR_RTS_EN;
0199     else
0200         mcr &= ~TEGRA_UART_MCR_RTS_EN;
0201     if (mcr != tup->mcr_shadow) {
0202         tegra_uart_write(tup, mcr, UART_MCR);
0203         tup->mcr_shadow = mcr;
0204     }
0205 }
0206 
0207 static void set_dtr(struct tegra_uart_port *tup, bool active)
0208 {
0209     unsigned long mcr;
0210 
0211     mcr = tup->mcr_shadow;
0212     if (active)
0213         mcr |= UART_MCR_DTR;
0214     else
0215         mcr &= ~UART_MCR_DTR;
0216     if (mcr != tup->mcr_shadow) {
0217         tegra_uart_write(tup, mcr, UART_MCR);
0218         tup->mcr_shadow = mcr;
0219     }
0220 }
0221 
0222 static void set_loopbk(struct tegra_uart_port *tup, bool active)
0223 {
0224     unsigned long mcr = tup->mcr_shadow;
0225 
0226     if (active)
0227         mcr |= UART_MCR_LOOP;
0228     else
0229         mcr &= ~UART_MCR_LOOP;
0230 
0231     if (mcr != tup->mcr_shadow) {
0232         tegra_uart_write(tup, mcr, UART_MCR);
0233         tup->mcr_shadow = mcr;
0234     }
0235 }
0236 
0237 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
0238 {
0239     struct tegra_uart_port *tup = to_tegra_uport(u);
0240     int enable;
0241 
0242     tup->rts_active = !!(mctrl & TIOCM_RTS);
0243     set_rts(tup, tup->rts_active);
0244 
0245     enable = !!(mctrl & TIOCM_DTR);
0246     set_dtr(tup, enable);
0247 
0248     enable = !!(mctrl & TIOCM_LOOP);
0249     set_loopbk(tup, enable);
0250 }
0251 
0252 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
0253 {
0254     struct tegra_uart_port *tup = to_tegra_uport(u);
0255     unsigned long lcr;
0256 
0257     lcr = tup->lcr_shadow;
0258     if (break_ctl)
0259         lcr |= UART_LCR_SBC;
0260     else
0261         lcr &= ~UART_LCR_SBC;
0262     tegra_uart_write(tup, lcr, UART_LCR);
0263     tup->lcr_shadow = lcr;
0264 }
0265 
0266 /**
0267  * tegra_uart_wait_cycle_time: Wait for N UART clock periods
0268  *
0269  * @tup:    Tegra serial port data structure.
0270  * @cycles: Number of clock periods to wait.
0271  *
0272  * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
0273  * clock speed is 16X the current baud rate.
0274  */
0275 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
0276                        unsigned int cycles)
0277 {
0278     if (tup->current_baud)
0279         udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
0280 }
0281 
0282 /* Wait for a symbol-time. */
0283 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
0284         unsigned int syms)
0285 {
0286     if (tup->current_baud)
0287         udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
0288             tup->current_baud));
0289 }
0290 
0291 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
0292 {
0293     unsigned long iir;
0294     unsigned int tmout = 100;
0295 
0296     do {
0297         iir = tegra_uart_read(tup, UART_IIR);
0298         if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
0299             return 0;
0300         udelay(1);
0301     } while (--tmout);
0302 
0303     return -ETIMEDOUT;
0304 }
0305 
0306 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
0307 {
0308     unsigned long fcr = tup->fcr_shadow;
0309     unsigned int lsr, tmout = 10000;
0310 
0311     if (tup->rts_active)
0312         set_rts(tup, false);
0313 
0314     if (tup->cdata->allow_txfifo_reset_fifo_mode) {
0315         fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0316         tegra_uart_write(tup, fcr, UART_FCR);
0317     } else {
0318         fcr &= ~UART_FCR_ENABLE_FIFO;
0319         tegra_uart_write(tup, fcr, UART_FCR);
0320         udelay(60);
0321         fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0322         tegra_uart_write(tup, fcr, UART_FCR);
0323         fcr |= UART_FCR_ENABLE_FIFO;
0324         tegra_uart_write(tup, fcr, UART_FCR);
0325         if (tup->cdata->fifo_mode_enable_status)
0326             tegra_uart_wait_fifo_mode_enabled(tup);
0327     }
0328 
0329     /* Dummy read to ensure the write is posted */
0330     tegra_uart_read(tup, UART_SCR);
0331 
0332     /*
0333      * For all tegra devices (up to t210), there is a hardware issue that
0334      * requires software to wait for 32 UART clock periods for the flush
0335      * to propagate, otherwise data could be lost.
0336      */
0337     tegra_uart_wait_cycle_time(tup, 32);
0338 
0339     do {
0340         lsr = tegra_uart_read(tup, UART_LSR);
0341         if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
0342             break;
0343         udelay(1);
0344     } while (--tmout);
0345 
0346     if (tup->rts_active)
0347         set_rts(tup, true);
0348 }
0349 
0350 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
0351                      unsigned int baud, long rate)
0352 {
0353     int i;
0354 
0355     for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
0356         if (baud >= tup->baud_tolerance[i].lower_range_baud &&
0357             baud <= tup->baud_tolerance[i].upper_range_baud)
0358             return (rate + (rate *
0359                 tup->baud_tolerance[i].tolerance) / 10000);
0360     }
0361 
0362     return rate;
0363 }
0364 
0365 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
0366 {
0367     long diff;
0368 
0369     diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
0370         / tup->required_rate;
0371     if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
0372         diff > (tup->cdata->error_tolerance_high_range * 100)) {
0373         dev_err(tup->uport.dev,
0374             "configured baud rate is out of range by %ld", diff);
0375         return -EIO;
0376     }
0377 
0378     return 0;
0379 }
0380 
0381 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
0382 {
0383     unsigned long rate;
0384     unsigned int divisor;
0385     unsigned long lcr;
0386     unsigned long flags;
0387     int ret;
0388 
0389     if (tup->current_baud == baud)
0390         return 0;
0391 
0392     if (tup->cdata->support_clk_src_div) {
0393         rate = baud * 16;
0394         tup->required_rate = rate;
0395 
0396         if (tup->n_adjustable_baud_rates)
0397             rate = tegra_get_tolerance_rate(tup, baud, rate);
0398 
0399         ret = clk_set_rate(tup->uart_clk, rate);
0400         if (ret < 0) {
0401             dev_err(tup->uport.dev,
0402                 "clk_set_rate() failed for rate %lu\n", rate);
0403             return ret;
0404         }
0405         tup->configured_rate = clk_get_rate(tup->uart_clk);
0406         divisor = 1;
0407         ret = tegra_check_rate_in_range(tup);
0408         if (ret < 0)
0409             return ret;
0410     } else {
0411         rate = clk_get_rate(tup->uart_clk);
0412         divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
0413     }
0414 
0415     spin_lock_irqsave(&tup->uport.lock, flags);
0416     lcr = tup->lcr_shadow;
0417     lcr |= UART_LCR_DLAB;
0418     tegra_uart_write(tup, lcr, UART_LCR);
0419 
0420     tegra_uart_write(tup, divisor & 0xFF, UART_TX);
0421     tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
0422 
0423     lcr &= ~UART_LCR_DLAB;
0424     tegra_uart_write(tup, lcr, UART_LCR);
0425 
0426     /* Dummy read to ensure the write is posted */
0427     tegra_uart_read(tup, UART_SCR);
0428     spin_unlock_irqrestore(&tup->uport.lock, flags);
0429 
0430     tup->current_baud = baud;
0431 
0432     /* wait two character intervals at new rate */
0433     tegra_uart_wait_sym_time(tup, 2);
0434     return 0;
0435 }
0436 
0437 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
0438             unsigned long lsr)
0439 {
0440     char flag = TTY_NORMAL;
0441 
0442     if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
0443         if (lsr & UART_LSR_OE) {
0444             /* Overrun error */
0445             flag = TTY_OVERRUN;
0446             tup->uport.icount.overrun++;
0447             dev_dbg(tup->uport.dev, "Got overrun errors\n");
0448         } else if (lsr & UART_LSR_PE) {
0449             /* Parity error */
0450             flag = TTY_PARITY;
0451             tup->uport.icount.parity++;
0452             dev_dbg(tup->uport.dev, "Got Parity errors\n");
0453         } else if (lsr & UART_LSR_FE) {
0454             flag = TTY_FRAME;
0455             tup->uport.icount.frame++;
0456             dev_dbg(tup->uport.dev, "Got frame errors\n");
0457         } else if (lsr & UART_LSR_BI) {
0458             /*
0459              * Break error
0460              * If FIFO read error without any data, reset Rx FIFO
0461              */
0462             if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
0463                 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
0464             if (tup->uport.ignore_status_mask & UART_LSR_BI)
0465                 return TTY_BREAK;
0466             flag = TTY_BREAK;
0467             tup->uport.icount.brk++;
0468             dev_dbg(tup->uport.dev, "Got Break\n");
0469         }
0470         uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
0471     }
0472 
0473     return flag;
0474 }
0475 
0476 static int tegra_uart_request_port(struct uart_port *u)
0477 {
0478     return 0;
0479 }
0480 
0481 static void tegra_uart_release_port(struct uart_port *u)
0482 {
0483     /* Nothing to do here */
0484 }
0485 
0486 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
0487 {
0488     struct circ_buf *xmit = &tup->uport.state->xmit;
0489     int i;
0490 
0491     for (i = 0; i < max_bytes; i++) {
0492         BUG_ON(uart_circ_empty(xmit));
0493         if (tup->cdata->tx_fifo_full_status) {
0494             unsigned long lsr = tegra_uart_read(tup, UART_LSR);
0495             if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
0496                 break;
0497         }
0498         tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
0499         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0500         tup->uport.icount.tx++;
0501     }
0502 }
0503 
0504 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
0505         unsigned int bytes)
0506 {
0507     if (bytes > TEGRA_UART_MIN_DMA)
0508         bytes = TEGRA_UART_MIN_DMA;
0509 
0510     tup->tx_in_progress = TEGRA_UART_TX_PIO;
0511     tup->tx_bytes = bytes;
0512     tup->ier_shadow |= UART_IER_THRI;
0513     tegra_uart_write(tup, tup->ier_shadow, UART_IER);
0514 }
0515 
0516 static void tegra_uart_tx_dma_complete(void *args)
0517 {
0518     struct tegra_uart_port *tup = args;
0519     struct circ_buf *xmit = &tup->uport.state->xmit;
0520     struct dma_tx_state state;
0521     unsigned long flags;
0522     unsigned int count;
0523 
0524     dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
0525     count = tup->tx_bytes_requested - state.residue;
0526     async_tx_ack(tup->tx_dma_desc);
0527     spin_lock_irqsave(&tup->uport.lock, flags);
0528     uart_xmit_advance(&tup->uport, count);
0529     tup->tx_in_progress = 0;
0530     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0531         uart_write_wakeup(&tup->uport);
0532     tegra_uart_start_next_tx(tup);
0533     spin_unlock_irqrestore(&tup->uport.lock, flags);
0534 }
0535 
0536 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
0537         unsigned long count)
0538 {
0539     struct circ_buf *xmit = &tup->uport.state->xmit;
0540     dma_addr_t tx_phys_addr;
0541 
0542     tup->tx_bytes = count & ~(0xF);
0543     tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
0544 
0545     dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
0546                    tup->tx_bytes, DMA_TO_DEVICE);
0547 
0548     tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
0549                 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
0550                 DMA_PREP_INTERRUPT);
0551     if (!tup->tx_dma_desc) {
0552         dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
0553         return -EIO;
0554     }
0555 
0556     tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
0557     tup->tx_dma_desc->callback_param = tup;
0558     tup->tx_in_progress = TEGRA_UART_TX_DMA;
0559     tup->tx_bytes_requested = tup->tx_bytes;
0560     tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
0561     dma_async_issue_pending(tup->tx_dma_chan);
0562     return 0;
0563 }
0564 
0565 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
0566 {
0567     unsigned long tail;
0568     unsigned long count;
0569     struct circ_buf *xmit = &tup->uport.state->xmit;
0570 
0571     if (!tup->current_baud)
0572         return;
0573 
0574     tail = (unsigned long)&xmit->buf[xmit->tail];
0575     count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
0576     if (!count)
0577         return;
0578 
0579     if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
0580         tegra_uart_start_pio_tx(tup, count);
0581     else if (BYTES_TO_ALIGN(tail) > 0)
0582         tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
0583     else
0584         tegra_uart_start_tx_dma(tup, count);
0585 }
0586 
0587 /* Called by serial core driver with u->lock taken. */
0588 static void tegra_uart_start_tx(struct uart_port *u)
0589 {
0590     struct tegra_uart_port *tup = to_tegra_uport(u);
0591     struct circ_buf *xmit = &u->state->xmit;
0592 
0593     if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
0594         tegra_uart_start_next_tx(tup);
0595 }
0596 
0597 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
0598 {
0599     struct tegra_uart_port *tup = to_tegra_uport(u);
0600     unsigned int ret = 0;
0601     unsigned long flags;
0602 
0603     spin_lock_irqsave(&u->lock, flags);
0604     if (!tup->tx_in_progress) {
0605         unsigned long lsr = tegra_uart_read(tup, UART_LSR);
0606         if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
0607             ret = TIOCSER_TEMT;
0608     }
0609     spin_unlock_irqrestore(&u->lock, flags);
0610     return ret;
0611 }
0612 
0613 static void tegra_uart_stop_tx(struct uart_port *u)
0614 {
0615     struct tegra_uart_port *tup = to_tegra_uport(u);
0616     struct dma_tx_state state;
0617     unsigned int count;
0618 
0619     if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
0620         return;
0621 
0622     dmaengine_terminate_all(tup->tx_dma_chan);
0623     dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
0624     count = tup->tx_bytes_requested - state.residue;
0625     async_tx_ack(tup->tx_dma_desc);
0626     uart_xmit_advance(&tup->uport, count);
0627     tup->tx_in_progress = 0;
0628 }
0629 
0630 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
0631 {
0632     struct circ_buf *xmit = &tup->uport.state->xmit;
0633 
0634     tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
0635     tup->tx_in_progress = 0;
0636     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0637         uart_write_wakeup(&tup->uport);
0638     tegra_uart_start_next_tx(tup);
0639 }
0640 
0641 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
0642         struct tty_port *port)
0643 {
0644     do {
0645         char flag = TTY_NORMAL;
0646         unsigned long lsr = 0;
0647         unsigned char ch;
0648 
0649         lsr = tegra_uart_read(tup, UART_LSR);
0650         if (!(lsr & UART_LSR_DR))
0651             break;
0652 
0653         flag = tegra_uart_decode_rx_error(tup, lsr);
0654         if (flag != TTY_NORMAL)
0655             continue;
0656 
0657         ch = (unsigned char) tegra_uart_read(tup, UART_RX);
0658         tup->uport.icount.rx++;
0659 
0660         if (uart_handle_sysrq_char(&tup->uport, ch))
0661             continue;
0662 
0663         if (tup->uport.ignore_status_mask & UART_LSR_DR)
0664             continue;
0665 
0666         tty_insert_flip_char(port, ch, flag);
0667     } while (1);
0668 }
0669 
0670 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
0671                       struct tty_port *port,
0672                       unsigned int count)
0673 {
0674     int copied;
0675 
0676     /* If count is zero, then there is no data to be copied */
0677     if (!count)
0678         return;
0679 
0680     tup->uport.icount.rx += count;
0681 
0682     if (tup->uport.ignore_status_mask & UART_LSR_DR)
0683         return;
0684 
0685     dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
0686                 count, DMA_FROM_DEVICE);
0687     copied = tty_insert_flip_string(port,
0688             ((unsigned char *)(tup->rx_dma_buf_virt)), count);
0689     if (copied != count) {
0690         WARN_ON(1);
0691         dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
0692     }
0693     dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
0694                    count, DMA_TO_DEVICE);
0695 }
0696 
0697 static void do_handle_rx_pio(struct tegra_uart_port *tup)
0698 {
0699     struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
0700     struct tty_port *port = &tup->uport.state->port;
0701 
0702     tegra_uart_handle_rx_pio(tup, port);
0703     if (tty) {
0704         tty_flip_buffer_push(port);
0705         tty_kref_put(tty);
0706     }
0707 }
0708 
0709 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
0710                       unsigned int residue)
0711 {
0712     struct tty_port *port = &tup->uport.state->port;
0713     unsigned int count;
0714 
0715     async_tx_ack(tup->rx_dma_desc);
0716     count = tup->rx_bytes_requested - residue;
0717 
0718     /* If we are here, DMA is stopped */
0719     tegra_uart_copy_rx_to_tty(tup, port, count);
0720 
0721     do_handle_rx_pio(tup);
0722 }
0723 
0724 static void tegra_uart_rx_dma_complete(void *args)
0725 {
0726     struct tegra_uart_port *tup = args;
0727     struct uart_port *u = &tup->uport;
0728     unsigned long flags;
0729     struct dma_tx_state state;
0730     enum dma_status status;
0731 
0732     spin_lock_irqsave(&u->lock, flags);
0733 
0734     status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
0735 
0736     if (status == DMA_IN_PROGRESS) {
0737         dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
0738         goto done;
0739     }
0740 
0741     /* Deactivate flow control to stop sender */
0742     if (tup->rts_active)
0743         set_rts(tup, false);
0744 
0745     tup->rx_dma_active = false;
0746     tegra_uart_rx_buffer_push(tup, 0);
0747     tegra_uart_start_rx_dma(tup);
0748 
0749     /* Activate flow control to start transfer */
0750     if (tup->rts_active)
0751         set_rts(tup, true);
0752 
0753 done:
0754     spin_unlock_irqrestore(&u->lock, flags);
0755 }
0756 
0757 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
0758 {
0759     struct dma_tx_state state;
0760 
0761     if (!tup->rx_dma_active) {
0762         do_handle_rx_pio(tup);
0763         return;
0764     }
0765 
0766     dmaengine_terminate_all(tup->rx_dma_chan);
0767     dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
0768 
0769     tegra_uart_rx_buffer_push(tup, state.residue);
0770     tup->rx_dma_active = false;
0771 }
0772 
0773 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
0774 {
0775     /* Deactivate flow control to stop sender */
0776     if (tup->rts_active)
0777         set_rts(tup, false);
0778 
0779     tegra_uart_terminate_rx_dma(tup);
0780 
0781     if (tup->rts_active)
0782         set_rts(tup, true);
0783 }
0784 
0785 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
0786 {
0787     unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
0788 
0789     if (tup->rx_dma_active)
0790         return 0;
0791 
0792     tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
0793                 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
0794                 DMA_PREP_INTERRUPT);
0795     if (!tup->rx_dma_desc) {
0796         dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
0797         return -EIO;
0798     }
0799 
0800     tup->rx_dma_active = true;
0801     tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
0802     tup->rx_dma_desc->callback_param = tup;
0803     tup->rx_bytes_requested = count;
0804     tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
0805     dma_async_issue_pending(tup->rx_dma_chan);
0806     return 0;
0807 }
0808 
0809 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
0810 {
0811     struct tegra_uart_port *tup = to_tegra_uport(u);
0812     unsigned long msr;
0813 
0814     msr = tegra_uart_read(tup, UART_MSR);
0815     if (!(msr & UART_MSR_ANY_DELTA))
0816         return;
0817 
0818     if (msr & UART_MSR_TERI)
0819         tup->uport.icount.rng++;
0820     if (msr & UART_MSR_DDSR)
0821         tup->uport.icount.dsr++;
0822     /* We may only get DDCD when HW init and reset */
0823     if (msr & UART_MSR_DDCD)
0824         uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
0825     /* Will start/stop_tx accordingly */
0826     if (msr & UART_MSR_DCTS)
0827         uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
0828 }
0829 
0830 static irqreturn_t tegra_uart_isr(int irq, void *data)
0831 {
0832     struct tegra_uart_port *tup = data;
0833     struct uart_port *u = &tup->uport;
0834     unsigned long iir;
0835     unsigned long ier;
0836     bool is_rx_start = false;
0837     bool is_rx_int = false;
0838     unsigned long flags;
0839 
0840     spin_lock_irqsave(&u->lock, flags);
0841     while (1) {
0842         iir = tegra_uart_read(tup, UART_IIR);
0843         if (iir & UART_IIR_NO_INT) {
0844             if (!tup->use_rx_pio && is_rx_int) {
0845                 tegra_uart_handle_rx_dma(tup);
0846                 if (tup->rx_in_progress) {
0847                     ier = tup->ier_shadow;
0848                     ier |= (UART_IER_RLSI | UART_IER_RTOIE |
0849                         TEGRA_UART_IER_EORD | UART_IER_RDI);
0850                     tup->ier_shadow = ier;
0851                     tegra_uart_write(tup, ier, UART_IER);
0852                 }
0853             } else if (is_rx_start) {
0854                 tegra_uart_start_rx_dma(tup);
0855             }
0856             spin_unlock_irqrestore(&u->lock, flags);
0857             return IRQ_HANDLED;
0858         }
0859 
0860         switch ((iir >> 1) & 0x7) {
0861         case 0: /* Modem signal change interrupt */
0862             tegra_uart_handle_modem_signal_change(u);
0863             break;
0864 
0865         case 1: /* Transmit interrupt only triggered when using PIO */
0866             tup->ier_shadow &= ~UART_IER_THRI;
0867             tegra_uart_write(tup, tup->ier_shadow, UART_IER);
0868             tegra_uart_handle_tx_pio(tup);
0869             break;
0870 
0871         case 4: /* End of data */
0872         case 6: /* Rx timeout */
0873             if (!tup->use_rx_pio) {
0874                 is_rx_int = tup->rx_in_progress;
0875                 /* Disable Rx interrupts */
0876                 ier = tup->ier_shadow;
0877                 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
0878                     UART_IER_RTOIE | TEGRA_UART_IER_EORD);
0879                 tup->ier_shadow = ier;
0880                 tegra_uart_write(tup, ier, UART_IER);
0881                 break;
0882             }
0883             fallthrough;
0884         case 2: /* Receive */
0885             if (!tup->use_rx_pio) {
0886                 is_rx_start = tup->rx_in_progress;
0887                 tup->ier_shadow  &= ~UART_IER_RDI;
0888                 tegra_uart_write(tup, tup->ier_shadow,
0889                          UART_IER);
0890             } else {
0891                 do_handle_rx_pio(tup);
0892             }
0893             break;
0894 
0895         case 3: /* Receive error */
0896             tegra_uart_decode_rx_error(tup,
0897                     tegra_uart_read(tup, UART_LSR));
0898             break;
0899 
0900         case 5: /* break nothing to handle */
0901         case 7: /* break nothing to handle */
0902             break;
0903         }
0904     }
0905 }
0906 
0907 static void tegra_uart_stop_rx(struct uart_port *u)
0908 {
0909     struct tegra_uart_port *tup = to_tegra_uport(u);
0910     struct tty_port *port = &tup->uport.state->port;
0911     unsigned long ier;
0912 
0913     if (tup->rts_active)
0914         set_rts(tup, false);
0915 
0916     if (!tup->rx_in_progress)
0917         return;
0918 
0919     tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
0920 
0921     ier = tup->ier_shadow;
0922     ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
0923                     TEGRA_UART_IER_EORD);
0924     tup->ier_shadow = ier;
0925     tegra_uart_write(tup, ier, UART_IER);
0926     tup->rx_in_progress = 0;
0927 
0928     if (!tup->use_rx_pio)
0929         tegra_uart_terminate_rx_dma(tup);
0930     else
0931         tegra_uart_handle_rx_pio(tup, port);
0932 }
0933 
0934 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
0935 {
0936     unsigned long flags;
0937     unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
0938     unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
0939     unsigned long wait_time;
0940     unsigned long lsr;
0941     unsigned long msr;
0942     unsigned long mcr;
0943 
0944     /* Disable interrupts */
0945     tegra_uart_write(tup, 0, UART_IER);
0946 
0947     lsr = tegra_uart_read(tup, UART_LSR);
0948     if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
0949         msr = tegra_uart_read(tup, UART_MSR);
0950         mcr = tegra_uart_read(tup, UART_MCR);
0951         if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
0952             dev_err(tup->uport.dev,
0953                 "Tx Fifo not empty, CTS disabled, waiting\n");
0954 
0955         /* Wait for Tx fifo to be empty */
0956         while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
0957             wait_time = min(fifo_empty_time, 100lu);
0958             udelay(wait_time);
0959             fifo_empty_time -= wait_time;
0960             if (!fifo_empty_time) {
0961                 msr = tegra_uart_read(tup, UART_MSR);
0962                 mcr = tegra_uart_read(tup, UART_MCR);
0963                 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
0964                     (msr & UART_MSR_CTS))
0965                     dev_err(tup->uport.dev,
0966                         "Slave not ready\n");
0967                 break;
0968             }
0969             lsr = tegra_uart_read(tup, UART_LSR);
0970         }
0971     }
0972 
0973     spin_lock_irqsave(&tup->uport.lock, flags);
0974     /* Reset the Rx and Tx FIFOs */
0975     tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
0976     tup->current_baud = 0;
0977     spin_unlock_irqrestore(&tup->uport.lock, flags);
0978 
0979     tup->rx_in_progress = 0;
0980     tup->tx_in_progress = 0;
0981 
0982     if (!tup->use_rx_pio)
0983         tegra_uart_dma_channel_free(tup, true);
0984     if (!tup->use_tx_pio)
0985         tegra_uart_dma_channel_free(tup, false);
0986 
0987     clk_disable_unprepare(tup->uart_clk);
0988 }
0989 
0990 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
0991 {
0992     int ret;
0993 
0994     tup->fcr_shadow = 0;
0995     tup->mcr_shadow = 0;
0996     tup->lcr_shadow = 0;
0997     tup->ier_shadow = 0;
0998     tup->current_baud = 0;
0999 
1000     clk_prepare_enable(tup->uart_clk);
1001 
1002     /* Reset the UART controller to clear all previous status.*/
1003     reset_control_assert(tup->rst);
1004     udelay(10);
1005     reset_control_deassert(tup->rst);
1006 
1007     tup->rx_in_progress = 0;
1008     tup->tx_in_progress = 0;
1009 
1010     /*
1011      * Set the trigger level
1012      *
1013      * For PIO mode:
1014      *
1015      * For receive, this will interrupt the CPU after that many number of
1016      * bytes are received, for the remaining bytes the receive timeout
1017      * interrupt is received. Rx high watermark is set to 4.
1018      *
1019      * For transmit, if the trasnmit interrupt is enabled, this will
1020      * interrupt the CPU when the number of entries in the FIFO reaches the
1021      * low watermark. Tx low watermark is set to 16 bytes.
1022      *
1023      * For DMA mode:
1024      *
1025      * Set the Tx trigger to 16. This should match the DMA burst size that
1026      * programmed in the DMA registers.
1027      */
1028     tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1029 
1030     if (tup->use_rx_pio) {
1031         tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1032     } else {
1033         if (tup->cdata->max_dma_burst_bytes == 8)
1034             tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1035         else
1036             tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1037     }
1038 
1039     tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1040     tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1041 
1042     /* Dummy read to ensure the write is posted */
1043     tegra_uart_read(tup, UART_SCR);
1044 
1045     if (tup->cdata->fifo_mode_enable_status) {
1046         ret = tegra_uart_wait_fifo_mode_enabled(tup);
1047         if (ret < 0) {
1048             dev_err(tup->uport.dev,
1049                 "Failed to enable FIFO mode: %d\n", ret);
1050             return ret;
1051         }
1052     } else {
1053         /*
1054          * For all tegra devices (up to t210), there is a hardware
1055          * issue that requires software to wait for 3 UART clock
1056          * periods after enabling the TX fifo, otherwise data could
1057          * be lost.
1058          */
1059         tegra_uart_wait_cycle_time(tup, 3);
1060     }
1061 
1062     /*
1063      * Initialize the UART with default configuration
1064      * (115200, N, 8, 1) so that the receive DMA buffer may be
1065      * enqueued
1066      */
1067     ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1068     if (ret < 0) {
1069         dev_err(tup->uport.dev, "Failed to set baud rate\n");
1070         return ret;
1071     }
1072     if (!tup->use_rx_pio) {
1073         tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1074         tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1075         tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1076     } else {
1077         tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1078     }
1079     tup->rx_in_progress = 1;
1080 
1081     /*
1082      * Enable IE_RXS for the receive status interrupts like line errors.
1083      * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1084      *
1085      * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1086      * the DATA is sitting in the FIFO and couldn't be transferred to the
1087      * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1088      * triggered when there is a pause of the incomming data stream for 4
1089      * characters long.
1090      *
1091      * For pauses in the data which is not aligned to 4 bytes, we get
1092      * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1093      * then the EORD.
1094      */
1095     tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1096 
1097     /*
1098      * If using DMA mode, enable EORD interrupt to notify about RX
1099      * completion.
1100      */
1101     if (!tup->use_rx_pio)
1102         tup->ier_shadow |= TEGRA_UART_IER_EORD;
1103 
1104     tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1105     return 0;
1106 }
1107 
1108 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1109         bool dma_to_memory)
1110 {
1111     if (dma_to_memory) {
1112         dmaengine_terminate_all(tup->rx_dma_chan);
1113         dma_release_channel(tup->rx_dma_chan);
1114         dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1115                 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1116         tup->rx_dma_chan = NULL;
1117         tup->rx_dma_buf_phys = 0;
1118         tup->rx_dma_buf_virt = NULL;
1119     } else {
1120         dmaengine_terminate_all(tup->tx_dma_chan);
1121         dma_release_channel(tup->tx_dma_chan);
1122         dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1123             UART_XMIT_SIZE, DMA_TO_DEVICE);
1124         tup->tx_dma_chan = NULL;
1125         tup->tx_dma_buf_phys = 0;
1126         tup->tx_dma_buf_virt = NULL;
1127     }
1128 }
1129 
1130 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1131             bool dma_to_memory)
1132 {
1133     struct dma_chan *dma_chan;
1134     unsigned char *dma_buf;
1135     dma_addr_t dma_phys;
1136     int ret;
1137     struct dma_slave_config dma_sconfig;
1138 
1139     dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1140     if (IS_ERR(dma_chan)) {
1141         ret = PTR_ERR(dma_chan);
1142         dev_err(tup->uport.dev,
1143             "DMA channel alloc failed: %d\n", ret);
1144         return ret;
1145     }
1146 
1147     if (dma_to_memory) {
1148         dma_buf = dma_alloc_coherent(tup->uport.dev,
1149                 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1150                  &dma_phys, GFP_KERNEL);
1151         if (!dma_buf) {
1152             dev_err(tup->uport.dev,
1153                 "Not able to allocate the dma buffer\n");
1154             dma_release_channel(dma_chan);
1155             return -ENOMEM;
1156         }
1157         dma_sync_single_for_device(tup->uport.dev, dma_phys,
1158                        TEGRA_UART_RX_DMA_BUFFER_SIZE,
1159                        DMA_TO_DEVICE);
1160         dma_sconfig.src_addr = tup->uport.mapbase;
1161         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162         dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1163         tup->rx_dma_chan = dma_chan;
1164         tup->rx_dma_buf_virt = dma_buf;
1165         tup->rx_dma_buf_phys = dma_phys;
1166     } else {
1167         dma_phys = dma_map_single(tup->uport.dev,
1168             tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1169             DMA_TO_DEVICE);
1170         if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1171             dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1172             dma_release_channel(dma_chan);
1173             return -ENOMEM;
1174         }
1175         dma_buf = tup->uport.state->xmit.buf;
1176         dma_sconfig.dst_addr = tup->uport.mapbase;
1177         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1178         dma_sconfig.dst_maxburst = 16;
1179         tup->tx_dma_chan = dma_chan;
1180         tup->tx_dma_buf_virt = dma_buf;
1181         tup->tx_dma_buf_phys = dma_phys;
1182     }
1183 
1184     ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1185     if (ret < 0) {
1186         dev_err(tup->uport.dev,
1187             "Dma slave config failed, err = %d\n", ret);
1188         tegra_uart_dma_channel_free(tup, dma_to_memory);
1189         return ret;
1190     }
1191 
1192     return 0;
1193 }
1194 
1195 static int tegra_uart_startup(struct uart_port *u)
1196 {
1197     struct tegra_uart_port *tup = to_tegra_uport(u);
1198     int ret;
1199 
1200     if (!tup->use_tx_pio) {
1201         ret = tegra_uart_dma_channel_allocate(tup, false);
1202         if (ret < 0) {
1203             dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1204                 ret);
1205             return ret;
1206         }
1207     }
1208 
1209     if (!tup->use_rx_pio) {
1210         ret = tegra_uart_dma_channel_allocate(tup, true);
1211         if (ret < 0) {
1212             dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1213                 ret);
1214             goto fail_rx_dma;
1215         }
1216     }
1217 
1218     ret = tegra_uart_hw_init(tup);
1219     if (ret < 0) {
1220         dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1221         goto fail_hw_init;
1222     }
1223 
1224     ret = request_irq(u->irq, tegra_uart_isr, 0,
1225                 dev_name(u->dev), tup);
1226     if (ret < 0) {
1227         dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1228         goto fail_hw_init;
1229     }
1230     return 0;
1231 
1232 fail_hw_init:
1233     if (!tup->use_rx_pio)
1234         tegra_uart_dma_channel_free(tup, true);
1235 fail_rx_dma:
1236     if (!tup->use_tx_pio)
1237         tegra_uart_dma_channel_free(tup, false);
1238     return ret;
1239 }
1240 
1241 /*
1242  * Flush any TX data submitted for DMA and PIO. Called when the
1243  * TX circular buffer is reset.
1244  */
1245 static void tegra_uart_flush_buffer(struct uart_port *u)
1246 {
1247     struct tegra_uart_port *tup = to_tegra_uport(u);
1248 
1249     tup->tx_bytes = 0;
1250     if (tup->tx_dma_chan)
1251         dmaengine_terminate_all(tup->tx_dma_chan);
1252 }
1253 
1254 static void tegra_uart_shutdown(struct uart_port *u)
1255 {
1256     struct tegra_uart_port *tup = to_tegra_uport(u);
1257 
1258     tegra_uart_hw_deinit(tup);
1259     free_irq(u->irq, tup);
1260 }
1261 
1262 static void tegra_uart_enable_ms(struct uart_port *u)
1263 {
1264     struct tegra_uart_port *tup = to_tegra_uport(u);
1265 
1266     if (tup->enable_modem_interrupt) {
1267         tup->ier_shadow |= UART_IER_MSI;
1268         tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1269     }
1270 }
1271 
1272 static void tegra_uart_set_termios(struct uart_port *u,
1273         struct ktermios *termios, struct ktermios *oldtermios)
1274 {
1275     struct tegra_uart_port *tup = to_tegra_uport(u);
1276     unsigned int baud;
1277     unsigned long flags;
1278     unsigned int lcr;
1279     unsigned char char_bits;
1280     int symb_bit = 1;
1281     struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1282     unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1283     int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1284     int ret;
1285 
1286     max_divider *= 16;
1287     spin_lock_irqsave(&u->lock, flags);
1288 
1289     /* Changing configuration, it is safe to stop any rx now */
1290     if (tup->rts_active)
1291         set_rts(tup, false);
1292 
1293     /* Clear all interrupts as configuration is going to be changed */
1294     tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1295     tegra_uart_read(tup, UART_IER);
1296     tegra_uart_write(tup, 0, UART_IER);
1297     tegra_uart_read(tup, UART_IER);
1298 
1299     /* Parity */
1300     lcr = tup->lcr_shadow;
1301     lcr &= ~UART_LCR_PARITY;
1302 
1303     /* CMSPAR isn't supported by this driver */
1304     termios->c_cflag &= ~CMSPAR;
1305 
1306     if ((termios->c_cflag & PARENB) == PARENB) {
1307         symb_bit++;
1308         if (termios->c_cflag & PARODD) {
1309             lcr |= UART_LCR_PARITY;
1310             lcr &= ~UART_LCR_EPAR;
1311             lcr &= ~UART_LCR_SPAR;
1312         } else {
1313             lcr |= UART_LCR_PARITY;
1314             lcr |= UART_LCR_EPAR;
1315             lcr &= ~UART_LCR_SPAR;
1316         }
1317     }
1318 
1319     char_bits = tty_get_char_size(termios->c_cflag);
1320     symb_bit += char_bits;
1321     lcr &= ~UART_LCR_WLEN8;
1322     lcr |= UART_LCR_WLEN(char_bits);
1323 
1324     /* Stop bits */
1325     if (termios->c_cflag & CSTOPB) {
1326         lcr |= UART_LCR_STOP;
1327         symb_bit += 2;
1328     } else {
1329         lcr &= ~UART_LCR_STOP;
1330         symb_bit++;
1331     }
1332 
1333     tegra_uart_write(tup, lcr, UART_LCR);
1334     tup->lcr_shadow = lcr;
1335     tup->symb_bit = symb_bit;
1336 
1337     /* Baud rate. */
1338     baud = uart_get_baud_rate(u, termios, oldtermios,
1339             parent_clk_rate/max_divider,
1340             parent_clk_rate/16);
1341     spin_unlock_irqrestore(&u->lock, flags);
1342     ret = tegra_set_baudrate(tup, baud);
1343     if (ret < 0) {
1344         dev_err(tup->uport.dev, "Failed to set baud rate\n");
1345         return;
1346     }
1347     if (tty_termios_baud_rate(termios))
1348         tty_termios_encode_baud_rate(termios, baud, baud);
1349     spin_lock_irqsave(&u->lock, flags);
1350 
1351     /* Flow control */
1352     if (termios->c_cflag & CRTSCTS) {
1353         tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1354         tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1355         tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1356         /* if top layer has asked to set rts active then do so here */
1357         if (tup->rts_active)
1358             set_rts(tup, true);
1359     } else {
1360         tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1361         tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1362         tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1363     }
1364 
1365     /* update the port timeout based on new settings */
1366     uart_update_timeout(u, termios->c_cflag, baud);
1367 
1368     /* Make sure all writes have completed */
1369     tegra_uart_read(tup, UART_IER);
1370 
1371     /* Re-enable interrupt */
1372     tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1373     tegra_uart_read(tup, UART_IER);
1374 
1375     tup->uport.ignore_status_mask = 0;
1376     /* Ignore all characters if CREAD is not set */
1377     if ((termios->c_cflag & CREAD) == 0)
1378         tup->uport.ignore_status_mask |= UART_LSR_DR;
1379     if (termios->c_iflag & IGNBRK)
1380         tup->uport.ignore_status_mask |= UART_LSR_BI;
1381 
1382     spin_unlock_irqrestore(&u->lock, flags);
1383 }
1384 
1385 static const char *tegra_uart_type(struct uart_port *u)
1386 {
1387     return TEGRA_UART_TYPE;
1388 }
1389 
1390 static const struct uart_ops tegra_uart_ops = {
1391     .tx_empty   = tegra_uart_tx_empty,
1392     .set_mctrl  = tegra_uart_set_mctrl,
1393     .get_mctrl  = tegra_uart_get_mctrl,
1394     .stop_tx    = tegra_uart_stop_tx,
1395     .start_tx   = tegra_uart_start_tx,
1396     .stop_rx    = tegra_uart_stop_rx,
1397     .flush_buffer   = tegra_uart_flush_buffer,
1398     .enable_ms  = tegra_uart_enable_ms,
1399     .break_ctl  = tegra_uart_break_ctl,
1400     .startup    = tegra_uart_startup,
1401     .shutdown   = tegra_uart_shutdown,
1402     .set_termios    = tegra_uart_set_termios,
1403     .type       = tegra_uart_type,
1404     .request_port   = tegra_uart_request_port,
1405     .release_port   = tegra_uart_release_port,
1406 };
1407 
1408 static struct uart_driver tegra_uart_driver = {
1409     .owner      = THIS_MODULE,
1410     .driver_name    = "tegra_hsuart",
1411     .dev_name   = "ttyTHS",
1412     .cons       = NULL,
1413     .nr     = TEGRA_UART_MAXIMUM,
1414 };
1415 
1416 static int tegra_uart_parse_dt(struct platform_device *pdev,
1417     struct tegra_uart_port *tup)
1418 {
1419     struct device_node *np = pdev->dev.of_node;
1420     int port;
1421     int ret;
1422     int index;
1423     u32 pval;
1424     int count;
1425     int n_entries;
1426 
1427     port = of_alias_get_id(np, "serial");
1428     if (port < 0) {
1429         dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1430         return port;
1431     }
1432     tup->uport.line = port;
1433 
1434     tup->enable_modem_interrupt = of_property_read_bool(np,
1435                     "nvidia,enable-modem-interrupt");
1436 
1437     index = of_property_match_string(np, "dma-names", "rx");
1438     if (index < 0) {
1439         tup->use_rx_pio = true;
1440         dev_info(&pdev->dev, "RX in PIO mode\n");
1441     }
1442     index = of_property_match_string(np, "dma-names", "tx");
1443     if (index < 0) {
1444         tup->use_tx_pio = true;
1445         dev_info(&pdev->dev, "TX in PIO mode\n");
1446     }
1447 
1448     n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1449     if (n_entries > 0) {
1450         tup->n_adjustable_baud_rates = n_entries / 3;
1451         tup->baud_tolerance =
1452         devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1453                  sizeof(*tup->baud_tolerance), GFP_KERNEL);
1454         if (!tup->baud_tolerance)
1455             return -ENOMEM;
1456         for (count = 0, index = 0; count < n_entries; count += 3,
1457              index++) {
1458             ret =
1459             of_property_read_u32_index(np,
1460                            "nvidia,adjust-baud-rates",
1461                            count, &pval);
1462             if (!ret)
1463                 tup->baud_tolerance[index].lower_range_baud =
1464                 pval;
1465             ret =
1466             of_property_read_u32_index(np,
1467                            "nvidia,adjust-baud-rates",
1468                            count + 1, &pval);
1469             if (!ret)
1470                 tup->baud_tolerance[index].upper_range_baud =
1471                 pval;
1472             ret =
1473             of_property_read_u32_index(np,
1474                            "nvidia,adjust-baud-rates",
1475                            count + 2, &pval);
1476             if (!ret)
1477                 tup->baud_tolerance[index].tolerance =
1478                 (s32)pval;
1479         }
1480     } else {
1481         tup->n_adjustable_baud_rates = 0;
1482     }
1483 
1484     return 0;
1485 }
1486 
1487 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1488     .tx_fifo_full_status        = false,
1489     .allow_txfifo_reset_fifo_mode   = true,
1490     .support_clk_src_div        = false,
1491     .fifo_mode_enable_status    = false,
1492     .uart_max_port          = 5,
1493     .max_dma_burst_bytes        = 4,
1494     .error_tolerance_low_range  = -4,
1495     .error_tolerance_high_range = 4,
1496 };
1497 
1498 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1499     .tx_fifo_full_status        = true,
1500     .allow_txfifo_reset_fifo_mode   = false,
1501     .support_clk_src_div        = true,
1502     .fifo_mode_enable_status    = false,
1503     .uart_max_port          = 5,
1504     .max_dma_burst_bytes        = 4,
1505     .error_tolerance_low_range  = -4,
1506     .error_tolerance_high_range = 4,
1507 };
1508 
1509 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1510     .tx_fifo_full_status        = true,
1511     .allow_txfifo_reset_fifo_mode   = false,
1512     .support_clk_src_div        = true,
1513     .fifo_mode_enable_status    = true,
1514     .uart_max_port          = 8,
1515     .max_dma_burst_bytes        = 8,
1516     .error_tolerance_low_range  = 0,
1517     .error_tolerance_high_range = 4,
1518 };
1519 
1520 static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1521     .tx_fifo_full_status        = true,
1522     .allow_txfifo_reset_fifo_mode   = false,
1523     .support_clk_src_div        = true,
1524     .fifo_mode_enable_status    = true,
1525     .uart_max_port          = 8,
1526     .max_dma_burst_bytes        = 8,
1527     .error_tolerance_low_range  = -2,
1528     .error_tolerance_high_range = 2,
1529 };
1530 
1531 static const struct of_device_id tegra_uart_of_match[] = {
1532     {
1533         .compatible = "nvidia,tegra30-hsuart",
1534         .data       = &tegra30_uart_chip_data,
1535     }, {
1536         .compatible = "nvidia,tegra20-hsuart",
1537         .data       = &tegra20_uart_chip_data,
1538     }, {
1539         .compatible     = "nvidia,tegra186-hsuart",
1540         .data       = &tegra186_uart_chip_data,
1541     }, {
1542         .compatible     = "nvidia,tegra194-hsuart",
1543         .data       = &tegra194_uart_chip_data,
1544     }, {
1545     },
1546 };
1547 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1548 
1549 static int tegra_uart_probe(struct platform_device *pdev)
1550 {
1551     struct tegra_uart_port *tup;
1552     struct uart_port *u;
1553     struct resource *resource;
1554     int ret;
1555     const struct tegra_uart_chip_data *cdata;
1556 
1557     cdata = of_device_get_match_data(&pdev->dev);
1558     if (!cdata) {
1559         dev_err(&pdev->dev, "Error: No device match found\n");
1560         return -ENODEV;
1561     }
1562 
1563     tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1564     if (!tup) {
1565         dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1566         return -ENOMEM;
1567     }
1568 
1569     ret = tegra_uart_parse_dt(pdev, tup);
1570     if (ret < 0)
1571         return ret;
1572 
1573     u = &tup->uport;
1574     u->dev = &pdev->dev;
1575     u->ops = &tegra_uart_ops;
1576     u->type = PORT_TEGRA;
1577     u->fifosize = 32;
1578     tup->cdata = cdata;
1579 
1580     platform_set_drvdata(pdev, tup);
1581     resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1582     if (!resource) {
1583         dev_err(&pdev->dev, "No IO memory resource\n");
1584         return -ENODEV;
1585     }
1586 
1587     u->mapbase = resource->start;
1588     u->membase = devm_ioremap_resource(&pdev->dev, resource);
1589     if (IS_ERR(u->membase))
1590         return PTR_ERR(u->membase);
1591 
1592     tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1593     if (IS_ERR(tup->uart_clk)) {
1594         dev_err(&pdev->dev, "Couldn't get the clock\n");
1595         return PTR_ERR(tup->uart_clk);
1596     }
1597 
1598     tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1599     if (IS_ERR(tup->rst)) {
1600         dev_err(&pdev->dev, "Couldn't get the reset\n");
1601         return PTR_ERR(tup->rst);
1602     }
1603 
1604     u->iotype = UPIO_MEM32;
1605     ret = platform_get_irq(pdev, 0);
1606     if (ret < 0)
1607         return ret;
1608     u->irq = ret;
1609     u->regshift = 2;
1610     ret = uart_add_one_port(&tegra_uart_driver, u);
1611     if (ret < 0) {
1612         dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1613         return ret;
1614     }
1615     return ret;
1616 }
1617 
1618 static int tegra_uart_remove(struct platform_device *pdev)
1619 {
1620     struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1621     struct uart_port *u = &tup->uport;
1622 
1623     uart_remove_one_port(&tegra_uart_driver, u);
1624     return 0;
1625 }
1626 
1627 #ifdef CONFIG_PM_SLEEP
1628 static int tegra_uart_suspend(struct device *dev)
1629 {
1630     struct tegra_uart_port *tup = dev_get_drvdata(dev);
1631     struct uart_port *u = &tup->uport;
1632 
1633     return uart_suspend_port(&tegra_uart_driver, u);
1634 }
1635 
1636 static int tegra_uart_resume(struct device *dev)
1637 {
1638     struct tegra_uart_port *tup = dev_get_drvdata(dev);
1639     struct uart_port *u = &tup->uport;
1640 
1641     return uart_resume_port(&tegra_uart_driver, u);
1642 }
1643 #endif
1644 
1645 static const struct dev_pm_ops tegra_uart_pm_ops = {
1646     SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1647 };
1648 
1649 static struct platform_driver tegra_uart_platform_driver = {
1650     .probe      = tegra_uart_probe,
1651     .remove     = tegra_uart_remove,
1652     .driver     = {
1653         .name   = "serial-tegra",
1654         .of_match_table = tegra_uart_of_match,
1655         .pm = &tegra_uart_pm_ops,
1656     },
1657 };
1658 
1659 static int __init tegra_uart_init(void)
1660 {
1661     int ret;
1662     struct device_node *node;
1663     const struct of_device_id *match = NULL;
1664     const struct tegra_uart_chip_data *cdata = NULL;
1665 
1666     node = of_find_matching_node(NULL, tegra_uart_of_match);
1667     if (node)
1668         match = of_match_node(tegra_uart_of_match, node);
1669     of_node_put(node);
1670     if (match)
1671         cdata = match->data;
1672     if (cdata)
1673         tegra_uart_driver.nr = cdata->uart_max_port;
1674 
1675     ret = uart_register_driver(&tegra_uart_driver);
1676     if (ret < 0) {
1677         pr_err("Could not register %s driver\n",
1678                tegra_uart_driver.driver_name);
1679         return ret;
1680     }
1681 
1682     ret = platform_driver_register(&tegra_uart_platform_driver);
1683     if (ret < 0) {
1684         pr_err("Uart platform driver register failed, e = %d\n", ret);
1685         uart_unregister_driver(&tegra_uart_driver);
1686         return ret;
1687     }
1688     return 0;
1689 }
1690 
1691 static void __exit tegra_uart_exit(void)
1692 {
1693     pr_info("Unloading tegra uart driver\n");
1694     platform_driver_unregister(&tegra_uart_platform_driver);
1695     uart_unregister_driver(&tegra_uart_driver);
1696 }
1697 
1698 module_init(tegra_uart_init);
1699 module_exit(tegra_uart_exit);
1700 
1701 MODULE_ALIAS("platform:serial-tegra");
1702 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1703 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1704 MODULE_LICENSE("GPL v2");
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