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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  NXP (Philips) SCC+++(SCN+++) serial driver
0004  *
0005  *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
0006  *
0007  *  Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/module.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/device.h>
0016 #include <linux/console.h>
0017 #include <linux/serial_core.h>
0018 #include <linux/serial.h>
0019 #include <linux/io.h>
0020 #include <linux/tty.h>
0021 #include <linux/tty_flip.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/platform_data/serial-sccnxp.h>
0025 #include <linux/regulator/consumer.h>
0026 
0027 #define SCCNXP_NAME         "uart-sccnxp"
0028 #define SCCNXP_MAJOR            204
0029 #define SCCNXP_MINOR            205
0030 
0031 #define SCCNXP_MR_REG           (0x00)
0032 #   define MR0_BAUD_NORMAL      (0 << 0)
0033 #   define MR0_BAUD_EXT1        (1 << 0)
0034 #   define MR0_BAUD_EXT2        (5 << 0)
0035 #   define MR0_FIFO         (1 << 3)
0036 #   define MR0_TXLVL        (1 << 4)
0037 #   define MR1_BITS_5       (0 << 0)
0038 #   define MR1_BITS_6       (1 << 0)
0039 #   define MR1_BITS_7       (2 << 0)
0040 #   define MR1_BITS_8       (3 << 0)
0041 #   define MR1_PAR_EVN      (0 << 2)
0042 #   define MR1_PAR_ODD      (1 << 2)
0043 #   define MR1_PAR_NO       (4 << 2)
0044 #   define MR2_STOP1        (7 << 0)
0045 #   define MR2_STOP2        (0xf << 0)
0046 #define SCCNXP_SR_REG           (0x01)
0047 #   define SR_RXRDY         (1 << 0)
0048 #   define SR_FULL          (1 << 1)
0049 #   define SR_TXRDY         (1 << 2)
0050 #   define SR_TXEMT         (1 << 3)
0051 #   define SR_OVR           (1 << 4)
0052 #   define SR_PE            (1 << 5)
0053 #   define SR_FE            (1 << 6)
0054 #   define SR_BRK           (1 << 7)
0055 #define SCCNXP_CSR_REG          (SCCNXP_SR_REG)
0056 #   define CSR_TIMER_MODE       (0x0d)
0057 #define SCCNXP_CR_REG           (0x02)
0058 #   define CR_RX_ENABLE     (1 << 0)
0059 #   define CR_RX_DISABLE        (1 << 1)
0060 #   define CR_TX_ENABLE     (1 << 2)
0061 #   define CR_TX_DISABLE        (1 << 3)
0062 #   define CR_CMD_MRPTR1        (0x01 << 4)
0063 #   define CR_CMD_RX_RESET      (0x02 << 4)
0064 #   define CR_CMD_TX_RESET      (0x03 << 4)
0065 #   define CR_CMD_STATUS_RESET  (0x04 << 4)
0066 #   define CR_CMD_BREAK_RESET   (0x05 << 4)
0067 #   define CR_CMD_START_BREAK   (0x06 << 4)
0068 #   define CR_CMD_STOP_BREAK    (0x07 << 4)
0069 #   define CR_CMD_MRPTR0        (0x0b << 4)
0070 #define SCCNXP_RHR_REG          (0x03)
0071 #define SCCNXP_THR_REG          SCCNXP_RHR_REG
0072 #define SCCNXP_IPCR_REG         (0x04)
0073 #define SCCNXP_ACR_REG          SCCNXP_IPCR_REG
0074 #   define ACR_BAUD0        (0 << 7)
0075 #   define ACR_BAUD1        (1 << 7)
0076 #   define ACR_TIMER_MODE       (6 << 4)
0077 #define SCCNXP_ISR_REG          (0x05)
0078 #define SCCNXP_IMR_REG          SCCNXP_ISR_REG
0079 #   define IMR_TXRDY        (1 << 0)
0080 #   define IMR_RXRDY        (1 << 1)
0081 #   define ISR_TXRDY(x)     (1 << ((x * 4) + 0))
0082 #   define ISR_RXRDY(x)     (1 << ((x * 4) + 1))
0083 #define SCCNXP_CTPU_REG         (0x06)
0084 #define SCCNXP_CTPL_REG         (0x07)
0085 #define SCCNXP_IPR_REG          (0x0d)
0086 #define SCCNXP_OPCR_REG         SCCNXP_IPR_REG
0087 #define SCCNXP_SOP_REG          (0x0e)
0088 #define SCCNXP_START_COUNTER_REG    SCCNXP_SOP_REG
0089 #define SCCNXP_ROP_REG          (0x0f)
0090 
0091 /* Route helpers */
0092 #define MCTRL_MASK(sig)         (0xf << (sig))
0093 #define MCTRL_IBIT(cfg, sig)        ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
0094 #define MCTRL_OBIT(cfg, sig)        ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
0095 
0096 #define SCCNXP_HAVE_IO      0x00000001
0097 #define SCCNXP_HAVE_MR0     0x00000002
0098 
0099 struct sccnxp_chip {
0100     const char      *name;
0101     unsigned int        nr;
0102     unsigned long       freq_min;
0103     unsigned long       freq_std;
0104     unsigned long       freq_max;
0105     unsigned int        flags;
0106     unsigned int        fifosize;
0107     /* Time between read/write cycles */
0108     unsigned int        trwd;
0109 };
0110 
0111 struct sccnxp_port {
0112     struct uart_driver  uart;
0113     struct uart_port    port[SCCNXP_MAX_UARTS];
0114     bool            opened[SCCNXP_MAX_UARTS];
0115 
0116     int         irq;
0117     u8          imr;
0118 
0119     struct sccnxp_chip  *chip;
0120 
0121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
0122     struct console      console;
0123 #endif
0124 
0125     spinlock_t      lock;
0126 
0127     bool            poll;
0128     struct timer_list   timer;
0129 
0130     struct sccnxp_pdata pdata;
0131 
0132     struct regulator    *regulator;
0133 };
0134 
0135 static const struct sccnxp_chip sc2681 = {
0136     .name       = "SC2681",
0137     .nr     = 2,
0138     .freq_min   = 1000000,
0139     .freq_std   = 3686400,
0140     .freq_max   = 4000000,
0141     .flags      = SCCNXP_HAVE_IO,
0142     .fifosize   = 3,
0143     .trwd       = 200,
0144 };
0145 
0146 static const struct sccnxp_chip sc2691 = {
0147     .name       = "SC2691",
0148     .nr     = 1,
0149     .freq_min   = 1000000,
0150     .freq_std   = 3686400,
0151     .freq_max   = 4000000,
0152     .flags      = 0,
0153     .fifosize   = 3,
0154     .trwd       = 150,
0155 };
0156 
0157 static const struct sccnxp_chip sc2692 = {
0158     .name       = "SC2692",
0159     .nr     = 2,
0160     .freq_min   = 1000000,
0161     .freq_std   = 3686400,
0162     .freq_max   = 4000000,
0163     .flags      = SCCNXP_HAVE_IO,
0164     .fifosize   = 3,
0165     .trwd       = 30,
0166 };
0167 
0168 static const struct sccnxp_chip sc2891 = {
0169     .name       = "SC2891",
0170     .nr     = 1,
0171     .freq_min   = 100000,
0172     .freq_std   = 3686400,
0173     .freq_max   = 8000000,
0174     .flags      = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
0175     .fifosize   = 16,
0176     .trwd       = 27,
0177 };
0178 
0179 static const struct sccnxp_chip sc2892 = {
0180     .name       = "SC2892",
0181     .nr     = 2,
0182     .freq_min   = 100000,
0183     .freq_std   = 3686400,
0184     .freq_max   = 8000000,
0185     .flags      = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
0186     .fifosize   = 16,
0187     .trwd       = 17,
0188 };
0189 
0190 static const struct sccnxp_chip sc28202 = {
0191     .name       = "SC28202",
0192     .nr     = 2,
0193     .freq_min   = 1000000,
0194     .freq_std   = 14745600,
0195     .freq_max   = 50000000,
0196     .flags      = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
0197     .fifosize   = 256,
0198     .trwd       = 10,
0199 };
0200 
0201 static const struct sccnxp_chip sc68681 = {
0202     .name       = "SC68681",
0203     .nr     = 2,
0204     .freq_min   = 1000000,
0205     .freq_std   = 3686400,
0206     .freq_max   = 4000000,
0207     .flags      = SCCNXP_HAVE_IO,
0208     .fifosize   = 3,
0209     .trwd       = 200,
0210 };
0211 
0212 static const struct sccnxp_chip sc68692 = {
0213     .name       = "SC68692",
0214     .nr     = 2,
0215     .freq_min   = 1000000,
0216     .freq_std   = 3686400,
0217     .freq_max   = 4000000,
0218     .flags      = SCCNXP_HAVE_IO,
0219     .fifosize   = 3,
0220     .trwd       = 200,
0221 };
0222 
0223 static u8 sccnxp_read(struct uart_port *port, u8 reg)
0224 {
0225     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0226     u8 ret;
0227 
0228     ret = readb(port->membase + (reg << port->regshift));
0229 
0230     ndelay(s->chip->trwd);
0231 
0232     return ret;
0233 }
0234 
0235 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
0236 {
0237     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0238 
0239     writeb(v, port->membase + (reg << port->regshift));
0240 
0241     ndelay(s->chip->trwd);
0242 }
0243 
0244 static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
0245 {
0246     return sccnxp_read(port, (port->line << 3) + reg);
0247 }
0248 
0249 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
0250 {
0251     sccnxp_write(port, (port->line << 3) + reg, v);
0252 }
0253 
0254 static int sccnxp_update_best_err(int a, int b, int *besterr)
0255 {
0256     int err = abs(a - b);
0257 
0258     if (*besterr > err) {
0259         *besterr = err;
0260         return 0;
0261     }
0262 
0263     return 1;
0264 }
0265 
0266 static const struct {
0267     u8  csr;
0268     u8  acr;
0269     u8  mr0;
0270     int baud;
0271 } baud_std[] = {
0272     { 0,    ACR_BAUD0,  MR0_BAUD_NORMAL,    50, },
0273     { 0,    ACR_BAUD1,  MR0_BAUD_NORMAL,    75, },
0274     { 1,    ACR_BAUD0,  MR0_BAUD_NORMAL,    110, },
0275     { 2,    ACR_BAUD0,  MR0_BAUD_NORMAL,    134, },
0276     { 3,    ACR_BAUD1,  MR0_BAUD_NORMAL,    150, },
0277     { 3,    ACR_BAUD0,  MR0_BAUD_NORMAL,    200, },
0278     { 4,    ACR_BAUD0,  MR0_BAUD_NORMAL,    300, },
0279     { 0,    ACR_BAUD1,  MR0_BAUD_EXT1,      450, },
0280     { 1,    ACR_BAUD0,  MR0_BAUD_EXT2,      880, },
0281     { 3,    ACR_BAUD1,  MR0_BAUD_EXT1,      900, },
0282     { 5,    ACR_BAUD0,  MR0_BAUD_NORMAL,    600, },
0283     { 7,    ACR_BAUD0,  MR0_BAUD_NORMAL,    1050, },
0284     { 2,    ACR_BAUD0,  MR0_BAUD_EXT2,      1076, },
0285     { 6,    ACR_BAUD0,  MR0_BAUD_NORMAL,    1200, },
0286     { 10,   ACR_BAUD1,  MR0_BAUD_NORMAL,    1800, },
0287     { 7,    ACR_BAUD1,  MR0_BAUD_NORMAL,    2000, },
0288     { 8,    ACR_BAUD0,  MR0_BAUD_NORMAL,    2400, },
0289     { 5,    ACR_BAUD1,  MR0_BAUD_EXT1,      3600, },
0290     { 9,    ACR_BAUD0,  MR0_BAUD_NORMAL,    4800, },
0291     { 10,   ACR_BAUD0,  MR0_BAUD_NORMAL,    7200, },
0292     { 11,   ACR_BAUD0,  MR0_BAUD_NORMAL,    9600, },
0293     { 8,    ACR_BAUD0,  MR0_BAUD_EXT1,      14400, },
0294     { 12,   ACR_BAUD1,  MR0_BAUD_NORMAL,    19200, },
0295     { 9,    ACR_BAUD0,  MR0_BAUD_EXT1,      28800, },
0296     { 12,   ACR_BAUD0,  MR0_BAUD_NORMAL,    38400, },
0297     { 11,   ACR_BAUD0,  MR0_BAUD_EXT1,      57600, },
0298     { 12,   ACR_BAUD1,  MR0_BAUD_EXT1,      115200, },
0299     { 12,   ACR_BAUD0,  MR0_BAUD_EXT1,      230400, },
0300     { 0, 0, 0, 0 }
0301 };
0302 
0303 static int sccnxp_set_baud(struct uart_port *port, int baud)
0304 {
0305     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0306     int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
0307     struct sccnxp_chip *chip = s->chip;
0308     u8 i, acr = 0, csr = 0, mr0 = 0;
0309 
0310     /* Find divisor to load to the timer preset registers */
0311     div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
0312     if ((div_std >= 2) && (div_std <= 0xffff)) {
0313         bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
0314         sccnxp_update_best_err(baud, bestbaud, &besterr);
0315         csr = CSR_TIMER_MODE;
0316         sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
0317         sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
0318         /* Issue start timer/counter command */
0319         sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
0320     }
0321 
0322     /* Find best baud from table */
0323     for (i = 0; baud_std[i].baud && besterr; i++) {
0324         if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
0325             continue;
0326         div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
0327         tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
0328         if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
0329             acr = baud_std[i].acr;
0330             csr = baud_std[i].csr;
0331             mr0 = baud_std[i].mr0;
0332             bestbaud = tmp_baud;
0333         }
0334     }
0335 
0336     if (chip->flags & SCCNXP_HAVE_MR0) {
0337         /* Enable FIFO, set half level for TX */
0338         mr0 |= MR0_FIFO | MR0_TXLVL;
0339         /* Update MR0 */
0340         sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
0341         sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
0342     }
0343 
0344     sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
0345     sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
0346 
0347     if (baud != bestbaud)
0348         dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
0349             baud, bestbaud);
0350 
0351     return bestbaud;
0352 }
0353 
0354 static void sccnxp_enable_irq(struct uart_port *port, int mask)
0355 {
0356     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0357 
0358     s->imr |= mask << (port->line * 4);
0359     sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
0360 }
0361 
0362 static void sccnxp_disable_irq(struct uart_port *port, int mask)
0363 {
0364     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0365 
0366     s->imr &= ~(mask << (port->line * 4));
0367     sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
0368 }
0369 
0370 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
0371 {
0372     u8 bitmask;
0373     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0374 
0375     if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
0376         bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
0377         if (state)
0378             sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
0379         else
0380             sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
0381     }
0382 }
0383 
0384 static void sccnxp_handle_rx(struct uart_port *port)
0385 {
0386     u8 sr;
0387     unsigned int ch, flag;
0388 
0389     for (;;) {
0390         sr = sccnxp_port_read(port, SCCNXP_SR_REG);
0391         if (!(sr & SR_RXRDY))
0392             break;
0393         sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
0394 
0395         ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
0396 
0397         port->icount.rx++;
0398         flag = TTY_NORMAL;
0399 
0400         if (unlikely(sr)) {
0401             if (sr & SR_BRK) {
0402                 port->icount.brk++;
0403                 sccnxp_port_write(port, SCCNXP_CR_REG,
0404                           CR_CMD_BREAK_RESET);
0405                 if (uart_handle_break(port))
0406                     continue;
0407             } else if (sr & SR_PE)
0408                 port->icount.parity++;
0409             else if (sr & SR_FE)
0410                 port->icount.frame++;
0411             else if (sr & SR_OVR) {
0412                 port->icount.overrun++;
0413                 sccnxp_port_write(port, SCCNXP_CR_REG,
0414                           CR_CMD_STATUS_RESET);
0415             }
0416 
0417             sr &= port->read_status_mask;
0418             if (sr & SR_BRK)
0419                 flag = TTY_BREAK;
0420             else if (sr & SR_PE)
0421                 flag = TTY_PARITY;
0422             else if (sr & SR_FE)
0423                 flag = TTY_FRAME;
0424             else if (sr & SR_OVR)
0425                 flag = TTY_OVERRUN;
0426         }
0427 
0428         if (uart_handle_sysrq_char(port, ch))
0429             continue;
0430 
0431         if (sr & port->ignore_status_mask)
0432             continue;
0433 
0434         uart_insert_char(port, sr, SR_OVR, ch, flag);
0435     }
0436 
0437     tty_flip_buffer_push(&port->state->port);
0438 }
0439 
0440 static void sccnxp_handle_tx(struct uart_port *port)
0441 {
0442     u8 sr;
0443     struct circ_buf *xmit = &port->state->xmit;
0444     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0445 
0446     if (unlikely(port->x_char)) {
0447         sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
0448         port->icount.tx++;
0449         port->x_char = 0;
0450         return;
0451     }
0452 
0453     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0454         /* Disable TX if FIFO is empty */
0455         if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
0456             sccnxp_disable_irq(port, IMR_TXRDY);
0457 
0458             /* Set direction to input */
0459             if (s->chip->flags & SCCNXP_HAVE_IO)
0460                 sccnxp_set_bit(port, DIR_OP, 0);
0461         }
0462         return;
0463     }
0464 
0465     while (!uart_circ_empty(xmit)) {
0466         sr = sccnxp_port_read(port, SCCNXP_SR_REG);
0467         if (!(sr & SR_TXRDY))
0468             break;
0469 
0470         sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
0471         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0472         port->icount.tx++;
0473     }
0474 
0475     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0476         uart_write_wakeup(port);
0477 }
0478 
0479 static void sccnxp_handle_events(struct sccnxp_port *s)
0480 {
0481     int i;
0482     u8 isr;
0483 
0484     do {
0485         isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
0486         isr &= s->imr;
0487         if (!isr)
0488             break;
0489 
0490         for (i = 0; i < s->uart.nr; i++) {
0491             if (s->opened[i] && (isr & ISR_RXRDY(i)))
0492                 sccnxp_handle_rx(&s->port[i]);
0493             if (s->opened[i] && (isr & ISR_TXRDY(i)))
0494                 sccnxp_handle_tx(&s->port[i]);
0495         }
0496     } while (1);
0497 }
0498 
0499 static void sccnxp_timer(struct timer_list *t)
0500 {
0501     struct sccnxp_port *s = from_timer(s, t, timer);
0502     unsigned long flags;
0503 
0504     spin_lock_irqsave(&s->lock, flags);
0505     sccnxp_handle_events(s);
0506     spin_unlock_irqrestore(&s->lock, flags);
0507 
0508     mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
0509 }
0510 
0511 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
0512 {
0513     struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
0514     unsigned long flags;
0515 
0516     spin_lock_irqsave(&s->lock, flags);
0517     sccnxp_handle_events(s);
0518     spin_unlock_irqrestore(&s->lock, flags);
0519 
0520     return IRQ_HANDLED;
0521 }
0522 
0523 static void sccnxp_start_tx(struct uart_port *port)
0524 {
0525     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0526     unsigned long flags;
0527 
0528     spin_lock_irqsave(&s->lock, flags);
0529 
0530     /* Set direction to output */
0531     if (s->chip->flags & SCCNXP_HAVE_IO)
0532         sccnxp_set_bit(port, DIR_OP, 1);
0533 
0534     sccnxp_enable_irq(port, IMR_TXRDY);
0535 
0536     spin_unlock_irqrestore(&s->lock, flags);
0537 }
0538 
0539 static void sccnxp_stop_tx(struct uart_port *port)
0540 {
0541     /* Do nothing */
0542 }
0543 
0544 static void sccnxp_stop_rx(struct uart_port *port)
0545 {
0546     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0547     unsigned long flags;
0548 
0549     spin_lock_irqsave(&s->lock, flags);
0550     sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
0551     spin_unlock_irqrestore(&s->lock, flags);
0552 }
0553 
0554 static unsigned int sccnxp_tx_empty(struct uart_port *port)
0555 {
0556     u8 val;
0557     unsigned long flags;
0558     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0559 
0560     spin_lock_irqsave(&s->lock, flags);
0561     val = sccnxp_port_read(port, SCCNXP_SR_REG);
0562     spin_unlock_irqrestore(&s->lock, flags);
0563 
0564     return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
0565 }
0566 
0567 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
0568 {
0569     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0570     unsigned long flags;
0571 
0572     if (!(s->chip->flags & SCCNXP_HAVE_IO))
0573         return;
0574 
0575     spin_lock_irqsave(&s->lock, flags);
0576 
0577     sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
0578     sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
0579 
0580     spin_unlock_irqrestore(&s->lock, flags);
0581 }
0582 
0583 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
0584 {
0585     u8 bitmask, ipr;
0586     unsigned long flags;
0587     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0588     unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
0589 
0590     if (!(s->chip->flags & SCCNXP_HAVE_IO))
0591         return mctrl;
0592 
0593     spin_lock_irqsave(&s->lock, flags);
0594 
0595     ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
0596 
0597     if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
0598         bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
0599                       DSR_IP);
0600         mctrl &= ~TIOCM_DSR;
0601         mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
0602     }
0603     if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
0604         bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
0605                       CTS_IP);
0606         mctrl &= ~TIOCM_CTS;
0607         mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
0608     }
0609     if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
0610         bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
0611                       DCD_IP);
0612         mctrl &= ~TIOCM_CAR;
0613         mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
0614     }
0615     if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
0616         bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
0617                       RNG_IP);
0618         mctrl &= ~TIOCM_RNG;
0619         mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
0620     }
0621 
0622     spin_unlock_irqrestore(&s->lock, flags);
0623 
0624     return mctrl;
0625 }
0626 
0627 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
0628 {
0629     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0630     unsigned long flags;
0631 
0632     spin_lock_irqsave(&s->lock, flags);
0633     sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
0634               CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
0635     spin_unlock_irqrestore(&s->lock, flags);
0636 }
0637 
0638 static void sccnxp_set_termios(struct uart_port *port,
0639                    struct ktermios *termios, struct ktermios *old)
0640 {
0641     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0642     unsigned long flags;
0643     u8 mr1, mr2;
0644     int baud;
0645 
0646     spin_lock_irqsave(&s->lock, flags);
0647 
0648     /* Mask termios capabilities we don't support */
0649     termios->c_cflag &= ~CMSPAR;
0650 
0651     /* Disable RX & TX, reset break condition, status and FIFOs */
0652     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
0653                            CR_RX_DISABLE | CR_TX_DISABLE);
0654     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
0655     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
0656     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
0657 
0658     /* Word size */
0659     switch (termios->c_cflag & CSIZE) {
0660     case CS5:
0661         mr1 = MR1_BITS_5;
0662         break;
0663     case CS6:
0664         mr1 = MR1_BITS_6;
0665         break;
0666     case CS7:
0667         mr1 = MR1_BITS_7;
0668         break;
0669     case CS8:
0670     default:
0671         mr1 = MR1_BITS_8;
0672         break;
0673     }
0674 
0675     /* Parity */
0676     if (termios->c_cflag & PARENB) {
0677         if (termios->c_cflag & PARODD)
0678             mr1 |= MR1_PAR_ODD;
0679     } else
0680         mr1 |= MR1_PAR_NO;
0681 
0682     /* Stop bits */
0683     mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
0684 
0685     /* Update desired format */
0686     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
0687     sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
0688     sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
0689 
0690     /* Set read status mask */
0691     port->read_status_mask = SR_OVR;
0692     if (termios->c_iflag & INPCK)
0693         port->read_status_mask |= SR_PE | SR_FE;
0694     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0695         port->read_status_mask |= SR_BRK;
0696 
0697     /* Set status ignore mask */
0698     port->ignore_status_mask = 0;
0699     if (termios->c_iflag & IGNBRK)
0700         port->ignore_status_mask |= SR_BRK;
0701     if (termios->c_iflag & IGNPAR)
0702         port->ignore_status_mask |= SR_PE;
0703     if (!(termios->c_cflag & CREAD))
0704         port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
0705 
0706     /* Setup baudrate */
0707     baud = uart_get_baud_rate(port, termios, old, 50,
0708                   (s->chip->flags & SCCNXP_HAVE_MR0) ?
0709                   230400 : 38400);
0710     baud = sccnxp_set_baud(port, baud);
0711 
0712     /* Update timeout according to new baud rate */
0713     uart_update_timeout(port, termios->c_cflag, baud);
0714 
0715     /* Report actual baudrate back to core */
0716     if (tty_termios_baud_rate(termios))
0717         tty_termios_encode_baud_rate(termios, baud, baud);
0718 
0719     /* Enable RX & TX */
0720     sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
0721 
0722     spin_unlock_irqrestore(&s->lock, flags);
0723 }
0724 
0725 static int sccnxp_startup(struct uart_port *port)
0726 {
0727     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0728     unsigned long flags;
0729 
0730     spin_lock_irqsave(&s->lock, flags);
0731 
0732     if (s->chip->flags & SCCNXP_HAVE_IO) {
0733         /* Outputs are controlled manually */
0734         sccnxp_write(port, SCCNXP_OPCR_REG, 0);
0735     }
0736 
0737     /* Reset break condition, status and FIFOs */
0738     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
0739     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
0740     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
0741     sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
0742 
0743     /* Enable RX & TX */
0744     sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
0745 
0746     /* Enable RX interrupt */
0747     sccnxp_enable_irq(port, IMR_RXRDY);
0748 
0749     s->opened[port->line] = 1;
0750 
0751     spin_unlock_irqrestore(&s->lock, flags);
0752 
0753     return 0;
0754 }
0755 
0756 static void sccnxp_shutdown(struct uart_port *port)
0757 {
0758     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0759     unsigned long flags;
0760 
0761     spin_lock_irqsave(&s->lock, flags);
0762 
0763     s->opened[port->line] = 0;
0764 
0765     /* Disable interrupts */
0766     sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
0767 
0768     /* Disable TX & RX */
0769     sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
0770 
0771     /* Leave direction to input */
0772     if (s->chip->flags & SCCNXP_HAVE_IO)
0773         sccnxp_set_bit(port, DIR_OP, 0);
0774 
0775     spin_unlock_irqrestore(&s->lock, flags);
0776 }
0777 
0778 static const char *sccnxp_type(struct uart_port *port)
0779 {
0780     struct sccnxp_port *s = dev_get_drvdata(port->dev);
0781 
0782     return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
0783 }
0784 
0785 static void sccnxp_release_port(struct uart_port *port)
0786 {
0787     /* Do nothing */
0788 }
0789 
0790 static int sccnxp_request_port(struct uart_port *port)
0791 {
0792     /* Do nothing */
0793     return 0;
0794 }
0795 
0796 static void sccnxp_config_port(struct uart_port *port, int flags)
0797 {
0798     if (flags & UART_CONFIG_TYPE)
0799         port->type = PORT_SC26XX;
0800 }
0801 
0802 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
0803 {
0804     if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
0805         return 0;
0806     if (s->irq == port->irq)
0807         return 0;
0808 
0809     return -EINVAL;
0810 }
0811 
0812 static const struct uart_ops sccnxp_ops = {
0813     .tx_empty   = sccnxp_tx_empty,
0814     .set_mctrl  = sccnxp_set_mctrl,
0815     .get_mctrl  = sccnxp_get_mctrl,
0816     .stop_tx    = sccnxp_stop_tx,
0817     .start_tx   = sccnxp_start_tx,
0818     .stop_rx    = sccnxp_stop_rx,
0819     .break_ctl  = sccnxp_break_ctl,
0820     .startup    = sccnxp_startup,
0821     .shutdown   = sccnxp_shutdown,
0822     .set_termios    = sccnxp_set_termios,
0823     .type       = sccnxp_type,
0824     .release_port   = sccnxp_release_port,
0825     .request_port   = sccnxp_request_port,
0826     .config_port    = sccnxp_config_port,
0827     .verify_port    = sccnxp_verify_port,
0828 };
0829 
0830 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
0831 static void sccnxp_console_putchar(struct uart_port *port, unsigned char c)
0832 {
0833     int tryes = 100000;
0834 
0835     while (tryes--) {
0836         if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
0837             sccnxp_port_write(port, SCCNXP_THR_REG, c);
0838             break;
0839         }
0840         barrier();
0841     }
0842 }
0843 
0844 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
0845 {
0846     struct sccnxp_port *s = (struct sccnxp_port *)co->data;
0847     struct uart_port *port = &s->port[co->index];
0848     unsigned long flags;
0849 
0850     spin_lock_irqsave(&s->lock, flags);
0851     uart_console_write(port, c, n, sccnxp_console_putchar);
0852     spin_unlock_irqrestore(&s->lock, flags);
0853 }
0854 
0855 static int sccnxp_console_setup(struct console *co, char *options)
0856 {
0857     struct sccnxp_port *s = (struct sccnxp_port *)co->data;
0858     struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
0859     int baud = 9600, bits = 8, parity = 'n', flow = 'n';
0860 
0861     if (options)
0862         uart_parse_options(options, &baud, &parity, &bits, &flow);
0863 
0864     return uart_set_options(port, co, baud, parity, bits, flow);
0865 }
0866 #endif
0867 
0868 static const struct platform_device_id sccnxp_id_table[] = {
0869     { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
0870     { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
0871     { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
0872     { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
0873     { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
0874     { .name = "sc28202",    .driver_data = (kernel_ulong_t)&sc28202, },
0875     { .name = "sc68681",    .driver_data = (kernel_ulong_t)&sc68681, },
0876     { .name = "sc68692",    .driver_data = (kernel_ulong_t)&sc68692, },
0877     { }
0878 };
0879 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
0880 
0881 static int sccnxp_probe(struct platform_device *pdev)
0882 {
0883     struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0884     struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
0885     int i, ret, uartclk;
0886     struct sccnxp_port *s;
0887     void __iomem *membase;
0888     struct clk *clk;
0889 
0890     membase = devm_ioremap_resource(&pdev->dev, res);
0891     if (IS_ERR(membase))
0892         return PTR_ERR(membase);
0893 
0894     s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
0895     if (!s) {
0896         dev_err(&pdev->dev, "Error allocating port structure\n");
0897         return -ENOMEM;
0898     }
0899     platform_set_drvdata(pdev, s);
0900 
0901     spin_lock_init(&s->lock);
0902 
0903     s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
0904 
0905     s->regulator = devm_regulator_get(&pdev->dev, "vcc");
0906     if (!IS_ERR(s->regulator)) {
0907         ret = regulator_enable(s->regulator);
0908         if (ret) {
0909             dev_err(&pdev->dev,
0910                 "Failed to enable regulator: %i\n", ret);
0911             return ret;
0912         }
0913     } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
0914         return -EPROBE_DEFER;
0915 
0916     clk = devm_clk_get(&pdev->dev, NULL);
0917     if (IS_ERR(clk)) {
0918         ret = PTR_ERR(clk);
0919         if (ret == -EPROBE_DEFER)
0920             goto err_out;
0921         uartclk = 0;
0922     } else {
0923         ret = clk_prepare_enable(clk);
0924         if (ret)
0925             goto err_out;
0926 
0927         ret = devm_add_action_or_reset(&pdev->dev,
0928                 (void(*)(void *))clk_disable_unprepare,
0929                 clk);
0930         if (ret)
0931             goto err_out;
0932 
0933         uartclk = clk_get_rate(clk);
0934     }
0935 
0936     if (!uartclk) {
0937         dev_notice(&pdev->dev, "Using default clock frequency\n");
0938         uartclk = s->chip->freq_std;
0939     }
0940 
0941     /* Check input frequency */
0942     if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
0943         dev_err(&pdev->dev, "Frequency out of bounds\n");
0944         ret = -EINVAL;
0945         goto err_out;
0946     }
0947 
0948     if (pdata)
0949         memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
0950 
0951     if (s->pdata.poll_time_us) {
0952         dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
0953              s->pdata.poll_time_us);
0954         s->poll = 1;
0955     }
0956 
0957     if (!s->poll) {
0958         s->irq = platform_get_irq(pdev, 0);
0959         if (s->irq < 0) {
0960             ret = -ENXIO;
0961             goto err_out;
0962         }
0963     }
0964 
0965     s->uart.owner       = THIS_MODULE;
0966     s->uart.dev_name    = "ttySC";
0967     s->uart.major       = SCCNXP_MAJOR;
0968     s->uart.minor       = SCCNXP_MINOR;
0969     s->uart.nr      = s->chip->nr;
0970 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
0971     s->uart.cons        = &s->console;
0972     s->uart.cons->device    = uart_console_device;
0973     s->uart.cons->write = sccnxp_console_write;
0974     s->uart.cons->setup = sccnxp_console_setup;
0975     s->uart.cons->flags = CON_PRINTBUFFER;
0976     s->uart.cons->index = -1;
0977     s->uart.cons->data  = s;
0978     strcpy(s->uart.cons->name, "ttySC");
0979 #endif
0980     ret = uart_register_driver(&s->uart);
0981     if (ret) {
0982         dev_err(&pdev->dev, "Registering UART driver failed\n");
0983         goto err_out;
0984     }
0985 
0986     for (i = 0; i < s->uart.nr; i++) {
0987         s->port[i].line     = i;
0988         s->port[i].dev      = &pdev->dev;
0989         s->port[i].irq      = s->irq;
0990         s->port[i].type     = PORT_SC26XX;
0991         s->port[i].fifosize = s->chip->fifosize;
0992         s->port[i].flags    = UPF_SKIP_TEST | UPF_FIXED_TYPE;
0993         s->port[i].iotype   = UPIO_MEM;
0994         s->port[i].mapbase  = res->start;
0995         s->port[i].membase  = membase;
0996         s->port[i].regshift = s->pdata.reg_shift;
0997         s->port[i].uartclk  = uartclk;
0998         s->port[i].ops      = &sccnxp_ops;
0999         s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);
1000         uart_add_one_port(&s->uart, &s->port[i]);
1001         /* Set direction to input */
1002         if (s->chip->flags & SCCNXP_HAVE_IO)
1003             sccnxp_set_bit(&s->port[i], DIR_OP, 0);
1004     }
1005 
1006     /* Disable interrupts */
1007     s->imr = 0;
1008     sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
1009 
1010     if (!s->poll) {
1011         ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1012                         sccnxp_ist,
1013                         IRQF_TRIGGER_FALLING |
1014                         IRQF_ONESHOT,
1015                         dev_name(&pdev->dev), s);
1016         if (!ret)
1017             return 0;
1018 
1019         dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1020     } else {
1021         timer_setup(&s->timer, sccnxp_timer, 0);
1022         mod_timer(&s->timer, jiffies +
1023               usecs_to_jiffies(s->pdata.poll_time_us));
1024         return 0;
1025     }
1026 
1027     uart_unregister_driver(&s->uart);
1028 err_out:
1029     if (!IS_ERR(s->regulator))
1030         regulator_disable(s->regulator);
1031 
1032     return ret;
1033 }
1034 
1035 static int sccnxp_remove(struct platform_device *pdev)
1036 {
1037     int i;
1038     struct sccnxp_port *s = platform_get_drvdata(pdev);
1039 
1040     if (!s->poll)
1041         devm_free_irq(&pdev->dev, s->irq, s);
1042     else
1043         del_timer_sync(&s->timer);
1044 
1045     for (i = 0; i < s->uart.nr; i++)
1046         uart_remove_one_port(&s->uart, &s->port[i]);
1047 
1048     uart_unregister_driver(&s->uart);
1049 
1050     if (!IS_ERR(s->regulator))
1051         return regulator_disable(s->regulator);
1052 
1053     return 0;
1054 }
1055 
1056 static struct platform_driver sccnxp_uart_driver = {
1057     .driver = {
1058         .name   = SCCNXP_NAME,
1059     },
1060     .probe      = sccnxp_probe,
1061     .remove     = sccnxp_remove,
1062     .id_table   = sccnxp_id_table,
1063 };
1064 module_platform_driver(sccnxp_uart_driver);
1065 
1066 MODULE_LICENSE("GPL v2");
1067 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1068 MODULE_DESCRIPTION("SCCNXP serial driver");
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