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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
0004  * Author: Jon Ringle <jringle@gridpoint.com>
0005  *
0006  *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
0007  */
0008 
0009 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0010 
0011 #include <linux/bitops.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/i2c.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/module.h>
0019 #include <linux/property.h>
0020 #include <linux/regmap.h>
0021 #include <linux/serial_core.h>
0022 #include <linux/serial.h>
0023 #include <linux/tty.h>
0024 #include <linux/tty_flip.h>
0025 #include <linux/spi/spi.h>
0026 #include <linux/uaccess.h>
0027 #include <uapi/linux/sched/types.h>
0028 
0029 #define SC16IS7XX_NAME          "sc16is7xx"
0030 #define SC16IS7XX_MAX_DEVS      8
0031 
0032 /* SC16IS7XX register definitions */
0033 #define SC16IS7XX_RHR_REG       (0x00) /* RX FIFO */
0034 #define SC16IS7XX_THR_REG       (0x00) /* TX FIFO */
0035 #define SC16IS7XX_IER_REG       (0x01) /* Interrupt enable */
0036 #define SC16IS7XX_IIR_REG       (0x02) /* Interrupt Identification */
0037 #define SC16IS7XX_FCR_REG       (0x02) /* FIFO control */
0038 #define SC16IS7XX_LCR_REG       (0x03) /* Line Control */
0039 #define SC16IS7XX_MCR_REG       (0x04) /* Modem Control */
0040 #define SC16IS7XX_LSR_REG       (0x05) /* Line Status */
0041 #define SC16IS7XX_MSR_REG       (0x06) /* Modem Status */
0042 #define SC16IS7XX_SPR_REG       (0x07) /* Scratch Pad */
0043 #define SC16IS7XX_TXLVL_REG     (0x08) /* TX FIFO level */
0044 #define SC16IS7XX_RXLVL_REG     (0x09) /* RX FIFO level */
0045 #define SC16IS7XX_IODIR_REG     (0x0a) /* I/O Direction
0046                         * - only on 75x/76x
0047                         */
0048 #define SC16IS7XX_IOSTATE_REG       (0x0b) /* I/O State
0049                         * - only on 75x/76x
0050                         */
0051 #define SC16IS7XX_IOINTENA_REG      (0x0c) /* I/O Interrupt Enable
0052                         * - only on 75x/76x
0053                         */
0054 #define SC16IS7XX_IOCONTROL_REG     (0x0e) /* I/O Control
0055                         * - only on 75x/76x
0056                         */
0057 #define SC16IS7XX_EFCR_REG      (0x0f) /* Extra Features Control */
0058 
0059 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
0060 #define SC16IS7XX_TCR_REG       (0x06) /* Transmit control */
0061 #define SC16IS7XX_TLR_REG       (0x07) /* Trigger level */
0062 
0063 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
0064 #define SC16IS7XX_DLL_REG       (0x00) /* Divisor Latch Low */
0065 #define SC16IS7XX_DLH_REG       (0x01) /* Divisor Latch High */
0066 
0067 /* Enhanced Register set: Only if (LCR == 0xBF) */
0068 #define SC16IS7XX_EFR_REG       (0x02) /* Enhanced Features */
0069 #define SC16IS7XX_XON1_REG      (0x04) /* Xon1 word */
0070 #define SC16IS7XX_XON2_REG      (0x05) /* Xon2 word */
0071 #define SC16IS7XX_XOFF1_REG     (0x06) /* Xoff1 word */
0072 #define SC16IS7XX_XOFF2_REG     (0x07) /* Xoff2 word */
0073 
0074 /* IER register bits */
0075 #define SC16IS7XX_IER_RDI_BIT       (1 << 0) /* Enable RX data interrupt */
0076 #define SC16IS7XX_IER_THRI_BIT      (1 << 1) /* Enable TX holding register
0077                           * interrupt */
0078 #define SC16IS7XX_IER_RLSI_BIT      (1 << 2) /* Enable RX line status
0079                           * interrupt */
0080 #define SC16IS7XX_IER_MSI_BIT       (1 << 3) /* Enable Modem status
0081                           * interrupt */
0082 
0083 /* IER register bits - write only if (EFR[4] == 1) */
0084 #define SC16IS7XX_IER_SLEEP_BIT     (1 << 4) /* Enable Sleep mode */
0085 #define SC16IS7XX_IER_XOFFI_BIT     (1 << 5) /* Enable Xoff interrupt */
0086 #define SC16IS7XX_IER_RTSI_BIT      (1 << 6) /* Enable nRTS interrupt */
0087 #define SC16IS7XX_IER_CTSI_BIT      (1 << 7) /* Enable nCTS interrupt */
0088 
0089 /* FCR register bits */
0090 #define SC16IS7XX_FCR_FIFO_BIT      (1 << 0) /* Enable FIFO */
0091 #define SC16IS7XX_FCR_RXRESET_BIT   (1 << 1) /* Reset RX FIFO */
0092 #define SC16IS7XX_FCR_TXRESET_BIT   (1 << 2) /* Reset TX FIFO */
0093 #define SC16IS7XX_FCR_RXLVLL_BIT    (1 << 6) /* RX Trigger level LSB */
0094 #define SC16IS7XX_FCR_RXLVLH_BIT    (1 << 7) /* RX Trigger level MSB */
0095 
0096 /* FCR register bits - write only if (EFR[4] == 1) */
0097 #define SC16IS7XX_FCR_TXLVLL_BIT    (1 << 4) /* TX Trigger level LSB */
0098 #define SC16IS7XX_FCR_TXLVLH_BIT    (1 << 5) /* TX Trigger level MSB */
0099 
0100 /* IIR register bits */
0101 #define SC16IS7XX_IIR_NO_INT_BIT    (1 << 0) /* No interrupts pending */
0102 #define SC16IS7XX_IIR_ID_MASK       0x3e     /* Mask for the interrupt ID */
0103 #define SC16IS7XX_IIR_THRI_SRC      0x02     /* TX holding register empty */
0104 #define SC16IS7XX_IIR_RDI_SRC       0x04     /* RX data interrupt */
0105 #define SC16IS7XX_IIR_RLSE_SRC      0x06     /* RX line status error */
0106 #define SC16IS7XX_IIR_RTOI_SRC      0x0c     /* RX time-out interrupt */
0107 #define SC16IS7XX_IIR_MSI_SRC       0x00     /* Modem status interrupt
0108                           * - only on 75x/76x
0109                           */
0110 #define SC16IS7XX_IIR_INPIN_SRC     0x30     /* Input pin change of state
0111                           * - only on 75x/76x
0112                           */
0113 #define SC16IS7XX_IIR_XOFFI_SRC     0x10     /* Received Xoff */
0114 #define SC16IS7XX_IIR_CTSRTS_SRC    0x20     /* nCTS,nRTS change of state
0115                           * from active (LOW)
0116                           * to inactive (HIGH)
0117                           */
0118 /* LCR register bits */
0119 #define SC16IS7XX_LCR_LENGTH0_BIT   (1 << 0) /* Word length bit 0 */
0120 #define SC16IS7XX_LCR_LENGTH1_BIT   (1 << 1) /* Word length bit 1
0121                           *
0122                           * Word length bits table:
0123                           * 00 -> 5 bit words
0124                           * 01 -> 6 bit words
0125                           * 10 -> 7 bit words
0126                           * 11 -> 8 bit words
0127                           */
0128 #define SC16IS7XX_LCR_STOPLEN_BIT   (1 << 2) /* STOP length bit
0129                           *
0130                           * STOP length bit table:
0131                           * 0 -> 1 stop bit
0132                           * 1 -> 1-1.5 stop bits if
0133                           *      word length is 5,
0134                           *      2 stop bits otherwise
0135                           */
0136 #define SC16IS7XX_LCR_PARITY_BIT    (1 << 3) /* Parity bit enable */
0137 #define SC16IS7XX_LCR_EVENPARITY_BIT    (1 << 4) /* Even parity bit enable */
0138 #define SC16IS7XX_LCR_FORCEPARITY_BIT   (1 << 5) /* 9-bit multidrop parity */
0139 #define SC16IS7XX_LCR_TXBREAK_BIT   (1 << 6) /* TX break enable */
0140 #define SC16IS7XX_LCR_DLAB_BIT      (1 << 7) /* Divisor Latch enable */
0141 #define SC16IS7XX_LCR_WORD_LEN_5    (0x00)
0142 #define SC16IS7XX_LCR_WORD_LEN_6    (0x01)
0143 #define SC16IS7XX_LCR_WORD_LEN_7    (0x02)
0144 #define SC16IS7XX_LCR_WORD_LEN_8    (0x03)
0145 #define SC16IS7XX_LCR_CONF_MODE_A   SC16IS7XX_LCR_DLAB_BIT /* Special
0146                                 * reg set */
0147 #define SC16IS7XX_LCR_CONF_MODE_B   0xBF                   /* Enhanced
0148                                 * reg set */
0149 
0150 /* MCR register bits */
0151 #define SC16IS7XX_MCR_DTR_BIT       (1 << 0) /* DTR complement
0152                           * - only on 75x/76x
0153                           */
0154 #define SC16IS7XX_MCR_RTS_BIT       (1 << 1) /* RTS complement */
0155 #define SC16IS7XX_MCR_TCRTLR_BIT    (1 << 2) /* TCR/TLR register enable */
0156 #define SC16IS7XX_MCR_LOOP_BIT      (1 << 4) /* Enable loopback test mode */
0157 #define SC16IS7XX_MCR_XONANY_BIT    (1 << 5) /* Enable Xon Any
0158                           * - write enabled
0159                           * if (EFR[4] == 1)
0160                           */
0161 #define SC16IS7XX_MCR_IRDA_BIT      (1 << 6) /* Enable IrDA mode
0162                           * - write enabled
0163                           * if (EFR[4] == 1)
0164                           */
0165 #define SC16IS7XX_MCR_CLKSEL_BIT    (1 << 7) /* Divide clock by 4
0166                           * - write enabled
0167                           * if (EFR[4] == 1)
0168                           */
0169 
0170 /* LSR register bits */
0171 #define SC16IS7XX_LSR_DR_BIT        (1 << 0) /* Receiver data ready */
0172 #define SC16IS7XX_LSR_OE_BIT        (1 << 1) /* Overrun Error */
0173 #define SC16IS7XX_LSR_PE_BIT        (1 << 2) /* Parity Error */
0174 #define SC16IS7XX_LSR_FE_BIT        (1 << 3) /* Frame Error */
0175 #define SC16IS7XX_LSR_BI_BIT        (1 << 4) /* Break Interrupt */
0176 #define SC16IS7XX_LSR_BRK_ERROR_MASK    0x1E     /* BI, FE, PE, OE bits */
0177 #define SC16IS7XX_LSR_THRE_BIT      (1 << 5) /* TX holding register empty */
0178 #define SC16IS7XX_LSR_TEMT_BIT      (1 << 6) /* Transmitter empty */
0179 #define SC16IS7XX_LSR_FIFOE_BIT     (1 << 7) /* Fifo Error */
0180 
0181 /* MSR register bits */
0182 #define SC16IS7XX_MSR_DCTS_BIT      (1 << 0) /* Delta CTS Clear To Send */
0183 #define SC16IS7XX_MSR_DDSR_BIT      (1 << 1) /* Delta DSR Data Set Ready
0184                           * or (IO4)
0185                           * - only on 75x/76x
0186                           */
0187 #define SC16IS7XX_MSR_DRI_BIT       (1 << 2) /* Delta RI Ring Indicator
0188                           * or (IO7)
0189                           * - only on 75x/76x
0190                           */
0191 #define SC16IS7XX_MSR_DCD_BIT       (1 << 3) /* Delta CD Carrier Detect
0192                           * or (IO6)
0193                           * - only on 75x/76x
0194                           */
0195 #define SC16IS7XX_MSR_CTS_BIT       (1 << 4) /* CTS */
0196 #define SC16IS7XX_MSR_DSR_BIT       (1 << 5) /* DSR (IO4)
0197                           * - only on 75x/76x
0198                           */
0199 #define SC16IS7XX_MSR_RI_BIT        (1 << 6) /* RI (IO7)
0200                           * - only on 75x/76x
0201                           */
0202 #define SC16IS7XX_MSR_CD_BIT        (1 << 7) /* CD (IO6)
0203                           * - only on 75x/76x
0204                           */
0205 #define SC16IS7XX_MSR_DELTA_MASK    0x0F     /* Any of the delta bits! */
0206 
0207 /*
0208  * TCR register bits
0209  * TCR trigger levels are available from 0 to 60 characters with a granularity
0210  * of four.
0211  * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
0212  * no built-in hardware check to make sure this condition is met. Also, the TCR
0213  * must be programmed with this condition before auto RTS or software flow
0214  * control is enabled to avoid spurious operation of the device.
0215  */
0216 #define SC16IS7XX_TCR_RX_HALT(words)    ((((words) / 4) & 0x0f) << 0)
0217 #define SC16IS7XX_TCR_RX_RESUME(words)  ((((words) / 4) & 0x0f) << 4)
0218 
0219 /*
0220  * TLR register bits
0221  * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
0222  * FIFO Control Register (FCR) are used for the transmit and receive FIFO
0223  * trigger levels. Trigger levels from 4 characters to 60 characters are
0224  * available with a granularity of four.
0225  *
0226  * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
0227  * trigger level setting defined in FCR. If TLR has non-zero trigger level value
0228  * the trigger level defined in FCR is discarded. This applies to both transmit
0229  * FIFO and receive FIFO trigger level setting.
0230  *
0231  * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
0232  * default state, that is, '00'.
0233  */
0234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
0235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
0236 
0237 /* IOControl register bits (Only 750/760) */
0238 #define SC16IS7XX_IOCONTROL_LATCH_BIT   (1 << 0) /* Enable input latching */
0239 #define SC16IS7XX_IOCONTROL_MODEM_BIT   (1 << 1) /* Enable GPIO[7:4] as modem pins */
0240 #define SC16IS7XX_IOCONTROL_SRESET_BIT  (1 << 3) /* Software Reset */
0241 
0242 /* EFCR register bits */
0243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT    (1 << 0) /* Enable 9-bit or Multidrop
0244                           * mode (RS485) */
0245 #define SC16IS7XX_EFCR_RXDISABLE_BIT    (1 << 1) /* Disable receiver */
0246 #define SC16IS7XX_EFCR_TXDISABLE_BIT    (1 << 2) /* Disable transmitter */
0247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT   (1 << 4) /* Auto RS485 RTS direction */
0248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT   (1 << 5) /* RTS output inversion */
0249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT    (1 << 7) /* IrDA mode
0250                           * 0 = rate upto 115.2 kbit/s
0251                           *   - Only 750/760
0252                           * 1 = rate upto 1.152 Mbit/s
0253                           *   - Only 760
0254                           */
0255 
0256 /* EFR register bits */
0257 #define SC16IS7XX_EFR_AUTORTS_BIT   (1 << 6) /* Auto RTS flow ctrl enable */
0258 #define SC16IS7XX_EFR_AUTOCTS_BIT   (1 << 7) /* Auto CTS flow ctrl enable */
0259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT  (1 << 5) /* Enable Xoff2 detection */
0260 #define SC16IS7XX_EFR_ENABLE_BIT    (1 << 4) /* Enable enhanced functions
0261                           * and writing to IER[7:4],
0262                           * FCR[5:4], MCR[7:5]
0263                           */
0264 #define SC16IS7XX_EFR_SWFLOW3_BIT   (1 << 3) /* SWFLOW bit 3 */
0265 #define SC16IS7XX_EFR_SWFLOW2_BIT   (1 << 2) /* SWFLOW bit 2
0266                           *
0267                           * SWFLOW bits 3 & 2 table:
0268                           * 00 -> no transmitter flow
0269                           *       control
0270                           * 01 -> transmitter generates
0271                           *       XON2 and XOFF2
0272                           * 10 -> transmitter generates
0273                           *       XON1 and XOFF1
0274                           * 11 -> transmitter generates
0275                           *       XON1, XON2, XOFF1 and
0276                           *       XOFF2
0277                           */
0278 #define SC16IS7XX_EFR_SWFLOW1_BIT   (1 << 1) /* SWFLOW bit 2 */
0279 #define SC16IS7XX_EFR_SWFLOW0_BIT   (1 << 0) /* SWFLOW bit 3
0280                           *
0281                           * SWFLOW bits 3 & 2 table:
0282                           * 00 -> no received flow
0283                           *       control
0284                           * 01 -> receiver compares
0285                           *       XON2 and XOFF2
0286                           * 10 -> receiver compares
0287                           *       XON1 and XOFF1
0288                           * 11 -> receiver compares
0289                           *       XON1, XON2, XOFF1 and
0290                           *       XOFF2
0291                           */
0292 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
0293                     SC16IS7XX_EFR_AUTOCTS_BIT | \
0294                     SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
0295                     SC16IS7XX_EFR_SWFLOW3_BIT | \
0296                     SC16IS7XX_EFR_SWFLOW2_BIT | \
0297                     SC16IS7XX_EFR_SWFLOW1_BIT | \
0298                     SC16IS7XX_EFR_SWFLOW0_BIT)
0299 
0300 
0301 /* Misc definitions */
0302 #define SC16IS7XX_FIFO_SIZE     (64)
0303 #define SC16IS7XX_REG_SHIFT     2
0304 
0305 struct sc16is7xx_devtype {
0306     char    name[10];
0307     int nr_gpio;
0308     int nr_uart;
0309     int has_mctrl;
0310 };
0311 
0312 #define SC16IS7XX_RECONF_MD     (1 << 0)
0313 #define SC16IS7XX_RECONF_IER        (1 << 1)
0314 #define SC16IS7XX_RECONF_RS485      (1 << 2)
0315 
0316 struct sc16is7xx_one_config {
0317     unsigned int            flags;
0318     u8              ier_mask;
0319     u8              ier_val;
0320 };
0321 
0322 struct sc16is7xx_one {
0323     struct uart_port        port;
0324     u8              line;
0325     struct kthread_work     tx_work;
0326     struct kthread_work     reg_work;
0327     struct kthread_delayed_work ms_work;
0328     struct sc16is7xx_one_config config;
0329     bool                irda_mode;
0330     unsigned int            old_mctrl;
0331 };
0332 
0333 struct sc16is7xx_port {
0334     const struct sc16is7xx_devtype  *devtype;
0335     struct regmap           *regmap;
0336     struct clk          *clk;
0337 #ifdef CONFIG_GPIOLIB
0338     struct gpio_chip        gpio;
0339 #endif
0340     unsigned char           buf[SC16IS7XX_FIFO_SIZE];
0341     struct kthread_worker       kworker;
0342     struct task_struct      *kworker_task;
0343     struct mutex            efr_lock;
0344     struct sc16is7xx_one        p[];
0345 };
0346 
0347 static unsigned long sc16is7xx_lines;
0348 
0349 static struct uart_driver sc16is7xx_uart = {
0350     .owner      = THIS_MODULE,
0351     .dev_name   = "ttySC",
0352     .nr     = SC16IS7XX_MAX_DEVS,
0353 };
0354 
0355 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
0356 static void sc16is7xx_stop_tx(struct uart_port *port);
0357 
0358 #define to_sc16is7xx_port(p,e)  ((container_of((p), struct sc16is7xx_port, e)))
0359 #define to_sc16is7xx_one(p,e)   ((container_of((p), struct sc16is7xx_one, e)))
0360 
0361 static int sc16is7xx_line(struct uart_port *port)
0362 {
0363     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0364 
0365     return one->line;
0366 }
0367 
0368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
0369 {
0370     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0371     unsigned int val = 0;
0372     const u8 line = sc16is7xx_line(port);
0373 
0374     regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
0375 
0376     return val;
0377 }
0378 
0379 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
0380 {
0381     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0382     const u8 line = sc16is7xx_line(port);
0383 
0384     regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
0385 }
0386 
0387 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
0388 {
0389     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0390     const u8 line = sc16is7xx_line(port);
0391     u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
0392 
0393     regcache_cache_bypass(s->regmap, true);
0394     regmap_raw_read(s->regmap, addr, s->buf, rxlen);
0395     regcache_cache_bypass(s->regmap, false);
0396 }
0397 
0398 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
0399 {
0400     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0401     const u8 line = sc16is7xx_line(port);
0402     u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
0403 
0404     /*
0405      * Don't send zero-length data, at least on SPI it confuses the chip
0406      * delivering wrong TXLVL data.
0407      */
0408     if (unlikely(!to_send))
0409         return;
0410 
0411     regcache_cache_bypass(s->regmap, true);
0412     regmap_raw_write(s->regmap, addr, s->buf, to_send);
0413     regcache_cache_bypass(s->regmap, false);
0414 }
0415 
0416 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
0417                   u8 mask, u8 val)
0418 {
0419     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0420     const u8 line = sc16is7xx_line(port);
0421 
0422     regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
0423                mask, val);
0424 }
0425 
0426 static int sc16is7xx_alloc_line(void)
0427 {
0428     int i;
0429 
0430     BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
0431 
0432     for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
0433         if (!test_and_set_bit(i, &sc16is7xx_lines))
0434             break;
0435 
0436     return i;
0437 }
0438 
0439 static void sc16is7xx_power(struct uart_port *port, int on)
0440 {
0441     sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
0442                   SC16IS7XX_IER_SLEEP_BIT,
0443                   on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
0444 }
0445 
0446 static const struct sc16is7xx_devtype sc16is74x_devtype = {
0447     .name       = "SC16IS74X",
0448     .nr_gpio    = 0,
0449     .nr_uart    = 1,
0450     .has_mctrl  = 0,
0451 };
0452 
0453 static const struct sc16is7xx_devtype sc16is750_devtype = {
0454     .name       = "SC16IS750",
0455     .nr_gpio    = 4,
0456     .nr_uart    = 1,
0457     .has_mctrl  = 1,
0458 };
0459 
0460 static const struct sc16is7xx_devtype sc16is752_devtype = {
0461     .name       = "SC16IS752",
0462     .nr_gpio    = 0,
0463     .nr_uart    = 2,
0464     .has_mctrl  = 1,
0465 };
0466 
0467 static const struct sc16is7xx_devtype sc16is760_devtype = {
0468     .name       = "SC16IS760",
0469     .nr_gpio    = 4,
0470     .nr_uart    = 1,
0471     .has_mctrl  = 1,
0472 };
0473 
0474 static const struct sc16is7xx_devtype sc16is762_devtype = {
0475     .name       = "SC16IS762",
0476     .nr_gpio    = 0,
0477     .nr_uart    = 2,
0478     .has_mctrl  = 1,
0479 };
0480 
0481 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
0482 {
0483     switch (reg >> SC16IS7XX_REG_SHIFT) {
0484     case SC16IS7XX_RHR_REG:
0485     case SC16IS7XX_IIR_REG:
0486     case SC16IS7XX_LSR_REG:
0487     case SC16IS7XX_MSR_REG:
0488     case SC16IS7XX_TXLVL_REG:
0489     case SC16IS7XX_RXLVL_REG:
0490     case SC16IS7XX_IOSTATE_REG:
0491         return true;
0492     default:
0493         break;
0494     }
0495 
0496     return false;
0497 }
0498 
0499 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
0500 {
0501     switch (reg >> SC16IS7XX_REG_SHIFT) {
0502     case SC16IS7XX_RHR_REG:
0503         return true;
0504     default:
0505         break;
0506     }
0507 
0508     return false;
0509 }
0510 
0511 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
0512 {
0513     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0514     u8 lcr;
0515     u8 prescaler = 0;
0516     unsigned long clk = port->uartclk, div = clk / 16 / baud;
0517 
0518     if (div > 0xffff) {
0519         prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
0520         div /= 4;
0521     }
0522 
0523     /* In an amazing feat of design, the Enhanced Features Register shares
0524      * the address of the Interrupt Identification Register, and is
0525      * switched in by writing a magic value (0xbf) to the Line Control
0526      * Register. Any interrupt firing during this time will see the EFR
0527      * where it expects the IIR to be, leading to "Unexpected interrupt"
0528      * messages.
0529      *
0530      * Prevent this possibility by claiming a mutex while accessing the
0531      * EFR, and claiming the same mutex from within the interrupt handler.
0532      * This is similar to disabling the interrupt, but that doesn't work
0533      * because the bulk of the interrupt processing is run as a workqueue
0534      * job in thread context.
0535      */
0536     mutex_lock(&s->efr_lock);
0537 
0538     lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
0539 
0540     /* Open the LCR divisors for configuration */
0541     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
0542                  SC16IS7XX_LCR_CONF_MODE_B);
0543 
0544     /* Enable enhanced features */
0545     regcache_cache_bypass(s->regmap, true);
0546     sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
0547                   SC16IS7XX_EFR_ENABLE_BIT,
0548                   SC16IS7XX_EFR_ENABLE_BIT);
0549 
0550     regcache_cache_bypass(s->regmap, false);
0551 
0552     /* Put LCR back to the normal mode */
0553     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
0554 
0555     mutex_unlock(&s->efr_lock);
0556 
0557     sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
0558                   SC16IS7XX_MCR_CLKSEL_BIT,
0559                   prescaler);
0560 
0561     /* Open the LCR divisors for configuration */
0562     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
0563                  SC16IS7XX_LCR_CONF_MODE_A);
0564 
0565     /* Write the new divisor */
0566     regcache_cache_bypass(s->regmap, true);
0567     sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
0568     sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
0569     regcache_cache_bypass(s->regmap, false);
0570 
0571     /* Put LCR back to the normal mode */
0572     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
0573 
0574     return DIV_ROUND_CLOSEST(clk / 16, div);
0575 }
0576 
0577 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
0578                 unsigned int iir)
0579 {
0580     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0581     unsigned int lsr = 0, ch, flag, bytes_read, i;
0582     bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
0583 
0584     if (unlikely(rxlen >= sizeof(s->buf))) {
0585         dev_warn_ratelimited(port->dev,
0586                      "ttySC%i: Possible RX FIFO overrun: %d\n",
0587                      port->line, rxlen);
0588         port->icount.buf_overrun++;
0589         /* Ensure sanity of RX level */
0590         rxlen = sizeof(s->buf);
0591     }
0592 
0593     while (rxlen) {
0594         /* Only read lsr if there are possible errors in FIFO */
0595         if (read_lsr) {
0596             lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
0597             if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
0598                 read_lsr = false; /* No errors left in FIFO */
0599         } else
0600             lsr = 0;
0601 
0602         if (read_lsr) {
0603             s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
0604             bytes_read = 1;
0605         } else {
0606             sc16is7xx_fifo_read(port, rxlen);
0607             bytes_read = rxlen;
0608         }
0609 
0610         lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
0611 
0612         port->icount.rx++;
0613         flag = TTY_NORMAL;
0614 
0615         if (unlikely(lsr)) {
0616             if (lsr & SC16IS7XX_LSR_BI_BIT) {
0617                 port->icount.brk++;
0618                 if (uart_handle_break(port))
0619                     continue;
0620             } else if (lsr & SC16IS7XX_LSR_PE_BIT)
0621                 port->icount.parity++;
0622             else if (lsr & SC16IS7XX_LSR_FE_BIT)
0623                 port->icount.frame++;
0624             else if (lsr & SC16IS7XX_LSR_OE_BIT)
0625                 port->icount.overrun++;
0626 
0627             lsr &= port->read_status_mask;
0628             if (lsr & SC16IS7XX_LSR_BI_BIT)
0629                 flag = TTY_BREAK;
0630             else if (lsr & SC16IS7XX_LSR_PE_BIT)
0631                 flag = TTY_PARITY;
0632             else if (lsr & SC16IS7XX_LSR_FE_BIT)
0633                 flag = TTY_FRAME;
0634             else if (lsr & SC16IS7XX_LSR_OE_BIT)
0635                 flag = TTY_OVERRUN;
0636         }
0637 
0638         for (i = 0; i < bytes_read; ++i) {
0639             ch = s->buf[i];
0640             if (uart_handle_sysrq_char(port, ch))
0641                 continue;
0642 
0643             if (lsr & port->ignore_status_mask)
0644                 continue;
0645 
0646             uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
0647                      flag);
0648         }
0649         rxlen -= bytes_read;
0650     }
0651 
0652     tty_flip_buffer_push(&port->state->port);
0653 }
0654 
0655 static void sc16is7xx_handle_tx(struct uart_port *port)
0656 {
0657     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0658     struct circ_buf *xmit = &port->state->xmit;
0659     unsigned int txlen, to_send, i;
0660     unsigned long flags;
0661 
0662     if (unlikely(port->x_char)) {
0663         sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
0664         port->icount.tx++;
0665         port->x_char = 0;
0666         return;
0667     }
0668 
0669     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0670         spin_lock_irqsave(&port->lock, flags);
0671         sc16is7xx_stop_tx(port);
0672         spin_unlock_irqrestore(&port->lock, flags);
0673         return;
0674     }
0675 
0676     /* Get length of data pending in circular buffer */
0677     to_send = uart_circ_chars_pending(xmit);
0678     if (likely(to_send)) {
0679         /* Limit to size of TX FIFO */
0680         txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
0681         if (txlen > SC16IS7XX_FIFO_SIZE) {
0682             dev_err_ratelimited(port->dev,
0683                 "chip reports %d free bytes in TX fifo, but it only has %d",
0684                 txlen, SC16IS7XX_FIFO_SIZE);
0685             txlen = 0;
0686         }
0687         to_send = (to_send > txlen) ? txlen : to_send;
0688 
0689         /* Add data to send */
0690         port->icount.tx += to_send;
0691 
0692         /* Convert to linear buffer */
0693         for (i = 0; i < to_send; ++i) {
0694             s->buf[i] = xmit->buf[xmit->tail];
0695             xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0696         }
0697 
0698         sc16is7xx_fifo_write(port, to_send);
0699     }
0700 
0701     spin_lock_irqsave(&port->lock, flags);
0702     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0703         uart_write_wakeup(port);
0704 
0705     if (uart_circ_empty(xmit))
0706         sc16is7xx_stop_tx(port);
0707     spin_unlock_irqrestore(&port->lock, flags);
0708 }
0709 
0710 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
0711 {
0712     u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
0713     unsigned int mctrl = 0;
0714 
0715     mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
0716     mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
0717     mctrl |= (msr & SC16IS7XX_MSR_CD_BIT)  ? TIOCM_CAR : 0;
0718     mctrl |= (msr & SC16IS7XX_MSR_RI_BIT)  ? TIOCM_RNG : 0;
0719     return mctrl;
0720 }
0721 
0722 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
0723 {
0724     struct uart_port *port = &one->port;
0725     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0726     unsigned long flags;
0727     unsigned int status, changed;
0728 
0729     lockdep_assert_held_once(&s->efr_lock);
0730 
0731     status = sc16is7xx_get_hwmctrl(port);
0732     changed = status ^ one->old_mctrl;
0733 
0734     if (changed == 0)
0735         return;
0736 
0737     one->old_mctrl = status;
0738 
0739     spin_lock_irqsave(&port->lock, flags);
0740     if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
0741         port->icount.rng++;
0742     if (changed & TIOCM_DSR)
0743         port->icount.dsr++;
0744     if (changed & TIOCM_CAR)
0745         uart_handle_dcd_change(port, status & TIOCM_CAR);
0746     if (changed & TIOCM_CTS)
0747         uart_handle_cts_change(port, status & TIOCM_CTS);
0748 
0749     wake_up_interruptible(&port->state->port.delta_msr_wait);
0750     spin_unlock_irqrestore(&port->lock, flags);
0751 }
0752 
0753 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
0754 {
0755     struct uart_port *port = &s->p[portno].port;
0756 
0757     do {
0758         unsigned int iir, rxlen;
0759         struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0760 
0761         iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
0762         if (iir & SC16IS7XX_IIR_NO_INT_BIT)
0763             return false;
0764 
0765         iir &= SC16IS7XX_IIR_ID_MASK;
0766 
0767         switch (iir) {
0768         case SC16IS7XX_IIR_RDI_SRC:
0769         case SC16IS7XX_IIR_RLSE_SRC:
0770         case SC16IS7XX_IIR_RTOI_SRC:
0771         case SC16IS7XX_IIR_XOFFI_SRC:
0772             rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
0773             if (rxlen)
0774                 sc16is7xx_handle_rx(port, rxlen, iir);
0775             break;
0776         /* CTSRTS interrupt comes only when CTS goes inactive */
0777         case SC16IS7XX_IIR_CTSRTS_SRC:
0778         case SC16IS7XX_IIR_MSI_SRC:
0779             sc16is7xx_update_mlines(one);
0780             break;
0781         case SC16IS7XX_IIR_THRI_SRC:
0782             sc16is7xx_handle_tx(port);
0783             break;
0784         default:
0785             dev_err_ratelimited(port->dev,
0786                         "ttySC%i: Unexpected interrupt: %x",
0787                         port->line, iir);
0788             break;
0789         }
0790     } while (0);
0791     return true;
0792 }
0793 
0794 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
0795 {
0796     struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
0797 
0798     mutex_lock(&s->efr_lock);
0799 
0800     while (1) {
0801         bool keep_polling = false;
0802         int i;
0803 
0804         for (i = 0; i < s->devtype->nr_uart; ++i)
0805             keep_polling |= sc16is7xx_port_irq(s, i);
0806         if (!keep_polling)
0807             break;
0808     }
0809 
0810     mutex_unlock(&s->efr_lock);
0811 
0812     return IRQ_HANDLED;
0813 }
0814 
0815 static void sc16is7xx_tx_proc(struct kthread_work *ws)
0816 {
0817     struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
0818     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0819     unsigned long flags;
0820 
0821     if ((port->rs485.flags & SER_RS485_ENABLED) &&
0822         (port->rs485.delay_rts_before_send > 0))
0823         msleep(port->rs485.delay_rts_before_send);
0824 
0825     mutex_lock(&s->efr_lock);
0826     sc16is7xx_handle_tx(port);
0827     mutex_unlock(&s->efr_lock);
0828 
0829     spin_lock_irqsave(&port->lock, flags);
0830     sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
0831     spin_unlock_irqrestore(&port->lock, flags);
0832 }
0833 
0834 static void sc16is7xx_reconf_rs485(struct uart_port *port)
0835 {
0836     const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
0837              SC16IS7XX_EFCR_RTS_INVERT_BIT;
0838     u32 efcr = 0;
0839     struct serial_rs485 *rs485 = &port->rs485;
0840     unsigned long irqflags;
0841 
0842     spin_lock_irqsave(&port->lock, irqflags);
0843     if (rs485->flags & SER_RS485_ENABLED) {
0844         efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
0845 
0846         if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
0847             efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
0848     }
0849     spin_unlock_irqrestore(&port->lock, irqflags);
0850 
0851     sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
0852 }
0853 
0854 static void sc16is7xx_reg_proc(struct kthread_work *ws)
0855 {
0856     struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
0857     struct sc16is7xx_one_config config;
0858     unsigned long irqflags;
0859 
0860     spin_lock_irqsave(&one->port.lock, irqflags);
0861     config = one->config;
0862     memset(&one->config, 0, sizeof(one->config));
0863     spin_unlock_irqrestore(&one->port.lock, irqflags);
0864 
0865     if (config.flags & SC16IS7XX_RECONF_MD) {
0866         u8 mcr = 0;
0867 
0868         /* Device ignores RTS setting when hardware flow is enabled */
0869         if (one->port.mctrl & TIOCM_RTS)
0870             mcr |= SC16IS7XX_MCR_RTS_BIT;
0871 
0872         if (one->port.mctrl & TIOCM_DTR)
0873             mcr |= SC16IS7XX_MCR_DTR_BIT;
0874 
0875         if (one->port.mctrl & TIOCM_LOOP)
0876             mcr |= SC16IS7XX_MCR_LOOP_BIT;
0877         sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
0878                       SC16IS7XX_MCR_RTS_BIT |
0879                       SC16IS7XX_MCR_DTR_BIT |
0880                       SC16IS7XX_MCR_LOOP_BIT,
0881                       mcr);
0882     }
0883 
0884     if (config.flags & SC16IS7XX_RECONF_IER)
0885         sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
0886                       config.ier_mask, config.ier_val);
0887 
0888     if (config.flags & SC16IS7XX_RECONF_RS485)
0889         sc16is7xx_reconf_rs485(&one->port);
0890 }
0891 
0892 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
0893 {
0894     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0895     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0896 
0897     lockdep_assert_held_once(&port->lock);
0898 
0899     one->config.flags |= SC16IS7XX_RECONF_IER;
0900     one->config.ier_mask |= bit;
0901     one->config.ier_val &= ~bit;
0902     kthread_queue_work(&s->kworker, &one->reg_work);
0903 }
0904 
0905 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
0906 {
0907     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0908     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0909 
0910     lockdep_assert_held_once(&port->lock);
0911 
0912     one->config.flags |= SC16IS7XX_RECONF_IER;
0913     one->config.ier_mask |= bit;
0914     one->config.ier_val |= bit;
0915     kthread_queue_work(&s->kworker, &one->reg_work);
0916 }
0917 
0918 static void sc16is7xx_stop_tx(struct uart_port *port)
0919 {
0920     sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
0921 }
0922 
0923 static void sc16is7xx_stop_rx(struct uart_port *port)
0924 {
0925     sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
0926 }
0927 
0928 static void sc16is7xx_ms_proc(struct kthread_work *ws)
0929 {
0930     struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
0931     struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
0932 
0933     if (one->port.state) {
0934         mutex_lock(&s->efr_lock);
0935         sc16is7xx_update_mlines(one);
0936         mutex_unlock(&s->efr_lock);
0937 
0938         kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
0939     }
0940 }
0941 
0942 static void sc16is7xx_enable_ms(struct uart_port *port)
0943 {
0944     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0945     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0946 
0947     lockdep_assert_held_once(&port->lock);
0948 
0949     kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
0950 }
0951 
0952 static void sc16is7xx_start_tx(struct uart_port *port)
0953 {
0954     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
0955     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0956 
0957     kthread_queue_work(&s->kworker, &one->tx_work);
0958 }
0959 
0960 static void sc16is7xx_throttle(struct uart_port *port)
0961 {
0962     unsigned long flags;
0963 
0964     /*
0965      * Hardware flow control is enabled and thus the device ignores RTS
0966      * value set in MCR register. Stop reading data from RX FIFO so the
0967      * AutoRTS feature will de-activate RTS output.
0968      */
0969     spin_lock_irqsave(&port->lock, flags);
0970     sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
0971     spin_unlock_irqrestore(&port->lock, flags);
0972 }
0973 
0974 static void sc16is7xx_unthrottle(struct uart_port *port)
0975 {
0976     unsigned long flags;
0977 
0978     spin_lock_irqsave(&port->lock, flags);
0979     sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
0980     spin_unlock_irqrestore(&port->lock, flags);
0981 }
0982 
0983 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
0984 {
0985     unsigned int lsr;
0986 
0987     lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
0988 
0989     return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
0990 }
0991 
0992 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
0993 {
0994     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
0995 
0996     /* Called with port lock taken so we can only return cached value */
0997     return one->old_mctrl;
0998 }
0999 
1000 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
1001 {
1002     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1003     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1004 
1005     one->config.flags |= SC16IS7XX_RECONF_MD;
1006     kthread_queue_work(&s->kworker, &one->reg_work);
1007 }
1008 
1009 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1010 {
1011     sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1012                   SC16IS7XX_LCR_TXBREAK_BIT,
1013                   break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1014 }
1015 
1016 static void sc16is7xx_set_termios(struct uart_port *port,
1017                   struct ktermios *termios,
1018                   struct ktermios *old)
1019 {
1020     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1021     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1022     unsigned int lcr, flow = 0;
1023     int baud;
1024     unsigned long flags;
1025 
1026     kthread_cancel_delayed_work_sync(&one->ms_work);
1027 
1028     /* Mask termios capabilities we don't support */
1029     termios->c_cflag &= ~CMSPAR;
1030 
1031     /* Word size */
1032     switch (termios->c_cflag & CSIZE) {
1033     case CS5:
1034         lcr = SC16IS7XX_LCR_WORD_LEN_5;
1035         break;
1036     case CS6:
1037         lcr = SC16IS7XX_LCR_WORD_LEN_6;
1038         break;
1039     case CS7:
1040         lcr = SC16IS7XX_LCR_WORD_LEN_7;
1041         break;
1042     case CS8:
1043         lcr = SC16IS7XX_LCR_WORD_LEN_8;
1044         break;
1045     default:
1046         lcr = SC16IS7XX_LCR_WORD_LEN_8;
1047         termios->c_cflag &= ~CSIZE;
1048         termios->c_cflag |= CS8;
1049         break;
1050     }
1051 
1052     /* Parity */
1053     if (termios->c_cflag & PARENB) {
1054         lcr |= SC16IS7XX_LCR_PARITY_BIT;
1055         if (!(termios->c_cflag & PARODD))
1056             lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1057     }
1058 
1059     /* Stop bits */
1060     if (termios->c_cflag & CSTOPB)
1061         lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1062 
1063     /* Set read status mask */
1064     port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1065     if (termios->c_iflag & INPCK)
1066         port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1067                       SC16IS7XX_LSR_FE_BIT;
1068     if (termios->c_iflag & (BRKINT | PARMRK))
1069         port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1070 
1071     /* Set status ignore mask */
1072     port->ignore_status_mask = 0;
1073     if (termios->c_iflag & IGNBRK)
1074         port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1075     if (!(termios->c_cflag & CREAD))
1076         port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1077 
1078     /* As above, claim the mutex while accessing the EFR. */
1079     mutex_lock(&s->efr_lock);
1080 
1081     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1082                  SC16IS7XX_LCR_CONF_MODE_B);
1083 
1084     /* Configure flow control */
1085     regcache_cache_bypass(s->regmap, true);
1086     sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1087     sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1088 
1089     port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1090     if (termios->c_cflag & CRTSCTS) {
1091         flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1092             SC16IS7XX_EFR_AUTORTS_BIT;
1093         port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1094     }
1095     if (termios->c_iflag & IXON)
1096         flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1097     if (termios->c_iflag & IXOFF)
1098         flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1099 
1100     sc16is7xx_port_update(port,
1101                   SC16IS7XX_EFR_REG,
1102                   SC16IS7XX_EFR_FLOWCTRL_BITS,
1103                   flow);
1104     regcache_cache_bypass(s->regmap, false);
1105 
1106     /* Update LCR register */
1107     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1108 
1109     mutex_unlock(&s->efr_lock);
1110 
1111     /* Get baud rate generator configuration */
1112     baud = uart_get_baud_rate(port, termios, old,
1113                   port->uartclk / 16 / 4 / 0xffff,
1114                   port->uartclk / 16);
1115 
1116     /* Setup baudrate generator */
1117     baud = sc16is7xx_set_baud(port, baud);
1118 
1119     spin_lock_irqsave(&port->lock, flags);
1120 
1121     /* Update timeout according to new baud rate */
1122     uart_update_timeout(port, termios->c_cflag, baud);
1123 
1124     if (UART_ENABLE_MS(port, termios->c_cflag))
1125         sc16is7xx_enable_ms(port);
1126 
1127     spin_unlock_irqrestore(&port->lock, flags);
1128 }
1129 
1130 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1131                   struct serial_rs485 *rs485)
1132 {
1133     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1134     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1135 
1136     if (rs485->flags & SER_RS485_ENABLED) {
1137         /*
1138          * RTS signal is handled by HW, it's timing can't be influenced.
1139          * However, it's sometimes useful to delay TX even without RTS
1140          * control therefore we try to handle .delay_rts_before_send.
1141          */
1142         if (rs485->delay_rts_after_send)
1143             return -EINVAL;
1144     }
1145 
1146     one->config.flags |= SC16IS7XX_RECONF_RS485;
1147     kthread_queue_work(&s->kworker, &one->reg_work);
1148 
1149     return 0;
1150 }
1151 
1152 static int sc16is7xx_startup(struct uart_port *port)
1153 {
1154     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1155     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1156     unsigned int val;
1157     unsigned long flags;
1158 
1159     sc16is7xx_power(port, 1);
1160 
1161     /* Reset FIFOs*/
1162     val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1163     sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1164     udelay(5);
1165     sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1166                  SC16IS7XX_FCR_FIFO_BIT);
1167 
1168     /* Enable EFR */
1169     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1170                  SC16IS7XX_LCR_CONF_MODE_B);
1171 
1172     regcache_cache_bypass(s->regmap, true);
1173 
1174     /* Enable write access to enhanced features and internal clock div */
1175     sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1176                   SC16IS7XX_EFR_ENABLE_BIT,
1177                   SC16IS7XX_EFR_ENABLE_BIT);
1178 
1179     /* Enable TCR/TLR */
1180     sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1181                   SC16IS7XX_MCR_TCRTLR_BIT,
1182                   SC16IS7XX_MCR_TCRTLR_BIT);
1183 
1184     /* Configure flow control levels */
1185     /* Flow control halt level 48, resume level 24 */
1186     sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1187                  SC16IS7XX_TCR_RX_RESUME(24) |
1188                  SC16IS7XX_TCR_RX_HALT(48));
1189 
1190     regcache_cache_bypass(s->regmap, false);
1191 
1192     /* Now, initialize the UART */
1193     sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1194 
1195     /* Enable IrDA mode if requested in DT */
1196     /* This bit must be written with LCR[7] = 0 */
1197     sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1198                   SC16IS7XX_MCR_IRDA_BIT,
1199                   one->irda_mode ?
1200                 SC16IS7XX_MCR_IRDA_BIT : 0);
1201 
1202     /* Enable the Rx and Tx FIFO */
1203     sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1204                   SC16IS7XX_EFCR_RXDISABLE_BIT |
1205                   SC16IS7XX_EFCR_TXDISABLE_BIT,
1206                   0);
1207 
1208     /* Enable RX, CTS change and modem lines interrupts */
1209     val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1210           SC16IS7XX_IER_MSI_BIT;
1211     sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1212 
1213     /* Enable modem status polling */
1214     spin_lock_irqsave(&port->lock, flags);
1215     sc16is7xx_enable_ms(port);
1216     spin_unlock_irqrestore(&port->lock, flags);
1217 
1218     return 0;
1219 }
1220 
1221 static void sc16is7xx_shutdown(struct uart_port *port)
1222 {
1223     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1224     struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1225 
1226     kthread_cancel_delayed_work_sync(&one->ms_work);
1227 
1228     /* Disable all interrupts */
1229     sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1230     /* Disable TX/RX */
1231     sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1232                   SC16IS7XX_EFCR_RXDISABLE_BIT |
1233                   SC16IS7XX_EFCR_TXDISABLE_BIT,
1234                   SC16IS7XX_EFCR_RXDISABLE_BIT |
1235                   SC16IS7XX_EFCR_TXDISABLE_BIT);
1236 
1237     sc16is7xx_power(port, 0);
1238 
1239     kthread_flush_worker(&s->kworker);
1240 }
1241 
1242 static const char *sc16is7xx_type(struct uart_port *port)
1243 {
1244     struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1245 
1246     return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1247 }
1248 
1249 static int sc16is7xx_request_port(struct uart_port *port)
1250 {
1251     /* Do nothing */
1252     return 0;
1253 }
1254 
1255 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1256 {
1257     if (flags & UART_CONFIG_TYPE)
1258         port->type = PORT_SC16IS7XX;
1259 }
1260 
1261 static int sc16is7xx_verify_port(struct uart_port *port,
1262                  struct serial_struct *s)
1263 {
1264     if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1265         return -EINVAL;
1266     if (s->irq != port->irq)
1267         return -EINVAL;
1268 
1269     return 0;
1270 }
1271 
1272 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1273              unsigned int oldstate)
1274 {
1275     sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1276 }
1277 
1278 static void sc16is7xx_null_void(struct uart_port *port)
1279 {
1280     /* Do nothing */
1281 }
1282 
1283 static const struct uart_ops sc16is7xx_ops = {
1284     .tx_empty   = sc16is7xx_tx_empty,
1285     .set_mctrl  = sc16is7xx_set_mctrl,
1286     .get_mctrl  = sc16is7xx_get_mctrl,
1287     .stop_tx    = sc16is7xx_stop_tx,
1288     .start_tx   = sc16is7xx_start_tx,
1289     .throttle   = sc16is7xx_throttle,
1290     .unthrottle = sc16is7xx_unthrottle,
1291     .stop_rx    = sc16is7xx_stop_rx,
1292     .enable_ms  = sc16is7xx_enable_ms,
1293     .break_ctl  = sc16is7xx_break_ctl,
1294     .startup    = sc16is7xx_startup,
1295     .shutdown   = sc16is7xx_shutdown,
1296     .set_termios    = sc16is7xx_set_termios,
1297     .type       = sc16is7xx_type,
1298     .request_port   = sc16is7xx_request_port,
1299     .release_port   = sc16is7xx_null_void,
1300     .config_port    = sc16is7xx_config_port,
1301     .verify_port    = sc16is7xx_verify_port,
1302     .pm     = sc16is7xx_pm,
1303 };
1304 
1305 #ifdef CONFIG_GPIOLIB
1306 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1307 {
1308     unsigned int val;
1309     struct sc16is7xx_port *s = gpiochip_get_data(chip);
1310     struct uart_port *port = &s->p[0].port;
1311 
1312     val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1313 
1314     return !!(val & BIT(offset));
1315 }
1316 
1317 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1318 {
1319     struct sc16is7xx_port *s = gpiochip_get_data(chip);
1320     struct uart_port *port = &s->p[0].port;
1321 
1322     sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1323                   val ? BIT(offset) : 0);
1324 }
1325 
1326 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1327                       unsigned offset)
1328 {
1329     struct sc16is7xx_port *s = gpiochip_get_data(chip);
1330     struct uart_port *port = &s->p[0].port;
1331 
1332     sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1333 
1334     return 0;
1335 }
1336 
1337 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1338                        unsigned offset, int val)
1339 {
1340     struct sc16is7xx_port *s = gpiochip_get_data(chip);
1341     struct uart_port *port = &s->p[0].port;
1342     u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1343 
1344     if (val)
1345         state |= BIT(offset);
1346     else
1347         state &= ~BIT(offset);
1348     sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1349     sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1350                   BIT(offset));
1351 
1352     return 0;
1353 }
1354 #endif
1355 
1356 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1357     .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1358     .delay_rts_before_send = 1,
1359     .delay_rts_after_send = 1,  /* Not supported but keep returning -EINVAL */
1360 };
1361 
1362 static int sc16is7xx_probe(struct device *dev,
1363                const struct sc16is7xx_devtype *devtype,
1364                struct regmap *regmap, int irq)
1365 {
1366     unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1367     unsigned int val;
1368     u32 uartclk = 0;
1369     int i, ret;
1370     struct sc16is7xx_port *s;
1371 
1372     if (IS_ERR(regmap))
1373         return PTR_ERR(regmap);
1374 
1375     /*
1376      * This device does not have an identification register that would
1377      * tell us if we are really connected to the correct device.
1378      * The best we can do is to check if communication is at all possible.
1379      */
1380     ret = regmap_read(regmap,
1381               SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1382     if (ret < 0)
1383         return -EPROBE_DEFER;
1384 
1385     /* Alloc port structure */
1386     s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1387     if (!s) {
1388         dev_err(dev, "Error allocating port structure\n");
1389         return -ENOMEM;
1390     }
1391 
1392     /* Always ask for fixed clock rate from a property. */
1393     device_property_read_u32(dev, "clock-frequency", &uartclk);
1394 
1395     s->clk = devm_clk_get_optional(dev, NULL);
1396     if (IS_ERR(s->clk))
1397         return PTR_ERR(s->clk);
1398 
1399     ret = clk_prepare_enable(s->clk);
1400     if (ret)
1401         return ret;
1402 
1403     freq = clk_get_rate(s->clk);
1404     if (freq == 0) {
1405         if (uartclk)
1406             freq = uartclk;
1407         if (pfreq)
1408             freq = *pfreq;
1409         if (freq)
1410             dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1411         else
1412             return -EINVAL;
1413     }
1414 
1415     s->regmap = regmap;
1416     s->devtype = devtype;
1417     dev_set_drvdata(dev, s);
1418     mutex_init(&s->efr_lock);
1419 
1420     kthread_init_worker(&s->kworker);
1421     s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1422                       "sc16is7xx");
1423     if (IS_ERR(s->kworker_task)) {
1424         ret = PTR_ERR(s->kworker_task);
1425         goto out_clk;
1426     }
1427     sched_set_fifo(s->kworker_task);
1428 
1429 #ifdef CONFIG_GPIOLIB
1430     if (devtype->nr_gpio) {
1431         /* Setup GPIO cotroller */
1432         s->gpio.owner        = THIS_MODULE;
1433         s->gpio.parent       = dev;
1434         s->gpio.label        = dev_name(dev);
1435         s->gpio.direction_input  = sc16is7xx_gpio_direction_input;
1436         s->gpio.get      = sc16is7xx_gpio_get;
1437         s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1438         s->gpio.set      = sc16is7xx_gpio_set;
1439         s->gpio.base         = -1;
1440         s->gpio.ngpio        = devtype->nr_gpio;
1441         s->gpio.can_sleep    = 1;
1442         ret = gpiochip_add_data(&s->gpio, s);
1443         if (ret)
1444             goto out_thread;
1445     }
1446 #endif
1447 
1448     /* reset device, purging any pending irq / data */
1449     regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1450             SC16IS7XX_IOCONTROL_SRESET_BIT);
1451 
1452     for (i = 0; i < devtype->nr_uart; ++i) {
1453         s->p[i].line        = i;
1454         /* Initialize port data */
1455         s->p[i].port.dev    = dev;
1456         s->p[i].port.irq    = irq;
1457         s->p[i].port.type   = PORT_SC16IS7XX;
1458         s->p[i].port.fifosize   = SC16IS7XX_FIFO_SIZE;
1459         s->p[i].port.flags  = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1460         s->p[i].port.iobase = i;
1461         s->p[i].port.iotype = UPIO_PORT;
1462         s->p[i].port.uartclk    = freq;
1463         s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1464         s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1465         s->p[i].port.ops    = &sc16is7xx_ops;
1466         s->p[i].old_mctrl   = 0;
1467         s->p[i].port.line   = sc16is7xx_alloc_line();
1468 
1469         if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1470             ret = -ENOMEM;
1471             goto out_ports;
1472         }
1473 
1474         /* Disable all interrupts */
1475         sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1476         /* Disable TX/RX */
1477         sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1478                      SC16IS7XX_EFCR_RXDISABLE_BIT |
1479                      SC16IS7XX_EFCR_TXDISABLE_BIT);
1480 
1481         /* Use GPIO lines as modem status registers */
1482         if (devtype->has_mctrl)
1483             sc16is7xx_port_write(&s->p[i].port,
1484                          SC16IS7XX_IOCONTROL_REG,
1485                          SC16IS7XX_IOCONTROL_MODEM_BIT);
1486 
1487         /* Initialize kthread work structs */
1488         kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1489         kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1490         kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1491         /* Register port */
1492         uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1493 
1494         /* Enable EFR */
1495         sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1496                      SC16IS7XX_LCR_CONF_MODE_B);
1497 
1498         regcache_cache_bypass(s->regmap, true);
1499 
1500         /* Enable write access to enhanced features */
1501         sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1502                      SC16IS7XX_EFR_ENABLE_BIT);
1503 
1504         regcache_cache_bypass(s->regmap, false);
1505 
1506         /* Restore access to general registers */
1507         sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1508 
1509         /* Go to suspend mode */
1510         sc16is7xx_power(&s->p[i].port, 0);
1511     }
1512 
1513     if (dev->of_node) {
1514         struct property *prop;
1515         const __be32 *p;
1516         u32 u;
1517 
1518         of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1519                      prop, p, u)
1520             if (u < devtype->nr_uart)
1521                 s->p[u].irda_mode = true;
1522     }
1523 
1524     /*
1525      * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1526      * If that succeeds, we can allow sharing the interrupt as well.
1527      * In case the interrupt controller doesn't support that, we fall
1528      * back to a non-shared falling-edge trigger.
1529      */
1530     ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1531                     IRQF_TRIGGER_LOW | IRQF_SHARED |
1532                     IRQF_ONESHOT,
1533                     dev_name(dev), s);
1534     if (!ret)
1535         return 0;
1536 
1537     ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1538                     IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1539                     dev_name(dev), s);
1540     if (!ret)
1541         return 0;
1542 
1543 out_ports:
1544     for (i--; i >= 0; i--) {
1545         uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1546         clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1547     }
1548 
1549 #ifdef CONFIG_GPIOLIB
1550     if (devtype->nr_gpio)
1551         gpiochip_remove(&s->gpio);
1552 
1553 out_thread:
1554 #endif
1555     kthread_stop(s->kworker_task);
1556 
1557 out_clk:
1558     clk_disable_unprepare(s->clk);
1559 
1560     return ret;
1561 }
1562 
1563 static void sc16is7xx_remove(struct device *dev)
1564 {
1565     struct sc16is7xx_port *s = dev_get_drvdata(dev);
1566     int i;
1567 
1568 #ifdef CONFIG_GPIOLIB
1569     if (s->devtype->nr_gpio)
1570         gpiochip_remove(&s->gpio);
1571 #endif
1572 
1573     for (i = 0; i < s->devtype->nr_uart; i++) {
1574         kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1575         uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1576         clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1577         sc16is7xx_power(&s->p[i].port, 0);
1578     }
1579 
1580     kthread_flush_worker(&s->kworker);
1581     kthread_stop(s->kworker_task);
1582 
1583     clk_disable_unprepare(s->clk);
1584 }
1585 
1586 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1587     { .compatible = "nxp,sc16is740",    .data = &sc16is74x_devtype, },
1588     { .compatible = "nxp,sc16is741",    .data = &sc16is74x_devtype, },
1589     { .compatible = "nxp,sc16is750",    .data = &sc16is750_devtype, },
1590     { .compatible = "nxp,sc16is752",    .data = &sc16is752_devtype, },
1591     { .compatible = "nxp,sc16is760",    .data = &sc16is760_devtype, },
1592     { .compatible = "nxp,sc16is762",    .data = &sc16is762_devtype, },
1593     { }
1594 };
1595 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1596 
1597 static struct regmap_config regcfg = {
1598     .reg_bits = 7,
1599     .pad_bits = 1,
1600     .val_bits = 8,
1601     .cache_type = REGCACHE_RBTREE,
1602     .volatile_reg = sc16is7xx_regmap_volatile,
1603     .precious_reg = sc16is7xx_regmap_precious,
1604 };
1605 
1606 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1607 static int sc16is7xx_spi_probe(struct spi_device *spi)
1608 {
1609     const struct sc16is7xx_devtype *devtype;
1610     struct regmap *regmap;
1611     int ret;
1612 
1613     /* Setup SPI bus */
1614     spi->bits_per_word  = 8;
1615     /* only supports mode 0 on SC16IS762 */
1616     spi->mode       = spi->mode ? : SPI_MODE_0;
1617     spi->max_speed_hz   = spi->max_speed_hz ? : 15000000;
1618     ret = spi_setup(spi);
1619     if (ret)
1620         return ret;
1621 
1622     if (spi->dev.of_node) {
1623         devtype = device_get_match_data(&spi->dev);
1624         if (!devtype)
1625             return -ENODEV;
1626     } else {
1627         const struct spi_device_id *id_entry = spi_get_device_id(spi);
1628 
1629         devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1630     }
1631 
1632     regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1633                   (devtype->nr_uart - 1);
1634     regmap = devm_regmap_init_spi(spi, &regcfg);
1635 
1636     return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1637 }
1638 
1639 static void sc16is7xx_spi_remove(struct spi_device *spi)
1640 {
1641     sc16is7xx_remove(&spi->dev);
1642 }
1643 
1644 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1645     { "sc16is74x",  (kernel_ulong_t)&sc16is74x_devtype, },
1646     { "sc16is740",  (kernel_ulong_t)&sc16is74x_devtype, },
1647     { "sc16is741",  (kernel_ulong_t)&sc16is74x_devtype, },
1648     { "sc16is750",  (kernel_ulong_t)&sc16is750_devtype, },
1649     { "sc16is752",  (kernel_ulong_t)&sc16is752_devtype, },
1650     { "sc16is760",  (kernel_ulong_t)&sc16is760_devtype, },
1651     { "sc16is762",  (kernel_ulong_t)&sc16is762_devtype, },
1652     { }
1653 };
1654 
1655 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1656 
1657 static struct spi_driver sc16is7xx_spi_uart_driver = {
1658     .driver = {
1659         .name       = SC16IS7XX_NAME,
1660         .of_match_table = sc16is7xx_dt_ids,
1661     },
1662     .probe      = sc16is7xx_spi_probe,
1663     .remove     = sc16is7xx_spi_remove,
1664     .id_table   = sc16is7xx_spi_id_table,
1665 };
1666 
1667 MODULE_ALIAS("spi:sc16is7xx");
1668 #endif
1669 
1670 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1671 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1672                    const struct i2c_device_id *id)
1673 {
1674     const struct sc16is7xx_devtype *devtype;
1675     struct regmap *regmap;
1676 
1677     if (i2c->dev.of_node) {
1678         devtype = device_get_match_data(&i2c->dev);
1679         if (!devtype)
1680             return -ENODEV;
1681     } else {
1682         devtype = (struct sc16is7xx_devtype *)id->driver_data;
1683     }
1684 
1685     regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1686                   (devtype->nr_uart - 1);
1687     regmap = devm_regmap_init_i2c(i2c, &regcfg);
1688 
1689     return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1690 }
1691 
1692 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1693 {
1694     sc16is7xx_remove(&client->dev);
1695 
1696     return 0;
1697 }
1698 
1699 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1700     { "sc16is74x",  (kernel_ulong_t)&sc16is74x_devtype, },
1701     { "sc16is740",  (kernel_ulong_t)&sc16is74x_devtype, },
1702     { "sc16is741",  (kernel_ulong_t)&sc16is74x_devtype, },
1703     { "sc16is750",  (kernel_ulong_t)&sc16is750_devtype, },
1704     { "sc16is752",  (kernel_ulong_t)&sc16is752_devtype, },
1705     { "sc16is760",  (kernel_ulong_t)&sc16is760_devtype, },
1706     { "sc16is762",  (kernel_ulong_t)&sc16is762_devtype, },
1707     { }
1708 };
1709 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1710 
1711 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1712     .driver = {
1713         .name       = SC16IS7XX_NAME,
1714         .of_match_table = sc16is7xx_dt_ids,
1715     },
1716     .probe      = sc16is7xx_i2c_probe,
1717     .remove     = sc16is7xx_i2c_remove,
1718     .id_table   = sc16is7xx_i2c_id_table,
1719 };
1720 
1721 #endif
1722 
1723 static int __init sc16is7xx_init(void)
1724 {
1725     int ret;
1726 
1727     ret = uart_register_driver(&sc16is7xx_uart);
1728     if (ret) {
1729         pr_err("Registering UART driver failed\n");
1730         return ret;
1731     }
1732 
1733 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1734     ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1735     if (ret < 0) {
1736         pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1737         goto err_i2c;
1738     }
1739 #endif
1740 
1741 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1742     ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1743     if (ret < 0) {
1744         pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1745         goto err_spi;
1746     }
1747 #endif
1748     return ret;
1749 
1750 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1751 err_spi:
1752 #endif
1753 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1754     i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1755 err_i2c:
1756 #endif
1757     uart_unregister_driver(&sc16is7xx_uart);
1758     return ret;
1759 }
1760 module_init(sc16is7xx_init);
1761 
1762 static void __exit sc16is7xx_exit(void)
1763 {
1764 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1765     i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1766 #endif
1767 
1768 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1769     spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1770 #endif
1771     uart_unregister_driver(&sc16is7xx_uart);
1772 }
1773 module_exit(sc16is7xx_exit);
1774 
1775 MODULE_LICENSE("GPL");
1776 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1777 MODULE_DESCRIPTION("SC16IS7XX serial driver");
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