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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Support for the asynchronous serial interface (DUART) included
0004  *  in the BCM1250 and derived System-On-a-Chip (SOC) devices.
0005  *
0006  *  Copyright (c) 2007  Maciej W. Rozycki
0007  *
0008  *  Derived from drivers/char/sb1250_duart.c for which the following
0009  *  copyright applies:
0010  *
0011  *  Copyright (c) 2000, 2001, 2002, 2003, 2004  Broadcom Corporation
0012  *
0013  *  References:
0014  *
0015  *  "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
0016  */
0017 
0018 #include <linux/compiler.h>
0019 #include <linux/console.h>
0020 #include <linux/delay.h>
0021 #include <linux/errno.h>
0022 #include <linux/init.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/ioport.h>
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/major.h>
0028 #include <linux/serial.h>
0029 #include <linux/serial_core.h>
0030 #include <linux/spinlock.h>
0031 #include <linux/sysrq.h>
0032 #include <linux/tty.h>
0033 #include <linux/tty_flip.h>
0034 #include <linux/types.h>
0035 
0036 #include <linux/refcount.h>
0037 #include <linux/io.h>
0038 
0039 #include <asm/sibyte/sb1250.h>
0040 #include <asm/sibyte/sb1250_uart.h>
0041 #include <asm/sibyte/swarm.h>
0042 
0043 
0044 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0045 #include <asm/sibyte/bcm1480_regs.h>
0046 #include <asm/sibyte/bcm1480_int.h>
0047 
0048 #define SBD_CHANREGS(line)  A_BCM1480_DUART_CHANREG((line), 0)
0049 #define SBD_CTRLREGS(line)  A_BCM1480_DUART_CTRLREG((line), 0)
0050 #define SBD_INT(line)       (K_BCM1480_INT_UART_0 + (line))
0051 
0052 #define DUART_CHANREG_SPACING   BCM1480_DUART_CHANREG_SPACING
0053 
0054 #define R_DUART_IMRREG(line)    R_BCM1480_DUART_IMRREG(line)
0055 #define R_DUART_INCHREG(line)   R_BCM1480_DUART_INCHREG(line)
0056 #define R_DUART_ISRREG(line)    R_BCM1480_DUART_ISRREG(line)
0057 
0058 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
0059 #include <asm/sibyte/sb1250_regs.h>
0060 #include <asm/sibyte/sb1250_int.h>
0061 
0062 #define SBD_CHANREGS(line)  A_DUART_CHANREG((line), 0)
0063 #define SBD_CTRLREGS(line)  A_DUART_CTRLREG(0)
0064 #define SBD_INT(line)       (K_INT_UART_0 + (line))
0065 
0066 #else
0067 #error invalid SB1250 UART configuration
0068 
0069 #endif
0070 
0071 
0072 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
0073 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
0074 MODULE_LICENSE("GPL");
0075 
0076 
0077 #define DUART_MAX_CHIP 2
0078 #define DUART_MAX_SIDE 2
0079 
0080 /*
0081  * Per-port state.
0082  */
0083 struct sbd_port {
0084     struct sbd_duart    *duart;
0085     struct uart_port    port;
0086     unsigned char __iomem   *memctrl;
0087     int         tx_stopped;
0088     int         initialised;
0089 };
0090 
0091 /*
0092  * Per-DUART state for the shared register space.
0093  */
0094 struct sbd_duart {
0095     struct sbd_port     sport[2];
0096     unsigned long       mapctrl;
0097     refcount_t      map_guard;
0098 };
0099 
0100 #define to_sport(uport) container_of(uport, struct sbd_port, port)
0101 
0102 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
0103 
0104 
0105 /*
0106  * Reading and writing SB1250 DUART registers.
0107  *
0108  * There are three register spaces: two per-channel ones and
0109  * a shared one.  We have to define accessors appropriately.
0110  * All registers are 64-bit and all but the Baud Rate Clock
0111  * registers only define 8 least significant bits.  There is
0112  * also a workaround to take into account.  Raw accessors use
0113  * the full register width, but cooked ones truncate it
0114  * intentionally so that the rest of the driver does not care.
0115  */
0116 static u64 __read_sbdchn(struct sbd_port *sport, int reg)
0117 {
0118     void __iomem *csr = sport->port.membase + reg;
0119 
0120     return __raw_readq(csr);
0121 }
0122 
0123 static u64 __read_sbdshr(struct sbd_port *sport, int reg)
0124 {
0125     void __iomem *csr = sport->memctrl + reg;
0126 
0127     return __raw_readq(csr);
0128 }
0129 
0130 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
0131 {
0132     void __iomem *csr = sport->port.membase + reg;
0133 
0134     __raw_writeq(value, csr);
0135 }
0136 
0137 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
0138 {
0139     void __iomem *csr = sport->memctrl + reg;
0140 
0141     __raw_writeq(value, csr);
0142 }
0143 
0144 /*
0145  * In bug 1956, we get glitches that can mess up uart registers.  This
0146  * "read-mode-reg after any register access" is an accepted workaround.
0147  */
0148 static void __war_sbd1956(struct sbd_port *sport)
0149 {
0150     __read_sbdchn(sport, R_DUART_MODE_REG_1);
0151     __read_sbdchn(sport, R_DUART_MODE_REG_2);
0152 }
0153 
0154 static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
0155 {
0156     unsigned char retval;
0157 
0158     retval = __read_sbdchn(sport, reg);
0159     if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
0160         __war_sbd1956(sport);
0161     return retval;
0162 }
0163 
0164 static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
0165 {
0166     unsigned char retval;
0167 
0168     retval = __read_sbdshr(sport, reg);
0169     if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
0170         __war_sbd1956(sport);
0171     return retval;
0172 }
0173 
0174 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
0175 {
0176     __write_sbdchn(sport, reg, value);
0177     if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
0178         __war_sbd1956(sport);
0179 }
0180 
0181 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
0182 {
0183     __write_sbdshr(sport, reg, value);
0184     if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
0185         __war_sbd1956(sport);
0186 }
0187 
0188 
0189 static int sbd_receive_ready(struct sbd_port *sport)
0190 {
0191     return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
0192 }
0193 
0194 static int sbd_receive_drain(struct sbd_port *sport)
0195 {
0196     int loops = 10000;
0197 
0198     while (sbd_receive_ready(sport) && --loops)
0199         read_sbdchn(sport, R_DUART_RX_HOLD);
0200     return loops;
0201 }
0202 
0203 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
0204 {
0205     return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
0206 }
0207 
0208 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
0209 {
0210     int loops = 10000;
0211 
0212     while (!sbd_transmit_ready(sport) && --loops)
0213         udelay(2);
0214     return loops;
0215 }
0216 
0217 static int sbd_transmit_empty(struct sbd_port *sport)
0218 {
0219     return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
0220 }
0221 
0222 static int sbd_line_drain(struct sbd_port *sport)
0223 {
0224     int loops = 10000;
0225 
0226     while (!sbd_transmit_empty(sport) && --loops)
0227         udelay(2);
0228     return loops;
0229 }
0230 
0231 
0232 static unsigned int sbd_tx_empty(struct uart_port *uport)
0233 {
0234     struct sbd_port *sport = to_sport(uport);
0235 
0236     return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
0237 }
0238 
0239 static unsigned int sbd_get_mctrl(struct uart_port *uport)
0240 {
0241     struct sbd_port *sport = to_sport(uport);
0242     unsigned int mctrl, status;
0243 
0244     status = read_sbdshr(sport, R_DUART_IN_PORT);
0245     status >>= (uport->line) % 2;
0246     mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
0247         (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
0248         (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
0249         (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
0250     return mctrl;
0251 }
0252 
0253 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
0254 {
0255     struct sbd_port *sport = to_sport(uport);
0256     unsigned int clr = 0, set = 0, mode2;
0257 
0258     if (mctrl & TIOCM_DTR)
0259         set |= M_DUART_SET_OPR2;
0260     else
0261         clr |= M_DUART_CLR_OPR2;
0262     if (mctrl & TIOCM_RTS)
0263         set |= M_DUART_SET_OPR0;
0264     else
0265         clr |= M_DUART_CLR_OPR0;
0266     clr <<= (uport->line) % 2;
0267     set <<= (uport->line) % 2;
0268 
0269     mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
0270     mode2 &= ~M_DUART_CHAN_MODE;
0271     if (mctrl & TIOCM_LOOP)
0272         mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
0273     else
0274         mode2 |= V_DUART_CHAN_MODE_NORMAL;
0275 
0276     write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
0277     write_sbdshr(sport, R_DUART_SET_OPR, set);
0278     write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
0279 }
0280 
0281 static void sbd_stop_tx(struct uart_port *uport)
0282 {
0283     struct sbd_port *sport = to_sport(uport);
0284 
0285     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
0286     sport->tx_stopped = 1;
0287 };
0288 
0289 static void sbd_start_tx(struct uart_port *uport)
0290 {
0291     struct sbd_port *sport = to_sport(uport);
0292     unsigned int mask;
0293 
0294     /* Enable tx interrupts.  */
0295     mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
0296     mask |= M_DUART_IMR_TX;
0297     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
0298 
0299     /* Go!, go!, go!...  */
0300     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
0301     sport->tx_stopped = 0;
0302 };
0303 
0304 static void sbd_stop_rx(struct uart_port *uport)
0305 {
0306     struct sbd_port *sport = to_sport(uport);
0307 
0308     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
0309 };
0310 
0311 static void sbd_enable_ms(struct uart_port *uport)
0312 {
0313     struct sbd_port *sport = to_sport(uport);
0314 
0315     write_sbdchn(sport, R_DUART_AUXCTL_X,
0316              M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
0317 }
0318 
0319 static void sbd_break_ctl(struct uart_port *uport, int break_state)
0320 {
0321     struct sbd_port *sport = to_sport(uport);
0322 
0323     if (break_state == -1)
0324         write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
0325     else
0326         write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
0327 }
0328 
0329 
0330 static void sbd_receive_chars(struct sbd_port *sport)
0331 {
0332     struct uart_port *uport = &sport->port;
0333     struct uart_icount *icount;
0334     unsigned int status, ch, flag;
0335     int count;
0336 
0337     for (count = 16; count; count--) {
0338         status = read_sbdchn(sport, R_DUART_STATUS);
0339         if (!(status & M_DUART_RX_RDY))
0340             break;
0341 
0342         ch = read_sbdchn(sport, R_DUART_RX_HOLD);
0343 
0344         flag = TTY_NORMAL;
0345 
0346         icount = &uport->icount;
0347         icount->rx++;
0348 
0349         if (unlikely(status &
0350                  (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
0351                   M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
0352             if (status & M_DUART_RCVD_BRK) {
0353                 icount->brk++;
0354                 if (uart_handle_break(uport))
0355                     continue;
0356             } else if (status & M_DUART_FRM_ERR)
0357                 icount->frame++;
0358             else if (status & M_DUART_PARITY_ERR)
0359                 icount->parity++;
0360             if (status & M_DUART_OVRUN_ERR)
0361                 icount->overrun++;
0362 
0363             status &= uport->read_status_mask;
0364             if (status & M_DUART_RCVD_BRK)
0365                 flag = TTY_BREAK;
0366             else if (status & M_DUART_FRM_ERR)
0367                 flag = TTY_FRAME;
0368             else if (status & M_DUART_PARITY_ERR)
0369                 flag = TTY_PARITY;
0370         }
0371 
0372         if (uart_handle_sysrq_char(uport, ch))
0373             continue;
0374 
0375         uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
0376     }
0377 
0378     tty_flip_buffer_push(&uport->state->port);
0379 }
0380 
0381 static void sbd_transmit_chars(struct sbd_port *sport)
0382 {
0383     struct uart_port *uport = &sport->port;
0384     struct circ_buf *xmit = &sport->port.state->xmit;
0385     unsigned int mask;
0386     int stop_tx;
0387 
0388     /* XON/XOFF chars.  */
0389     if (sport->port.x_char) {
0390         write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
0391         sport->port.icount.tx++;
0392         sport->port.x_char = 0;
0393         return;
0394     }
0395 
0396     /* If nothing to do or stopped or hardware stopped.  */
0397     stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
0398 
0399     /* Send char.  */
0400     if (!stop_tx) {
0401         write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
0402         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0403         sport->port.icount.tx++;
0404 
0405         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0406             uart_write_wakeup(&sport->port);
0407     }
0408 
0409     /* Are we are done?  */
0410     if (stop_tx || uart_circ_empty(xmit)) {
0411         /* Disable tx interrupts.  */
0412         mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
0413         mask &= ~M_DUART_IMR_TX;
0414         write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
0415     }
0416 }
0417 
0418 static void sbd_status_handle(struct sbd_port *sport)
0419 {
0420     struct uart_port *uport = &sport->port;
0421     unsigned int delta;
0422 
0423     delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
0424     delta >>= (uport->line) % 2;
0425 
0426     if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
0427         uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
0428 
0429     if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
0430         uport->icount.dsr++;
0431 
0432     if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
0433              S_DUART_IN_PIN_CHNG))
0434         wake_up_interruptible(&uport->state->port.delta_msr_wait);
0435 }
0436 
0437 static irqreturn_t sbd_interrupt(int irq, void *dev_id)
0438 {
0439     struct sbd_port *sport = dev_id;
0440     struct uart_port *uport = &sport->port;
0441     irqreturn_t status = IRQ_NONE;
0442     unsigned int intstat;
0443     int count;
0444 
0445     for (count = 16; count; count--) {
0446         intstat = read_sbdshr(sport,
0447                       R_DUART_ISRREG((uport->line) % 2));
0448         intstat &= read_sbdshr(sport,
0449                        R_DUART_IMRREG((uport->line) % 2));
0450         intstat &= M_DUART_ISR_ALL;
0451         if (!intstat)
0452             break;
0453 
0454         if (intstat & M_DUART_ISR_RX)
0455             sbd_receive_chars(sport);
0456         if (intstat & M_DUART_ISR_IN)
0457             sbd_status_handle(sport);
0458         if (intstat & M_DUART_ISR_TX)
0459             sbd_transmit_chars(sport);
0460 
0461         status = IRQ_HANDLED;
0462     }
0463 
0464     return status;
0465 }
0466 
0467 
0468 static int sbd_startup(struct uart_port *uport)
0469 {
0470     struct sbd_port *sport = to_sport(uport);
0471     unsigned int mode1;
0472     int ret;
0473 
0474     ret = request_irq(sport->port.irq, sbd_interrupt,
0475               IRQF_SHARED, "sb1250-duart", sport);
0476     if (ret)
0477         return ret;
0478 
0479     /* Clear the receive FIFO.  */
0480     sbd_receive_drain(sport);
0481 
0482     /* Clear the interrupt registers.  */
0483     write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
0484     read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
0485 
0486     /* Set rx/tx interrupt to FIFO available.  */
0487     mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
0488     mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
0489     write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
0490 
0491     /* Disable tx, enable rx.  */
0492     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
0493     sport->tx_stopped = 1;
0494 
0495     /* Enable interrupts.  */
0496     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
0497              M_DUART_IMR_IN | M_DUART_IMR_RX);
0498 
0499     return 0;
0500 }
0501 
0502 static void sbd_shutdown(struct uart_port *uport)
0503 {
0504     struct sbd_port *sport = to_sport(uport);
0505 
0506     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
0507     sport->tx_stopped = 1;
0508     free_irq(sport->port.irq, sport);
0509 }
0510 
0511 
0512 static void sbd_init_port(struct sbd_port *sport)
0513 {
0514     struct uart_port *uport = &sport->port;
0515 
0516     if (sport->initialised)
0517         return;
0518 
0519     /* There is no DUART reset feature, so just set some sane defaults.  */
0520     write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
0521     write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
0522     write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
0523     write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
0524     write_sbdchn(sport, R_DUART_FULL_CTL,
0525              V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
0526     write_sbdchn(sport, R_DUART_OPCR_X, 0);
0527     write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
0528     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
0529 
0530     sport->initialised = 1;
0531 }
0532 
0533 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
0534                 struct ktermios *old_termios)
0535 {
0536     struct sbd_port *sport = to_sport(uport);
0537     unsigned int mode1 = 0, mode2 = 0, aux = 0;
0538     unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
0539     unsigned int oldmode1, oldmode2, oldaux;
0540     unsigned int baud, brg;
0541     unsigned int command;
0542 
0543     mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
0544                M_DUART_BITS_PER_CHAR);
0545     mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
0546     auxmask |= ~M_DUART_CTS_CHNG_ENA;
0547 
0548     /* Byte size.  */
0549     switch (termios->c_cflag & CSIZE) {
0550     case CS5:
0551     case CS6:
0552         /* Unsupported, leave unchanged.  */
0553         mode1mask |= M_DUART_PARITY_MODE;
0554         break;
0555     case CS7:
0556         mode1 |= V_DUART_BITS_PER_CHAR_7;
0557         break;
0558     case CS8:
0559     default:
0560         mode1 |= V_DUART_BITS_PER_CHAR_8;
0561         break;
0562     }
0563 
0564     /* Parity and stop bits.  */
0565     if (termios->c_cflag & CSTOPB)
0566         mode2 |= M_DUART_STOP_BIT_LEN_2;
0567     else
0568         mode2 |= M_DUART_STOP_BIT_LEN_1;
0569     if (termios->c_cflag & PARENB)
0570         mode1 |= V_DUART_PARITY_MODE_ADD;
0571     else
0572         mode1 |= V_DUART_PARITY_MODE_NONE;
0573     if (termios->c_cflag & PARODD)
0574         mode1 |= M_DUART_PARITY_TYPE_ODD;
0575     else
0576         mode1 |= M_DUART_PARITY_TYPE_EVEN;
0577 
0578     baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
0579     brg = V_DUART_BAUD_RATE(baud);
0580     /* The actual lower bound is 1221bps, so compensate.  */
0581     if (brg > M_DUART_CLK_COUNTER)
0582         brg = M_DUART_CLK_COUNTER;
0583 
0584     uart_update_timeout(uport, termios->c_cflag, baud);
0585 
0586     uport->read_status_mask = M_DUART_OVRUN_ERR;
0587     if (termios->c_iflag & INPCK)
0588         uport->read_status_mask |= M_DUART_FRM_ERR |
0589                        M_DUART_PARITY_ERR;
0590     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0591         uport->read_status_mask |= M_DUART_RCVD_BRK;
0592 
0593     uport->ignore_status_mask = 0;
0594     if (termios->c_iflag & IGNPAR)
0595         uport->ignore_status_mask |= M_DUART_FRM_ERR |
0596                          M_DUART_PARITY_ERR;
0597     if (termios->c_iflag & IGNBRK) {
0598         uport->ignore_status_mask |= M_DUART_RCVD_BRK;
0599         if (termios->c_iflag & IGNPAR)
0600             uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
0601     }
0602 
0603     if (termios->c_cflag & CREAD)
0604         command = M_DUART_RX_EN;
0605     else
0606         command = M_DUART_RX_DIS;
0607 
0608     if (termios->c_cflag & CRTSCTS)
0609         aux |= M_DUART_CTS_CHNG_ENA;
0610     else
0611         aux &= ~M_DUART_CTS_CHNG_ENA;
0612 
0613     spin_lock(&uport->lock);
0614 
0615     if (sport->tx_stopped)
0616         command |= M_DUART_TX_DIS;
0617     else
0618         command |= M_DUART_TX_EN;
0619 
0620     oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
0621     oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
0622     oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
0623 
0624     if (!sport->tx_stopped)
0625         sbd_line_drain(sport);
0626     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
0627 
0628     write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
0629     write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
0630     write_sbdchn(sport, R_DUART_CLK_SEL, brg);
0631     write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
0632 
0633     write_sbdchn(sport, R_DUART_CMD, command);
0634 
0635     spin_unlock(&uport->lock);
0636 }
0637 
0638 
0639 static const char *sbd_type(struct uart_port *uport)
0640 {
0641     return "SB1250 DUART";
0642 }
0643 
0644 static void sbd_release_port(struct uart_port *uport)
0645 {
0646     struct sbd_port *sport = to_sport(uport);
0647     struct sbd_duart *duart = sport->duart;
0648 
0649     iounmap(sport->memctrl);
0650     sport->memctrl = NULL;
0651     iounmap(uport->membase);
0652     uport->membase = NULL;
0653 
0654     if(refcount_dec_and_test(&duart->map_guard))
0655         release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
0656     release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
0657 }
0658 
0659 static int sbd_map_port(struct uart_port *uport)
0660 {
0661     const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
0662     struct sbd_port *sport = to_sport(uport);
0663     struct sbd_duart *duart = sport->duart;
0664 
0665     if (!uport->membase)
0666         uport->membase = ioremap(uport->mapbase,
0667                          DUART_CHANREG_SPACING);
0668     if (!uport->membase) {
0669         printk(err);
0670         return -ENOMEM;
0671     }
0672 
0673     if (!sport->memctrl)
0674         sport->memctrl = ioremap(duart->mapctrl,
0675                          DUART_CHANREG_SPACING);
0676     if (!sport->memctrl) {
0677         printk(err);
0678         iounmap(uport->membase);
0679         uport->membase = NULL;
0680         return -ENOMEM;
0681     }
0682 
0683     return 0;
0684 }
0685 
0686 static int sbd_request_port(struct uart_port *uport)
0687 {
0688     const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
0689     struct sbd_duart *duart = to_sport(uport)->duart;
0690     int ret = 0;
0691 
0692     if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
0693                 "sb1250-duart")) {
0694         printk(err);
0695         return -EBUSY;
0696     }
0697     refcount_inc(&duart->map_guard);
0698     if (refcount_read(&duart->map_guard) == 1) {
0699         if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
0700                     "sb1250-duart")) {
0701             refcount_dec(&duart->map_guard);
0702             printk(err);
0703             ret = -EBUSY;
0704         }
0705     }
0706     if (!ret) {
0707         ret = sbd_map_port(uport);
0708         if (ret) {
0709             if (refcount_dec_and_test(&duart->map_guard))
0710                 release_mem_region(duart->mapctrl,
0711                            DUART_CHANREG_SPACING);
0712         }
0713     }
0714     if (ret) {
0715         release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
0716         return ret;
0717     }
0718     return 0;
0719 }
0720 
0721 static void sbd_config_port(struct uart_port *uport, int flags)
0722 {
0723     struct sbd_port *sport = to_sport(uport);
0724 
0725     if (flags & UART_CONFIG_TYPE) {
0726         if (sbd_request_port(uport))
0727             return;
0728 
0729         uport->type = PORT_SB1250_DUART;
0730 
0731         sbd_init_port(sport);
0732     }
0733 }
0734 
0735 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
0736 {
0737     int ret = 0;
0738 
0739     if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
0740         ret = -EINVAL;
0741     if (ser->irq != uport->irq)
0742         ret = -EINVAL;
0743     if (ser->baud_base != uport->uartclk / 16)
0744         ret = -EINVAL;
0745     return ret;
0746 }
0747 
0748 
0749 static const struct uart_ops sbd_ops = {
0750     .tx_empty   = sbd_tx_empty,
0751     .set_mctrl  = sbd_set_mctrl,
0752     .get_mctrl  = sbd_get_mctrl,
0753     .stop_tx    = sbd_stop_tx,
0754     .start_tx   = sbd_start_tx,
0755     .stop_rx    = sbd_stop_rx,
0756     .enable_ms  = sbd_enable_ms,
0757     .break_ctl  = sbd_break_ctl,
0758     .startup    = sbd_startup,
0759     .shutdown   = sbd_shutdown,
0760     .set_termios    = sbd_set_termios,
0761     .type       = sbd_type,
0762     .release_port   = sbd_release_port,
0763     .request_port   = sbd_request_port,
0764     .config_port    = sbd_config_port,
0765     .verify_port    = sbd_verify_port,
0766 };
0767 
0768 /* Initialize SB1250 DUART port structures.  */
0769 static void __init sbd_probe_duarts(void)
0770 {
0771     static int probed;
0772     int chip, side;
0773     int max_lines, line;
0774 
0775     if (probed)
0776         return;
0777 
0778     /* Set the number of available units based on the SOC type.  */
0779     switch (soc_type) {
0780     case K_SYS_SOC_TYPE_BCM1x55:
0781     case K_SYS_SOC_TYPE_BCM1x80:
0782         max_lines = 4;
0783         break;
0784     default:
0785         /* Assume at least two serial ports at the normal address.  */
0786         max_lines = 2;
0787         break;
0788     }
0789 
0790     probed = 1;
0791 
0792     for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
0793          chip++) {
0794         sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
0795 
0796         for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
0797              side++, line++) {
0798             struct sbd_port *sport = &sbd_duarts[chip].sport[side];
0799             struct uart_port *uport = &sport->port;
0800 
0801             sport->duart    = &sbd_duarts[chip];
0802 
0803             uport->irq  = SBD_INT(line);
0804             uport->uartclk  = 100000000 / 20 * 16;
0805             uport->fifosize = 16;
0806             uport->iotype   = UPIO_MEM;
0807             uport->flags    = UPF_BOOT_AUTOCONF;
0808             uport->ops  = &sbd_ops;
0809             uport->line = line;
0810             uport->mapbase  = SBD_CHANREGS(line);
0811             uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SB1250_DUART_CONSOLE);
0812         }
0813     }
0814 }
0815 
0816 
0817 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
0818 /*
0819  * Serial console stuff.  Very basic, polling driver for doing serial
0820  * console output.  The console_lock is held by the caller, so we
0821  * shouldn't be interrupted for more console activity.
0822  */
0823 static void sbd_console_putchar(struct uart_port *uport, unsigned char ch)
0824 {
0825     struct sbd_port *sport = to_sport(uport);
0826 
0827     sbd_transmit_drain(sport);
0828     write_sbdchn(sport, R_DUART_TX_HOLD, ch);
0829 }
0830 
0831 static void sbd_console_write(struct console *co, const char *s,
0832                   unsigned int count)
0833 {
0834     int chip = co->index / DUART_MAX_SIDE;
0835     int side = co->index % DUART_MAX_SIDE;
0836     struct sbd_port *sport = &sbd_duarts[chip].sport[side];
0837     struct uart_port *uport = &sport->port;
0838     unsigned long flags;
0839     unsigned int mask;
0840 
0841     /* Disable transmit interrupts and enable the transmitter. */
0842     spin_lock_irqsave(&uport->lock, flags);
0843     mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
0844     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
0845              mask & ~M_DUART_IMR_TX);
0846     write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
0847     spin_unlock_irqrestore(&uport->lock, flags);
0848 
0849     uart_console_write(&sport->port, s, count, sbd_console_putchar);
0850 
0851     /* Restore transmit interrupts and the transmitter enable. */
0852     spin_lock_irqsave(&uport->lock, flags);
0853     sbd_line_drain(sport);
0854     if (sport->tx_stopped)
0855         write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
0856     write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
0857     spin_unlock_irqrestore(&uport->lock, flags);
0858 }
0859 
0860 static int __init sbd_console_setup(struct console *co, char *options)
0861 {
0862     int chip = co->index / DUART_MAX_SIDE;
0863     int side = co->index % DUART_MAX_SIDE;
0864     struct sbd_port *sport = &sbd_duarts[chip].sport[side];
0865     struct uart_port *uport = &sport->port;
0866     int baud = 115200;
0867     int bits = 8;
0868     int parity = 'n';
0869     int flow = 'n';
0870     int ret;
0871 
0872     if (!sport->duart)
0873         return -ENXIO;
0874 
0875     ret = sbd_map_port(uport);
0876     if (ret)
0877         return ret;
0878 
0879     sbd_init_port(sport);
0880 
0881     if (options)
0882         uart_parse_options(options, &baud, &parity, &bits, &flow);
0883     return uart_set_options(uport, co, baud, parity, bits, flow);
0884 }
0885 
0886 static struct uart_driver sbd_reg;
0887 static struct console sbd_console = {
0888     .name   = "duart",
0889     .write  = sbd_console_write,
0890     .device = uart_console_device,
0891     .setup  = sbd_console_setup,
0892     .flags  = CON_PRINTBUFFER,
0893     .index  = -1,
0894     .data   = &sbd_reg
0895 };
0896 
0897 static int __init sbd_serial_console_init(void)
0898 {
0899     sbd_probe_duarts();
0900     register_console(&sbd_console);
0901 
0902     return 0;
0903 }
0904 
0905 console_initcall(sbd_serial_console_init);
0906 
0907 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console
0908 #else
0909 #define SERIAL_SB1250_DUART_CONSOLE NULL
0910 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
0911 
0912 
0913 static struct uart_driver sbd_reg = {
0914     .owner      = THIS_MODULE,
0915     .driver_name    = "sb1250_duart",
0916     .dev_name   = "duart",
0917     .major      = TTY_MAJOR,
0918     .minor      = SB1250_DUART_MINOR_BASE,
0919     .nr     = DUART_MAX_CHIP * DUART_MAX_SIDE,
0920     .cons       = SERIAL_SB1250_DUART_CONSOLE,
0921 };
0922 
0923 /* Set up the driver and register it.  */
0924 static int __init sbd_init(void)
0925 {
0926     int i, ret;
0927 
0928     sbd_probe_duarts();
0929 
0930     ret = uart_register_driver(&sbd_reg);
0931     if (ret)
0932         return ret;
0933 
0934     for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
0935         struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
0936         struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
0937         struct uart_port *uport = &sport->port;
0938 
0939         if (sport->duart)
0940             uart_add_one_port(&sbd_reg, uport);
0941     }
0942 
0943     return 0;
0944 }
0945 
0946 /* Unload the driver.  Unregister stuff, get ready to go away.  */
0947 static void __exit sbd_exit(void)
0948 {
0949     int i;
0950 
0951     for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
0952         struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
0953         struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
0954         struct uart_port *uport = &sport->port;
0955 
0956         if (sport->duart)
0957             uart_remove_one_port(&sbd_reg, uport);
0958     }
0959 
0960     uart_unregister_driver(&sbd_reg);
0961 }
0962 
0963 module_init(sbd_init);
0964 module_exit(sbd_exit);
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