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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Driver for SA11x0 serial ports
0004  *
0005  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
0006  *
0007  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/ioport.h>
0012 #include <linux/init.h>
0013 #include <linux/console.h>
0014 #include <linux/sysrq.h>
0015 #include <linux/platform_data/sa11x0-serial.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/tty.h>
0018 #include <linux/tty_flip.h>
0019 #include <linux/serial_core.h>
0020 #include <linux/serial.h>
0021 #include <linux/io.h>
0022 
0023 #include <asm/irq.h>
0024 #include <mach/hardware.h>
0025 #include <mach/irqs.h>
0026 
0027 #include "serial_mctrl_gpio.h"
0028 
0029 /* We've been assigned a range on the "Low-density serial ports" major */
0030 #define SERIAL_SA1100_MAJOR 204
0031 #define MINOR_START     5
0032 
0033 #define NR_PORTS        3
0034 
0035 #define SA1100_ISR_PASS_LIMIT   256
0036 
0037 /*
0038  * Convert from ignore_status_mask or read_status_mask to UTSR[01]
0039  */
0040 #define SM_TO_UTSR0(x)  ((x) & 0xff)
0041 #define SM_TO_UTSR1(x)  ((x) >> 8)
0042 #define UTSR0_TO_SM(x)  ((x))
0043 #define UTSR1_TO_SM(x)  ((x) << 8)
0044 
0045 #define UART_GET_UTCR0(sport)   __raw_readl((sport)->port.membase + UTCR0)
0046 #define UART_GET_UTCR1(sport)   __raw_readl((sport)->port.membase + UTCR1)
0047 #define UART_GET_UTCR2(sport)   __raw_readl((sport)->port.membase + UTCR2)
0048 #define UART_GET_UTCR3(sport)   __raw_readl((sport)->port.membase + UTCR3)
0049 #define UART_GET_UTSR0(sport)   __raw_readl((sport)->port.membase + UTSR0)
0050 #define UART_GET_UTSR1(sport)   __raw_readl((sport)->port.membase + UTSR1)
0051 #define UART_GET_CHAR(sport)    __raw_readl((sport)->port.membase + UTDR)
0052 
0053 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
0054 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
0055 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
0056 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
0057 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
0058 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
0059 #define UART_PUT_CHAR(sport,v)  __raw_writel((v),(sport)->port.membase + UTDR)
0060 
0061 /*
0062  * This is the size of our serial port register set.
0063  */
0064 #define UART_PORT_SIZE  0x24
0065 
0066 /*
0067  * This determines how often we check the modem status signals
0068  * for any change.  They generally aren't connected to an IRQ
0069  * so we have to poll them.  We also check immediately before
0070  * filling the TX fifo incase CTS has been dropped.
0071  */
0072 #define MCTRL_TIMEOUT   (250*HZ/1000)
0073 
0074 struct sa1100_port {
0075     struct uart_port    port;
0076     struct timer_list   timer;
0077     unsigned int        old_status;
0078     struct mctrl_gpios  *gpios;
0079 };
0080 
0081 /*
0082  * Handle any change of modem status signal since we were last called.
0083  */
0084 static void sa1100_mctrl_check(struct sa1100_port *sport)
0085 {
0086     unsigned int status, changed;
0087 
0088     status = sport->port.ops->get_mctrl(&sport->port);
0089     changed = status ^ sport->old_status;
0090 
0091     if (changed == 0)
0092         return;
0093 
0094     sport->old_status = status;
0095 
0096     if (changed & TIOCM_RI)
0097         sport->port.icount.rng++;
0098     if (changed & TIOCM_DSR)
0099         sport->port.icount.dsr++;
0100     if (changed & TIOCM_CAR)
0101         uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
0102     if (changed & TIOCM_CTS)
0103         uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
0104 
0105     wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
0106 }
0107 
0108 /*
0109  * This is our per-port timeout handler, for checking the
0110  * modem status signals.
0111  */
0112 static void sa1100_timeout(struct timer_list *t)
0113 {
0114     struct sa1100_port *sport = from_timer(sport, t, timer);
0115     unsigned long flags;
0116 
0117     if (sport->port.state) {
0118         spin_lock_irqsave(&sport->port.lock, flags);
0119         sa1100_mctrl_check(sport);
0120         spin_unlock_irqrestore(&sport->port.lock, flags);
0121 
0122         mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
0123     }
0124 }
0125 
0126 /*
0127  * interrupts disabled on entry
0128  */
0129 static void sa1100_stop_tx(struct uart_port *port)
0130 {
0131     struct sa1100_port *sport =
0132         container_of(port, struct sa1100_port, port);
0133     u32 utcr3;
0134 
0135     utcr3 = UART_GET_UTCR3(sport);
0136     UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
0137     sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
0138 }
0139 
0140 /*
0141  * port locked and interrupts disabled
0142  */
0143 static void sa1100_start_tx(struct uart_port *port)
0144 {
0145     struct sa1100_port *sport =
0146         container_of(port, struct sa1100_port, port);
0147     u32 utcr3;
0148 
0149     utcr3 = UART_GET_UTCR3(sport);
0150     sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
0151     UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
0152 }
0153 
0154 /*
0155  * Interrupts enabled
0156  */
0157 static void sa1100_stop_rx(struct uart_port *port)
0158 {
0159     struct sa1100_port *sport =
0160         container_of(port, struct sa1100_port, port);
0161     u32 utcr3;
0162 
0163     utcr3 = UART_GET_UTCR3(sport);
0164     UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
0165 }
0166 
0167 /*
0168  * Set the modem control timer to fire immediately.
0169  */
0170 static void sa1100_enable_ms(struct uart_port *port)
0171 {
0172     struct sa1100_port *sport =
0173         container_of(port, struct sa1100_port, port);
0174 
0175     mod_timer(&sport->timer, jiffies);
0176 
0177     mctrl_gpio_enable_ms(sport->gpios);
0178 }
0179 
0180 static void
0181 sa1100_rx_chars(struct sa1100_port *sport)
0182 {
0183     unsigned int status, ch, flg;
0184 
0185     status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
0186          UTSR0_TO_SM(UART_GET_UTSR0(sport));
0187     while (status & UTSR1_TO_SM(UTSR1_RNE)) {
0188         ch = UART_GET_CHAR(sport);
0189 
0190         sport->port.icount.rx++;
0191 
0192         flg = TTY_NORMAL;
0193 
0194         /*
0195          * note that the error handling code is
0196          * out of the main execution path
0197          */
0198         if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
0199             if (status & UTSR1_TO_SM(UTSR1_PRE))
0200                 sport->port.icount.parity++;
0201             else if (status & UTSR1_TO_SM(UTSR1_FRE))
0202                 sport->port.icount.frame++;
0203             if (status & UTSR1_TO_SM(UTSR1_ROR))
0204                 sport->port.icount.overrun++;
0205 
0206             status &= sport->port.read_status_mask;
0207 
0208             if (status & UTSR1_TO_SM(UTSR1_PRE))
0209                 flg = TTY_PARITY;
0210             else if (status & UTSR1_TO_SM(UTSR1_FRE))
0211                 flg = TTY_FRAME;
0212 
0213             sport->port.sysrq = 0;
0214         }
0215 
0216         if (uart_handle_sysrq_char(&sport->port, ch))
0217             goto ignore_char;
0218 
0219         uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
0220 
0221     ignore_char:
0222         status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
0223              UTSR0_TO_SM(UART_GET_UTSR0(sport));
0224     }
0225 
0226     tty_flip_buffer_push(&sport->port.state->port);
0227 }
0228 
0229 static void sa1100_tx_chars(struct sa1100_port *sport)
0230 {
0231     struct circ_buf *xmit = &sport->port.state->xmit;
0232 
0233     if (sport->port.x_char) {
0234         UART_PUT_CHAR(sport, sport->port.x_char);
0235         sport->port.icount.tx++;
0236         sport->port.x_char = 0;
0237         return;
0238     }
0239 
0240     /*
0241      * Check the modem control lines before
0242      * transmitting anything.
0243      */
0244     sa1100_mctrl_check(sport);
0245 
0246     if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
0247         sa1100_stop_tx(&sport->port);
0248         return;
0249     }
0250 
0251     /*
0252      * Tried using FIFO (not checking TNF) for fifo fill:
0253      * still had the '4 bytes repeated' problem.
0254      */
0255     while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
0256         UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
0257         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0258         sport->port.icount.tx++;
0259         if (uart_circ_empty(xmit))
0260             break;
0261     }
0262 
0263     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0264         uart_write_wakeup(&sport->port);
0265 
0266     if (uart_circ_empty(xmit))
0267         sa1100_stop_tx(&sport->port);
0268 }
0269 
0270 static irqreturn_t sa1100_int(int irq, void *dev_id)
0271 {
0272     struct sa1100_port *sport = dev_id;
0273     unsigned int status, pass_counter = 0;
0274 
0275     spin_lock(&sport->port.lock);
0276     status = UART_GET_UTSR0(sport);
0277     status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
0278     do {
0279         if (status & (UTSR0_RFS | UTSR0_RID)) {
0280             /* Clear the receiver idle bit, if set */
0281             if (status & UTSR0_RID)
0282                 UART_PUT_UTSR0(sport, UTSR0_RID);
0283             sa1100_rx_chars(sport);
0284         }
0285 
0286         /* Clear the relevant break bits */
0287         if (status & (UTSR0_RBB | UTSR0_REB))
0288             UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
0289 
0290         if (status & UTSR0_RBB)
0291             sport->port.icount.brk++;
0292 
0293         if (status & UTSR0_REB)
0294             uart_handle_break(&sport->port);
0295 
0296         if (status & UTSR0_TFS)
0297             sa1100_tx_chars(sport);
0298         if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
0299             break;
0300         status = UART_GET_UTSR0(sport);
0301         status &= SM_TO_UTSR0(sport->port.read_status_mask) |
0302               ~UTSR0_TFS;
0303     } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
0304     spin_unlock(&sport->port.lock);
0305 
0306     return IRQ_HANDLED;
0307 }
0308 
0309 /*
0310  * Return TIOCSER_TEMT when transmitter is not busy.
0311  */
0312 static unsigned int sa1100_tx_empty(struct uart_port *port)
0313 {
0314     struct sa1100_port *sport =
0315         container_of(port, struct sa1100_port, port);
0316 
0317     return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
0318 }
0319 
0320 static unsigned int sa1100_get_mctrl(struct uart_port *port)
0321 {
0322     struct sa1100_port *sport =
0323         container_of(port, struct sa1100_port, port);
0324     int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
0325 
0326     mctrl_gpio_get(sport->gpios, &ret);
0327 
0328     return ret;
0329 }
0330 
0331 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
0332 {
0333     struct sa1100_port *sport =
0334         container_of(port, struct sa1100_port, port);
0335 
0336     mctrl_gpio_set(sport->gpios, mctrl);
0337 }
0338 
0339 /*
0340  * Interrupts always disabled.
0341  */
0342 static void sa1100_break_ctl(struct uart_port *port, int break_state)
0343 {
0344     struct sa1100_port *sport =
0345         container_of(port, struct sa1100_port, port);
0346     unsigned long flags;
0347     unsigned int utcr3;
0348 
0349     spin_lock_irqsave(&sport->port.lock, flags);
0350     utcr3 = UART_GET_UTCR3(sport);
0351     if (break_state == -1)
0352         utcr3 |= UTCR3_BRK;
0353     else
0354         utcr3 &= ~UTCR3_BRK;
0355     UART_PUT_UTCR3(sport, utcr3);
0356     spin_unlock_irqrestore(&sport->port.lock, flags);
0357 }
0358 
0359 static int sa1100_startup(struct uart_port *port)
0360 {
0361     struct sa1100_port *sport =
0362         container_of(port, struct sa1100_port, port);
0363     int retval;
0364 
0365     /*
0366      * Allocate the IRQ
0367      */
0368     retval = request_irq(sport->port.irq, sa1100_int, 0,
0369                  "sa11x0-uart", sport);
0370     if (retval)
0371         return retval;
0372 
0373     /*
0374      * Finally, clear and enable interrupts
0375      */
0376     UART_PUT_UTSR0(sport, -1);
0377     UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
0378 
0379     /*
0380      * Enable modem status interrupts
0381      */
0382     spin_lock_irq(&sport->port.lock);
0383     sa1100_enable_ms(&sport->port);
0384     spin_unlock_irq(&sport->port.lock);
0385 
0386     return 0;
0387 }
0388 
0389 static void sa1100_shutdown(struct uart_port *port)
0390 {
0391     struct sa1100_port *sport =
0392         container_of(port, struct sa1100_port, port);
0393 
0394     /*
0395      * Stop our timer.
0396      */
0397     del_timer_sync(&sport->timer);
0398 
0399     /*
0400      * Free the interrupt
0401      */
0402     free_irq(sport->port.irq, sport);
0403 
0404     /*
0405      * Disable all interrupts, port and break condition.
0406      */
0407     UART_PUT_UTCR3(sport, 0);
0408 }
0409 
0410 static void
0411 sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
0412            struct ktermios *old)
0413 {
0414     struct sa1100_port *sport =
0415         container_of(port, struct sa1100_port, port);
0416     unsigned long flags;
0417     unsigned int utcr0, old_utcr3, baud, quot;
0418     unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
0419 
0420     /*
0421      * We only support CS7 and CS8.
0422      */
0423     while ((termios->c_cflag & CSIZE) != CS7 &&
0424            (termios->c_cflag & CSIZE) != CS8) {
0425         termios->c_cflag &= ~CSIZE;
0426         termios->c_cflag |= old_csize;
0427         old_csize = CS8;
0428     }
0429 
0430     if ((termios->c_cflag & CSIZE) == CS8)
0431         utcr0 = UTCR0_DSS;
0432     else
0433         utcr0 = 0;
0434 
0435     if (termios->c_cflag & CSTOPB)
0436         utcr0 |= UTCR0_SBS;
0437     if (termios->c_cflag & PARENB) {
0438         utcr0 |= UTCR0_PE;
0439         if (!(termios->c_cflag & PARODD))
0440             utcr0 |= UTCR0_OES;
0441     }
0442 
0443     /*
0444      * Ask the core to calculate the divisor for us.
0445      */
0446     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
0447     quot = uart_get_divisor(port, baud);
0448 
0449     del_timer_sync(&sport->timer);
0450 
0451     spin_lock_irqsave(&sport->port.lock, flags);
0452 
0453     sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
0454     sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
0455     if (termios->c_iflag & INPCK)
0456         sport->port.read_status_mask |=
0457                 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
0458     if (termios->c_iflag & (BRKINT | PARMRK))
0459         sport->port.read_status_mask |=
0460                 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
0461 
0462     /*
0463      * Characters to ignore
0464      */
0465     sport->port.ignore_status_mask = 0;
0466     if (termios->c_iflag & IGNPAR)
0467         sport->port.ignore_status_mask |=
0468                 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
0469     if (termios->c_iflag & IGNBRK) {
0470         sport->port.ignore_status_mask |=
0471                 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
0472         /*
0473          * If we're ignoring parity and break indicators,
0474          * ignore overruns too (for real raw support).
0475          */
0476         if (termios->c_iflag & IGNPAR)
0477             sport->port.ignore_status_mask |=
0478                 UTSR1_TO_SM(UTSR1_ROR);
0479     }
0480 
0481     /*
0482      * Update the per-port timeout.
0483      */
0484     uart_update_timeout(port, termios->c_cflag, baud);
0485 
0486     /*
0487      * disable interrupts and drain transmitter
0488      */
0489     old_utcr3 = UART_GET_UTCR3(sport);
0490     UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
0491 
0492     while (UART_GET_UTSR1(sport) & UTSR1_TBY)
0493         barrier();
0494 
0495     /* then, disable everything */
0496     UART_PUT_UTCR3(sport, 0);
0497 
0498     /* set the parity, stop bits and data size */
0499     UART_PUT_UTCR0(sport, utcr0);
0500 
0501     /* set the baud rate */
0502     quot -= 1;
0503     UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
0504     UART_PUT_UTCR2(sport, (quot & 0xff));
0505 
0506     UART_PUT_UTSR0(sport, -1);
0507 
0508     UART_PUT_UTCR3(sport, old_utcr3);
0509 
0510     if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
0511         sa1100_enable_ms(&sport->port);
0512 
0513     spin_unlock_irqrestore(&sport->port.lock, flags);
0514 }
0515 
0516 static const char *sa1100_type(struct uart_port *port)
0517 {
0518     struct sa1100_port *sport =
0519         container_of(port, struct sa1100_port, port);
0520 
0521     return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
0522 }
0523 
0524 /*
0525  * Release the memory region(s) being used by 'port'.
0526  */
0527 static void sa1100_release_port(struct uart_port *port)
0528 {
0529     struct sa1100_port *sport =
0530         container_of(port, struct sa1100_port, port);
0531 
0532     release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
0533 }
0534 
0535 /*
0536  * Request the memory region(s) being used by 'port'.
0537  */
0538 static int sa1100_request_port(struct uart_port *port)
0539 {
0540     struct sa1100_port *sport =
0541         container_of(port, struct sa1100_port, port);
0542 
0543     return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
0544             "sa11x0-uart") != NULL ? 0 : -EBUSY;
0545 }
0546 
0547 /*
0548  * Configure/autoconfigure the port.
0549  */
0550 static void sa1100_config_port(struct uart_port *port, int flags)
0551 {
0552     struct sa1100_port *sport =
0553         container_of(port, struct sa1100_port, port);
0554 
0555     if (flags & UART_CONFIG_TYPE &&
0556         sa1100_request_port(&sport->port) == 0)
0557         sport->port.type = PORT_SA1100;
0558 }
0559 
0560 /*
0561  * Verify the new serial_struct (for TIOCSSERIAL).
0562  * The only change we allow are to the flags and type, and
0563  * even then only between PORT_SA1100 and PORT_UNKNOWN
0564  */
0565 static int
0566 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
0567 {
0568     struct sa1100_port *sport =
0569         container_of(port, struct sa1100_port, port);
0570     int ret = 0;
0571 
0572     if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
0573         ret = -EINVAL;
0574     if (sport->port.irq != ser->irq)
0575         ret = -EINVAL;
0576     if (ser->io_type != SERIAL_IO_MEM)
0577         ret = -EINVAL;
0578     if (sport->port.uartclk / 16 != ser->baud_base)
0579         ret = -EINVAL;
0580     if ((void *)sport->port.mapbase != ser->iomem_base)
0581         ret = -EINVAL;
0582     if (sport->port.iobase != ser->port)
0583         ret = -EINVAL;
0584     if (ser->hub6 != 0)
0585         ret = -EINVAL;
0586     return ret;
0587 }
0588 
0589 static struct uart_ops sa1100_pops = {
0590     .tx_empty   = sa1100_tx_empty,
0591     .set_mctrl  = sa1100_set_mctrl,
0592     .get_mctrl  = sa1100_get_mctrl,
0593     .stop_tx    = sa1100_stop_tx,
0594     .start_tx   = sa1100_start_tx,
0595     .stop_rx    = sa1100_stop_rx,
0596     .enable_ms  = sa1100_enable_ms,
0597     .break_ctl  = sa1100_break_ctl,
0598     .startup    = sa1100_startup,
0599     .shutdown   = sa1100_shutdown,
0600     .set_termios    = sa1100_set_termios,
0601     .type       = sa1100_type,
0602     .release_port   = sa1100_release_port,
0603     .request_port   = sa1100_request_port,
0604     .config_port    = sa1100_config_port,
0605     .verify_port    = sa1100_verify_port,
0606 };
0607 
0608 static struct sa1100_port sa1100_ports[NR_PORTS];
0609 
0610 /*
0611  * Setup the SA1100 serial ports.  Note that we don't include the IrDA
0612  * port here since we have our own SIR/FIR driver (see drivers/net/irda)
0613  *
0614  * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
0615  * Which serial port this ends up being depends on the machine you're
0616  * running this kernel on.  I'm not convinced that this is a good idea,
0617  * but that's the way it traditionally works.
0618  *
0619  * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
0620  * used here.
0621  */
0622 static void __init sa1100_init_ports(void)
0623 {
0624     static int first = 1;
0625     int i;
0626 
0627     if (!first)
0628         return;
0629     first = 0;
0630 
0631     for (i = 0; i < NR_PORTS; i++) {
0632         sa1100_ports[i].port.uartclk   = 3686400;
0633         sa1100_ports[i].port.ops       = &sa1100_pops;
0634         sa1100_ports[i].port.fifosize  = 8;
0635         sa1100_ports[i].port.line      = i;
0636         sa1100_ports[i].port.iotype    = UPIO_MEM;
0637         timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
0638     }
0639 
0640     /*
0641      * make transmit lines outputs, so that when the port
0642      * is closed, the output is in the MARK state.
0643      */
0644     PPDR |= PPC_TXD1 | PPC_TXD3;
0645     PPSR |= PPC_TXD1 | PPC_TXD3;
0646 }
0647 
0648 void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
0649 {
0650     if (fns->get_mctrl)
0651         sa1100_pops.get_mctrl = fns->get_mctrl;
0652     if (fns->set_mctrl)
0653         sa1100_pops.set_mctrl = fns->set_mctrl;
0654 
0655     sa1100_pops.pm       = fns->pm;
0656     /*
0657      * FIXME: fns->set_wake is unused - this should be called from
0658      * the suspend() callback if device_may_wakeup(dev)) is set.
0659      */
0660 }
0661 
0662 void __init sa1100_register_uart(int idx, int port)
0663 {
0664     if (idx >= NR_PORTS) {
0665         printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
0666         return;
0667     }
0668 
0669     switch (port) {
0670     case 1:
0671         sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
0672         sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
0673         sa1100_ports[idx].port.irq     = IRQ_Ser1UART;
0674         sa1100_ports[idx].port.flags   = UPF_BOOT_AUTOCONF;
0675         break;
0676 
0677     case 2:
0678         sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
0679         sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
0680         sa1100_ports[idx].port.irq     = IRQ_Ser2ICP;
0681         sa1100_ports[idx].port.flags   = UPF_BOOT_AUTOCONF;
0682         break;
0683 
0684     case 3:
0685         sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
0686         sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
0687         sa1100_ports[idx].port.irq     = IRQ_Ser3UART;
0688         sa1100_ports[idx].port.flags   = UPF_BOOT_AUTOCONF;
0689         break;
0690 
0691     default:
0692         printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
0693     }
0694 }
0695 
0696 
0697 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
0698 static void sa1100_console_putchar(struct uart_port *port, unsigned char ch)
0699 {
0700     struct sa1100_port *sport =
0701         container_of(port, struct sa1100_port, port);
0702 
0703     while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
0704         barrier();
0705     UART_PUT_CHAR(sport, ch);
0706 }
0707 
0708 /*
0709  * Interrupts are disabled on entering
0710  */
0711 static void
0712 sa1100_console_write(struct console *co, const char *s, unsigned int count)
0713 {
0714     struct sa1100_port *sport = &sa1100_ports[co->index];
0715     unsigned int old_utcr3, status;
0716 
0717     /*
0718      *  First, save UTCR3 and then disable interrupts
0719      */
0720     old_utcr3 = UART_GET_UTCR3(sport);
0721     UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
0722                 UTCR3_TXE);
0723 
0724     uart_console_write(&sport->port, s, count, sa1100_console_putchar);
0725 
0726     /*
0727      *  Finally, wait for transmitter to become empty
0728      *  and restore UTCR3
0729      */
0730     do {
0731         status = UART_GET_UTSR1(sport);
0732     } while (status & UTSR1_TBY);
0733     UART_PUT_UTCR3(sport, old_utcr3);
0734 }
0735 
0736 /*
0737  * If the port was already initialised (eg, by a boot loader),
0738  * try to determine the current setup.
0739  */
0740 static void __init
0741 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
0742                int *parity, int *bits)
0743 {
0744     unsigned int utcr3;
0745 
0746     utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
0747     if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
0748         /* ok, the port was enabled */
0749         unsigned int utcr0, quot;
0750 
0751         utcr0 = UART_GET_UTCR0(sport);
0752 
0753         *parity = 'n';
0754         if (utcr0 & UTCR0_PE) {
0755             if (utcr0 & UTCR0_OES)
0756                 *parity = 'e';
0757             else
0758                 *parity = 'o';
0759         }
0760 
0761         if (utcr0 & UTCR0_DSS)
0762             *bits = 8;
0763         else
0764             *bits = 7;
0765 
0766         quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
0767         quot &= 0xfff;
0768         *baud = sport->port.uartclk / (16 * (quot + 1));
0769     }
0770 }
0771 
0772 static int __init
0773 sa1100_console_setup(struct console *co, char *options)
0774 {
0775     struct sa1100_port *sport;
0776     int baud = 9600;
0777     int bits = 8;
0778     int parity = 'n';
0779     int flow = 'n';
0780 
0781     /*
0782      * Check whether an invalid uart number has been specified, and
0783      * if so, search for the first available port that does have
0784      * console support.
0785      */
0786     if (co->index == -1 || co->index >= NR_PORTS)
0787         co->index = 0;
0788     sport = &sa1100_ports[co->index];
0789 
0790     if (options)
0791         uart_parse_options(options, &baud, &parity, &bits, &flow);
0792     else
0793         sa1100_console_get_options(sport, &baud, &parity, &bits);
0794 
0795     return uart_set_options(&sport->port, co, baud, parity, bits, flow);
0796 }
0797 
0798 static struct uart_driver sa1100_reg;
0799 static struct console sa1100_console = {
0800     .name       = "ttySA",
0801     .write      = sa1100_console_write,
0802     .device     = uart_console_device,
0803     .setup      = sa1100_console_setup,
0804     .flags      = CON_PRINTBUFFER,
0805     .index      = -1,
0806     .data       = &sa1100_reg,
0807 };
0808 
0809 static int __init sa1100_rs_console_init(void)
0810 {
0811     sa1100_init_ports();
0812     register_console(&sa1100_console);
0813     return 0;
0814 }
0815 console_initcall(sa1100_rs_console_init);
0816 
0817 #define SA1100_CONSOLE  &sa1100_console
0818 #else
0819 #define SA1100_CONSOLE  NULL
0820 #endif
0821 
0822 static struct uart_driver sa1100_reg = {
0823     .owner          = THIS_MODULE,
0824     .driver_name        = "ttySA",
0825     .dev_name       = "ttySA",
0826     .major          = SERIAL_SA1100_MAJOR,
0827     .minor          = MINOR_START,
0828     .nr         = NR_PORTS,
0829     .cons           = SA1100_CONSOLE,
0830 };
0831 
0832 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
0833 {
0834     struct sa1100_port *sport = platform_get_drvdata(dev);
0835 
0836     if (sport)
0837         uart_suspend_port(&sa1100_reg, &sport->port);
0838 
0839     return 0;
0840 }
0841 
0842 static int sa1100_serial_resume(struct platform_device *dev)
0843 {
0844     struct sa1100_port *sport = platform_get_drvdata(dev);
0845 
0846     if (sport)
0847         uart_resume_port(&sa1100_reg, &sport->port);
0848 
0849     return 0;
0850 }
0851 
0852 static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
0853 {
0854     sport->port.dev = &dev->dev;
0855     sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);
0856 
0857     // mctrl_gpio_init() requires that the GPIO driver supports interrupts,
0858     // but we need to support GPIO drivers for hardware that has no such
0859     // interrupts.  Use mctrl_gpio_init_noauto() instead.
0860     sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
0861     if (IS_ERR(sport->gpios)) {
0862         int err = PTR_ERR(sport->gpios);
0863 
0864         dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
0865             err);
0866 
0867         if (err == -EPROBE_DEFER)
0868             return err;
0869 
0870         sport->gpios = NULL;
0871     }
0872 
0873     platform_set_drvdata(dev, sport);
0874 
0875     return uart_add_one_port(&sa1100_reg, &sport->port);
0876 }
0877 
0878 static int sa1100_serial_probe(struct platform_device *dev)
0879 {
0880     struct resource *res;
0881     int i;
0882 
0883     res = platform_get_resource(dev, IORESOURCE_MEM, 0);
0884     if (!res)
0885         return -EINVAL;
0886 
0887     for (i = 0; i < NR_PORTS; i++)
0888         if (sa1100_ports[i].port.mapbase == res->start)
0889             break;
0890     if (i == NR_PORTS)
0891         return -ENODEV;
0892 
0893     sa1100_serial_add_one_port(&sa1100_ports[i], dev);
0894 
0895     return 0;
0896 }
0897 
0898 static int sa1100_serial_remove(struct platform_device *pdev)
0899 {
0900     struct sa1100_port *sport = platform_get_drvdata(pdev);
0901 
0902     if (sport)
0903         uart_remove_one_port(&sa1100_reg, &sport->port);
0904 
0905     return 0;
0906 }
0907 
0908 static struct platform_driver sa11x0_serial_driver = {
0909     .probe      = sa1100_serial_probe,
0910     .remove     = sa1100_serial_remove,
0911     .suspend    = sa1100_serial_suspend,
0912     .resume     = sa1100_serial_resume,
0913     .driver     = {
0914         .name   = "sa11x0-uart",
0915     },
0916 };
0917 
0918 static int __init sa1100_serial_init(void)
0919 {
0920     int ret;
0921 
0922     printk(KERN_INFO "Serial: SA11x0 driver\n");
0923 
0924     sa1100_init_ports();
0925 
0926     ret = uart_register_driver(&sa1100_reg);
0927     if (ret == 0) {
0928         ret = platform_driver_register(&sa11x0_serial_driver);
0929         if (ret)
0930             uart_unregister_driver(&sa1100_reg);
0931     }
0932     return ret;
0933 }
0934 
0935 static void __exit sa1100_serial_exit(void)
0936 {
0937     platform_driver_unregister(&sa11x0_serial_driver);
0938     uart_unregister_driver(&sa1100_reg);
0939 }
0940 
0941 module_init(sa1100_serial_init);
0942 module_exit(sa1100_serial_exit);
0943 
0944 MODULE_AUTHOR("Deep Blue Solutions Ltd");
0945 MODULE_DESCRIPTION("SA1100 generic serial port driver");
0946 MODULE_LICENSE("GPL");
0947 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
0948 MODULE_ALIAS("platform:sa11x0-uart");
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