Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
0004  *
0005  * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
0006  *
0007  * Inspired by, and loosely based on:
0008  *
0009  *   ar933x_uart.c
0010  *     Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
0011  *
0012  *   rocketport_infinity_express-linux-1.20.tar.gz
0013  *     Copyright (C) 2004-2011 Comtrol, Inc.
0014  */
0015 
0016 #include <linux/bitops.h>
0017 #include <linux/compiler.h>
0018 #include <linux/completion.h>
0019 #include <linux/console.h>
0020 #include <linux/delay.h>
0021 #include <linux/firmware.h>
0022 #include <linux/init.h>
0023 #include <linux/io.h>
0024 #include <linux/ioport.h>
0025 #include <linux/irq.h>
0026 #include <linux/kernel.h>
0027 #include <linux/log2.h>
0028 #include <linux/module.h>
0029 #include <linux/pci.h>
0030 #include <linux/serial.h>
0031 #include <linux/serial_core.h>
0032 #include <linux/slab.h>
0033 #include <linux/sysrq.h>
0034 #include <linux/tty.h>
0035 #include <linux/tty_flip.h>
0036 #include <linux/types.h>
0037 
0038 #define DRV_NAME            "rp2"
0039 
0040 #define RP2_FW_NAME         "rp2.fw"
0041 #define RP2_UCODE_BYTES         0x3f
0042 
0043 #define PORTS_PER_ASIC          16
0044 #define ALL_PORTS_MASK          (BIT(PORTS_PER_ASIC) - 1)
0045 
0046 #define UART_CLOCK          44236800
0047 #define DEFAULT_BAUD_DIV        (UART_CLOCK / (9600 * 16))
0048 #define FIFO_SIZE           512
0049 
0050 /* BAR0 registers */
0051 #define RP2_FPGA_CTL0           0x110
0052 #define RP2_FPGA_CTL1           0x11c
0053 #define RP2_IRQ_MASK            0x1ec
0054 #define RP2_IRQ_MASK_EN_m       BIT(0)
0055 #define RP2_IRQ_STATUS          0x1f0
0056 
0057 /* BAR1 registers */
0058 #define RP2_ASIC_SPACING        0x1000
0059 #define RP2_ASIC_OFFSET(i)      ((i) << ilog2(RP2_ASIC_SPACING))
0060 
0061 #define RP2_PORT_BASE           0x000
0062 #define RP2_PORT_SPACING        0x040
0063 
0064 #define RP2_UCODE_BASE          0x400
0065 #define RP2_UCODE_SPACING       0x80
0066 
0067 #define RP2_CLK_PRESCALER       0xc00
0068 #define RP2_CH_IRQ_STAT         0xc04
0069 #define RP2_CH_IRQ_MASK         0xc08
0070 #define RP2_ASIC_IRQ            0xd00
0071 #define RP2_ASIC_IRQ_EN_m       BIT(20)
0072 #define RP2_GLOBAL_CMD          0xd0c
0073 #define RP2_ASIC_CFG            0xd04
0074 
0075 /* port registers */
0076 #define RP2_DATA_DWORD          0x000
0077 
0078 #define RP2_DATA_BYTE           0x008
0079 #define RP2_DATA_BYTE_ERR_PARITY_m  BIT(8)
0080 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
0081 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
0082 #define RP2_DATA_BYTE_BREAK_m       BIT(11)
0083 
0084 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
0085 #define RP2_DUMMY_READ          BIT(16)
0086 
0087 #define RP2_DATA_BYTE_EXCEPTION_MASK    (RP2_DATA_BYTE_ERR_PARITY_m | \
0088                      RP2_DATA_BYTE_ERR_OVERRUN_m | \
0089                      RP2_DATA_BYTE_ERR_FRAMING_m | \
0090                      RP2_DATA_BYTE_BREAK_m)
0091 
0092 #define RP2_RX_FIFO_COUNT       0x00c
0093 #define RP2_TX_FIFO_COUNT       0x00e
0094 
0095 #define RP2_CHAN_STAT           0x010
0096 #define RP2_CHAN_STAT_RXDATA_m      BIT(0)
0097 #define RP2_CHAN_STAT_DCD_m     BIT(3)
0098 #define RP2_CHAN_STAT_DSR_m     BIT(4)
0099 #define RP2_CHAN_STAT_CTS_m     BIT(5)
0100 #define RP2_CHAN_STAT_RI_m      BIT(6)
0101 #define RP2_CHAN_STAT_OVERRUN_m     BIT(13)
0102 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
0103 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
0104 #define RP2_CHAN_STAT_CD_CHANGED_m  BIT(18)
0105 #define RP2_CHAN_STAT_RI_CHANGED_m  BIT(22)
0106 #define RP2_CHAN_STAT_TXEMPTY_m     BIT(25)
0107 
0108 #define RP2_CHAN_STAT_MS_CHANGED_MASK   (RP2_CHAN_STAT_DSR_CHANGED_m | \
0109                      RP2_CHAN_STAT_CTS_CHANGED_m | \
0110                      RP2_CHAN_STAT_CD_CHANGED_m | \
0111                      RP2_CHAN_STAT_RI_CHANGED_m)
0112 
0113 #define RP2_TXRX_CTL            0x014
0114 #define RP2_TXRX_CTL_MSRIRQ_m       BIT(0)
0115 #define RP2_TXRX_CTL_RXIRQ_m        BIT(2)
0116 #define RP2_TXRX_CTL_RX_TRIG_s      3
0117 #define RP2_TXRX_CTL_RX_TRIG_m      (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
0118 #define RP2_TXRX_CTL_RX_TRIG_1      (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
0119 #define RP2_TXRX_CTL_RX_TRIG_256    (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
0120 #define RP2_TXRX_CTL_RX_TRIG_448    (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
0121 #define RP2_TXRX_CTL_RX_EN_m        BIT(5)
0122 #define RP2_TXRX_CTL_RTSFLOW_m      BIT(6)
0123 #define RP2_TXRX_CTL_DTRFLOW_m      BIT(7)
0124 #define RP2_TXRX_CTL_TX_TRIG_s      16
0125 #define RP2_TXRX_CTL_TX_TRIG_m      (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
0126 #define RP2_TXRX_CTL_DSRFLOW_m      BIT(18)
0127 #define RP2_TXRX_CTL_TXIRQ_m        BIT(19)
0128 #define RP2_TXRX_CTL_CTSFLOW_m      BIT(23)
0129 #define RP2_TXRX_CTL_TX_EN_m        BIT(24)
0130 #define RP2_TXRX_CTL_RTS_m      BIT(25)
0131 #define RP2_TXRX_CTL_DTR_m      BIT(26)
0132 #define RP2_TXRX_CTL_LOOP_m     BIT(27)
0133 #define RP2_TXRX_CTL_BREAK_m        BIT(28)
0134 #define RP2_TXRX_CTL_CMSPAR_m       BIT(29)
0135 #define RP2_TXRX_CTL_nPARODD_m      BIT(30)
0136 #define RP2_TXRX_CTL_PARENB_m       BIT(31)
0137 
0138 #define RP2_UART_CTL            0x018
0139 #define RP2_UART_CTL_MODE_s     0
0140 #define RP2_UART_CTL_MODE_m     (0x7 << RP2_UART_CTL_MODE_s)
0141 #define RP2_UART_CTL_MODE_rs232     (0x1 << RP2_UART_CTL_MODE_s)
0142 #define RP2_UART_CTL_FLUSH_RX_m     BIT(3)
0143 #define RP2_UART_CTL_FLUSH_TX_m     BIT(4)
0144 #define RP2_UART_CTL_RESET_CH_m     BIT(5)
0145 #define RP2_UART_CTL_XMIT_EN_m      BIT(6)
0146 #define RP2_UART_CTL_DATABITS_s     8
0147 #define RP2_UART_CTL_DATABITS_m     (0x3 << RP2_UART_CTL_DATABITS_s)
0148 #define RP2_UART_CTL_DATABITS_8     (0x3 << RP2_UART_CTL_DATABITS_s)
0149 #define RP2_UART_CTL_DATABITS_7     (0x2 << RP2_UART_CTL_DATABITS_s)
0150 #define RP2_UART_CTL_DATABITS_6     (0x1 << RP2_UART_CTL_DATABITS_s)
0151 #define RP2_UART_CTL_DATABITS_5     (0x0 << RP2_UART_CTL_DATABITS_s)
0152 #define RP2_UART_CTL_STOPBITS_m     BIT(10)
0153 
0154 #define RP2_BAUD            0x01c
0155 
0156 /* ucode registers */
0157 #define RP2_TX_SWFLOW           0x02
0158 #define RP2_TX_SWFLOW_ena       0x81
0159 #define RP2_TX_SWFLOW_dis       0x9d
0160 
0161 #define RP2_RX_SWFLOW           0x0c
0162 #define RP2_RX_SWFLOW_ena       0x81
0163 #define RP2_RX_SWFLOW_dis       0x8d
0164 
0165 #define RP2_RX_FIFO         0x37
0166 #define RP2_RX_FIFO_ena         0x08
0167 #define RP2_RX_FIFO_dis         0x81
0168 
0169 static struct uart_driver rp2_uart_driver = {
0170     .owner              = THIS_MODULE,
0171     .driver_name            = DRV_NAME,
0172     .dev_name           = "ttyRP",
0173     .nr             = CONFIG_SERIAL_RP2_NR_UARTS,
0174 };
0175 
0176 struct rp2_card;
0177 
0178 struct rp2_uart_port {
0179     struct uart_port        port;
0180     int             idx;
0181     int             ignore_rx;
0182     struct rp2_card         *card;
0183     void __iomem            *asic_base;
0184     void __iomem            *base;
0185     void __iomem            *ucode;
0186 };
0187 
0188 struct rp2_card {
0189     struct pci_dev          *pdev;
0190     struct rp2_uart_port        *ports;
0191     int             n_ports;
0192     int             initialized_ports;
0193     int             minor_start;
0194     int             smpte;
0195     void __iomem            *bar0;
0196     void __iomem            *bar1;
0197     spinlock_t          card_lock;
0198 };
0199 
0200 #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
0201 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
0202 
0203 static inline void rp2_decode_cap(const struct pci_device_id *id,
0204                   int *ports, int *smpte)
0205 {
0206     *ports = id->driver_data >> 8;
0207     *smpte = id->driver_data & 0xff;
0208 }
0209 
0210 static DEFINE_SPINLOCK(rp2_minor_lock);
0211 static int rp2_minor_next;
0212 
0213 static int rp2_alloc_ports(int n_ports)
0214 {
0215     int ret = -ENOSPC;
0216 
0217     spin_lock(&rp2_minor_lock);
0218     if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
0219         /* sorry, no support for hot unplugging individual cards */
0220         ret = rp2_minor_next;
0221         rp2_minor_next += n_ports;
0222     }
0223     spin_unlock(&rp2_minor_lock);
0224 
0225     return ret;
0226 }
0227 
0228 static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
0229 {
0230     return container_of(port, struct rp2_uart_port, port);
0231 }
0232 
0233 static void rp2_rmw(struct rp2_uart_port *up, int reg,
0234             u32 clr_bits, u32 set_bits)
0235 {
0236     u32 tmp = readl(up->base + reg);
0237     tmp &= ~clr_bits;
0238     tmp |= set_bits;
0239     writel(tmp, up->base + reg);
0240 }
0241 
0242 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
0243 {
0244     rp2_rmw(up, reg, val, 0);
0245 }
0246 
0247 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
0248 {
0249     rp2_rmw(up, reg, 0, val);
0250 }
0251 
0252 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
0253                 int is_enabled)
0254 {
0255     unsigned long flags, irq_mask;
0256 
0257     spin_lock_irqsave(&up->card->card_lock, flags);
0258 
0259     irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
0260     if (is_enabled)
0261         irq_mask &= ~BIT(ch_num);
0262     else
0263         irq_mask |= BIT(ch_num);
0264     writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
0265 
0266     spin_unlock_irqrestore(&up->card->card_lock, flags);
0267 }
0268 
0269 static unsigned int rp2_uart_tx_empty(struct uart_port *port)
0270 {
0271     struct rp2_uart_port *up = port_to_up(port);
0272     unsigned long tx_fifo_bytes, flags;
0273 
0274     /*
0275      * This should probably check the transmitter, not the FIFO.
0276      * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
0277      * enabled.
0278      */
0279     spin_lock_irqsave(&up->port.lock, flags);
0280     tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
0281     spin_unlock_irqrestore(&up->port.lock, flags);
0282 
0283     return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
0284 }
0285 
0286 static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
0287 {
0288     struct rp2_uart_port *up = port_to_up(port);
0289     u32 status;
0290 
0291     status = readl(up->base + RP2_CHAN_STAT);
0292     return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
0293            ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
0294            ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
0295            ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
0296 }
0297 
0298 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0299 {
0300     rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
0301         RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
0302         ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
0303         ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
0304         ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
0305 }
0306 
0307 static void rp2_uart_start_tx(struct uart_port *port)
0308 {
0309     rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
0310 }
0311 
0312 static void rp2_uart_stop_tx(struct uart_port *port)
0313 {
0314     rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
0315 }
0316 
0317 static void rp2_uart_stop_rx(struct uart_port *port)
0318 {
0319     rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
0320 }
0321 
0322 static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
0323 {
0324     unsigned long flags;
0325 
0326     spin_lock_irqsave(&port->lock, flags);
0327     rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
0328         break_state ? RP2_TXRX_CTL_BREAK_m : 0);
0329     spin_unlock_irqrestore(&port->lock, flags);
0330 }
0331 
0332 static void rp2_uart_enable_ms(struct uart_port *port)
0333 {
0334     rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
0335 }
0336 
0337 static void __rp2_uart_set_termios(struct rp2_uart_port *up,
0338                    unsigned long cfl,
0339                    unsigned long ifl,
0340                    unsigned int baud_div)
0341 {
0342     /* baud rate divisor (calculated elsewhere).  0 = divide-by-1 */
0343     writew(baud_div - 1, up->base + RP2_BAUD);
0344 
0345     /* data bits and stop bits */
0346     rp2_rmw(up, RP2_UART_CTL,
0347         RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
0348         ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
0349         (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
0350         (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
0351         (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
0352         (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
0353 
0354     /* parity and hardware flow control */
0355     rp2_rmw(up, RP2_TXRX_CTL,
0356         RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
0357         RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
0358         RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
0359         RP2_TXRX_CTL_CTSFLOW_m,
0360         ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
0361         ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
0362         ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
0363         ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
0364                     RP2_TXRX_CTL_CTSFLOW_m) : 0));
0365 
0366     /* XON/XOFF software flow control */
0367     writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
0368            up->ucode + RP2_TX_SWFLOW);
0369     writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
0370            up->ucode + RP2_RX_SWFLOW);
0371 }
0372 
0373 static void rp2_uart_set_termios(struct uart_port *port,
0374                  struct ktermios *new,
0375                  struct ktermios *old)
0376 {
0377     struct rp2_uart_port *up = port_to_up(port);
0378     unsigned long flags;
0379     unsigned int baud, baud_div;
0380 
0381     baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
0382     baud_div = uart_get_divisor(port, baud);
0383 
0384     if (tty_termios_baud_rate(new))
0385         tty_termios_encode_baud_rate(new, baud, baud);
0386 
0387     spin_lock_irqsave(&port->lock, flags);
0388 
0389     /* ignore all characters if CREAD is not set */
0390     port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
0391 
0392     __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
0393     uart_update_timeout(port, new->c_cflag, baud);
0394 
0395     spin_unlock_irqrestore(&port->lock, flags);
0396 }
0397 
0398 static void rp2_rx_chars(struct rp2_uart_port *up)
0399 {
0400     u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
0401     struct tty_port *port = &up->port.state->port;
0402 
0403     for (; bytes != 0; bytes--) {
0404         u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
0405         char ch = byte & 0xff;
0406 
0407         if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
0408             if (!uart_handle_sysrq_char(&up->port, ch))
0409                 uart_insert_char(&up->port, byte, 0, ch,
0410                          TTY_NORMAL);
0411         } else {
0412             char flag = TTY_NORMAL;
0413 
0414             if (byte & RP2_DATA_BYTE_BREAK_m)
0415                 flag = TTY_BREAK;
0416             else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
0417                 flag = TTY_FRAME;
0418             else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
0419                 flag = TTY_PARITY;
0420             uart_insert_char(&up->port, byte,
0421                      RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
0422         }
0423         up->port.icount.rx++;
0424     }
0425 
0426     tty_flip_buffer_push(port);
0427 }
0428 
0429 static void rp2_tx_chars(struct rp2_uart_port *up)
0430 {
0431     u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
0432     struct circ_buf *xmit = &up->port.state->xmit;
0433 
0434     if (uart_tx_stopped(&up->port)) {
0435         rp2_uart_stop_tx(&up->port);
0436         return;
0437     }
0438 
0439     for (; max_tx != 0; max_tx--) {
0440         if (up->port.x_char) {
0441             writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
0442             up->port.x_char = 0;
0443             up->port.icount.tx++;
0444             continue;
0445         }
0446         if (uart_circ_empty(xmit)) {
0447             rp2_uart_stop_tx(&up->port);
0448             break;
0449         }
0450         writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
0451         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0452         up->port.icount.tx++;
0453     }
0454 
0455     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0456         uart_write_wakeup(&up->port);
0457 }
0458 
0459 static void rp2_ch_interrupt(struct rp2_uart_port *up)
0460 {
0461     u32 status;
0462 
0463     spin_lock(&up->port.lock);
0464 
0465     /*
0466      * The IRQ status bits are clear-on-write.  Other status bits in
0467      * this register aren't, so it's harmless to write to them.
0468      */
0469     status = readl(up->base + RP2_CHAN_STAT);
0470     writel(status, up->base + RP2_CHAN_STAT);
0471 
0472     if (status & RP2_CHAN_STAT_RXDATA_m)
0473         rp2_rx_chars(up);
0474     if (status & RP2_CHAN_STAT_TXEMPTY_m)
0475         rp2_tx_chars(up);
0476     if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
0477         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
0478 
0479     spin_unlock(&up->port.lock);
0480 }
0481 
0482 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
0483 {
0484     void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
0485     int ch, handled = 0;
0486     unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
0487                    ~readl(base + RP2_CH_IRQ_MASK);
0488 
0489     for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
0490         rp2_ch_interrupt(&card->ports[ch]);
0491         handled++;
0492     }
0493     return handled;
0494 }
0495 
0496 static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
0497 {
0498     struct rp2_card *card = dev_id;
0499     int handled;
0500 
0501     handled = rp2_asic_interrupt(card, 0);
0502     if (card->n_ports >= PORTS_PER_ASIC)
0503         handled += rp2_asic_interrupt(card, 1);
0504 
0505     return handled ? IRQ_HANDLED : IRQ_NONE;
0506 }
0507 
0508 static inline void rp2_flush_fifos(struct rp2_uart_port *up)
0509 {
0510     rp2_rmw_set(up, RP2_UART_CTL,
0511             RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
0512     readl(up->base + RP2_UART_CTL);
0513     udelay(10);
0514     rp2_rmw_clr(up, RP2_UART_CTL,
0515             RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
0516 }
0517 
0518 static int rp2_uart_startup(struct uart_port *port)
0519 {
0520     struct rp2_uart_port *up = port_to_up(port);
0521 
0522     rp2_flush_fifos(up);
0523     rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
0524     rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
0525         RP2_TXRX_CTL_RX_TRIG_1);
0526     rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
0527     rp2_mask_ch_irq(up, up->idx, 1);
0528 
0529     return 0;
0530 }
0531 
0532 static void rp2_uart_shutdown(struct uart_port *port)
0533 {
0534     struct rp2_uart_port *up = port_to_up(port);
0535     unsigned long flags;
0536 
0537     rp2_uart_break_ctl(port, 0);
0538 
0539     spin_lock_irqsave(&port->lock, flags);
0540     rp2_mask_ch_irq(up, up->idx, 0);
0541     rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
0542     spin_unlock_irqrestore(&port->lock, flags);
0543 }
0544 
0545 static const char *rp2_uart_type(struct uart_port *port)
0546 {
0547     return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
0548 }
0549 
0550 static void rp2_uart_release_port(struct uart_port *port)
0551 {
0552     /* Nothing to release ... */
0553 }
0554 
0555 static int rp2_uart_request_port(struct uart_port *port)
0556 {
0557     /* UARTs always present */
0558     return 0;
0559 }
0560 
0561 static void rp2_uart_config_port(struct uart_port *port, int flags)
0562 {
0563     if (flags & UART_CONFIG_TYPE)
0564         port->type = PORT_RP2;
0565 }
0566 
0567 static int rp2_uart_verify_port(struct uart_port *port,
0568                    struct serial_struct *ser)
0569 {
0570     if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
0571         return -EINVAL;
0572 
0573     return 0;
0574 }
0575 
0576 static const struct uart_ops rp2_uart_ops = {
0577     .tx_empty   = rp2_uart_tx_empty,
0578     .set_mctrl  = rp2_uart_set_mctrl,
0579     .get_mctrl  = rp2_uart_get_mctrl,
0580     .stop_tx    = rp2_uart_stop_tx,
0581     .start_tx   = rp2_uart_start_tx,
0582     .stop_rx    = rp2_uart_stop_rx,
0583     .enable_ms  = rp2_uart_enable_ms,
0584     .break_ctl  = rp2_uart_break_ctl,
0585     .startup    = rp2_uart_startup,
0586     .shutdown   = rp2_uart_shutdown,
0587     .set_termios    = rp2_uart_set_termios,
0588     .type       = rp2_uart_type,
0589     .release_port   = rp2_uart_release_port,
0590     .request_port   = rp2_uart_request_port,
0591     .config_port    = rp2_uart_config_port,
0592     .verify_port    = rp2_uart_verify_port,
0593 };
0594 
0595 static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
0596 {
0597     void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
0598     u32 clk_cfg;
0599 
0600     writew(1, base + RP2_GLOBAL_CMD);
0601     readw(base + RP2_GLOBAL_CMD);
0602     msleep(100);
0603     writel(0, base + RP2_CLK_PRESCALER);
0604 
0605     /* TDM clock configuration */
0606     clk_cfg = readw(base + RP2_ASIC_CFG);
0607     clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
0608     writew(clk_cfg, base + RP2_ASIC_CFG);
0609 
0610     /* IRQ routing */
0611     writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
0612     writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
0613 }
0614 
0615 static void rp2_init_card(struct rp2_card *card)
0616 {
0617     writel(4, card->bar0 + RP2_FPGA_CTL0);
0618     writel(0, card->bar0 + RP2_FPGA_CTL1);
0619 
0620     rp2_reset_asic(card, 0);
0621     if (card->n_ports >= PORTS_PER_ASIC)
0622         rp2_reset_asic(card, 1);
0623 
0624     writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
0625 }
0626 
0627 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
0628 {
0629     int i;
0630 
0631     writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
0632     readl(up->base + RP2_UART_CTL);
0633     udelay(1);
0634 
0635     writel(0, up->base + RP2_TXRX_CTL);
0636     writel(0, up->base + RP2_UART_CTL);
0637     readl(up->base + RP2_UART_CTL);
0638     udelay(1);
0639 
0640     rp2_flush_fifos(up);
0641 
0642     for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
0643         writeb(fw->data[i], up->ucode + i);
0644 
0645     __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
0646     rp2_uart_set_mctrl(&up->port, 0);
0647 
0648     writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
0649     rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
0650         RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
0651     rp2_rmw_set(up, RP2_TXRX_CTL,
0652             RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
0653 }
0654 
0655 static void rp2_remove_ports(struct rp2_card *card)
0656 {
0657     int i;
0658 
0659     for (i = 0; i < card->initialized_ports; i++)
0660         uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
0661     card->initialized_ports = 0;
0662 }
0663 
0664 static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
0665 {
0666     resource_size_t phys_base;
0667     int i, rc = 0;
0668 
0669     phys_base = pci_resource_start(card->pdev, 1);
0670 
0671     for (i = 0; i < card->n_ports; i++) {
0672         struct rp2_uart_port *rp = &card->ports[i];
0673         struct uart_port *p;
0674         int j = (unsigned)i % PORTS_PER_ASIC;
0675 
0676         rp->asic_base = card->bar1;
0677         rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
0678         rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
0679         rp->card = card;
0680         rp->idx = j;
0681 
0682         p = &rp->port;
0683         p->line = card->minor_start + i;
0684         p->dev = &card->pdev->dev;
0685         p->type = PORT_RP2;
0686         p->iotype = UPIO_MEM32;
0687         p->uartclk = UART_CLOCK;
0688         p->regshift = 2;
0689         p->fifosize = FIFO_SIZE;
0690         p->ops = &rp2_uart_ops;
0691         p->irq = card->pdev->irq;
0692         p->membase = rp->base;
0693         p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
0694 
0695         if (i >= PORTS_PER_ASIC) {
0696             rp->asic_base += RP2_ASIC_SPACING;
0697             rp->base += RP2_ASIC_SPACING;
0698             rp->ucode += RP2_ASIC_SPACING;
0699             p->mapbase += RP2_ASIC_SPACING;
0700         }
0701 
0702         rp2_init_port(rp, fw);
0703         rc = uart_add_one_port(&rp2_uart_driver, p);
0704         if (rc) {
0705             dev_err(&card->pdev->dev,
0706                 "error registering port %d: %d\n", i, rc);
0707             rp2_remove_ports(card);
0708             break;
0709         }
0710         card->initialized_ports++;
0711     }
0712 
0713     return rc;
0714 }
0715 
0716 static int rp2_probe(struct pci_dev *pdev,
0717                    const struct pci_device_id *id)
0718 {
0719     const struct firmware *fw;
0720     struct rp2_card *card;
0721     struct rp2_uart_port *ports;
0722     void __iomem * const *bars;
0723     int rc;
0724 
0725     card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
0726     if (!card)
0727         return -ENOMEM;
0728     pci_set_drvdata(pdev, card);
0729     spin_lock_init(&card->card_lock);
0730 
0731     rc = pcim_enable_device(pdev);
0732     if (rc)
0733         return rc;
0734 
0735     rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
0736     if (rc)
0737         return rc;
0738 
0739     bars = pcim_iomap_table(pdev);
0740     card->bar0 = bars[0];
0741     card->bar1 = bars[1];
0742     card->pdev = pdev;
0743 
0744     rp2_decode_cap(id, &card->n_ports, &card->smpte);
0745     dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
0746 
0747     card->minor_start = rp2_alloc_ports(card->n_ports);
0748     if (card->minor_start < 0) {
0749         dev_err(&pdev->dev,
0750             "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
0751         return -EINVAL;
0752     }
0753 
0754     rp2_init_card(card);
0755 
0756     ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
0757                  GFP_KERNEL);
0758     if (!ports)
0759         return -ENOMEM;
0760     card->ports = ports;
0761 
0762     rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
0763     if (rc < 0) {
0764         dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
0765             RP2_FW_NAME);
0766         return rc;
0767     }
0768 
0769     rc = rp2_load_firmware(card, fw);
0770 
0771     release_firmware(fw);
0772     if (rc < 0)
0773         return rc;
0774 
0775     rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
0776                   IRQF_SHARED, DRV_NAME, card);
0777     if (rc)
0778         return rc;
0779 
0780     return 0;
0781 }
0782 
0783 static void rp2_remove(struct pci_dev *pdev)
0784 {
0785     struct rp2_card *card = pci_get_drvdata(pdev);
0786 
0787     rp2_remove_ports(card);
0788 }
0789 
0790 static const struct pci_device_id rp2_pci_tbl[] = {
0791 
0792     /* RocketPort INFINITY cards */
0793 
0794     { RP_ID(0x0040), RP_CAP(8,  0) }, /* INF Octa, RJ45, selectable */
0795     { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
0796     { RP_ID(0x0042), RP_CAP(8,  0) }, /* INF Octa, ext interface */
0797     { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
0798     { RP_ID(0x0044), RP_CAP(4,  0) }, /* INF Quad, DB, selectable */
0799     { RP_ID(0x0045), RP_CAP(8,  0) }, /* INF Octa, DB, selectable */
0800     { RP_ID(0x0046), RP_CAP(4,  0) }, /* INF Quad, ext interface */
0801     { RP_ID(0x0047), RP_CAP(4,  0) }, /* INF Quad, RJ45 */
0802     { RP_ID(0x004a), RP_CAP(4,  0) }, /* INF Plus, Quad */
0803     { RP_ID(0x004b), RP_CAP(8,  0) }, /* INF Plus, Octa */
0804     { RP_ID(0x004c), RP_CAP(8,  0) }, /* INF III, Octa */
0805     { RP_ID(0x004d), RP_CAP(4,  0) }, /* INF III, Quad */
0806     { RP_ID(0x004e), RP_CAP(2,  0) }, /* INF Plus, 2, RS232 */
0807     { RP_ID(0x004f), RP_CAP(2,  1) }, /* INF Plus, 2, SMPTE */
0808     { RP_ID(0x0050), RP_CAP(4,  0) }, /* INF Plus, Quad, RJ45 */
0809     { RP_ID(0x0051), RP_CAP(8,  0) }, /* INF Plus, Octa, RJ45 */
0810     { RP_ID(0x0052), RP_CAP(8,  1) }, /* INF Octa, SMPTE */
0811 
0812     /* RocketPort EXPRESS cards */
0813 
0814     { RP_ID(0x0060), RP_CAP(8,  0) }, /* EXP Octa, RJ45, selectable */
0815     { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
0816     { RP_ID(0x0062), RP_CAP(8,  0) }, /* EXP Octa, ext interface */
0817     { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
0818     { RP_ID(0x0064), RP_CAP(4,  0) }, /* EXP Quad, DB, selectable */
0819     { RP_ID(0x0065), RP_CAP(8,  0) }, /* EXP Octa, DB, selectable */
0820     { RP_ID(0x0066), RP_CAP(4,  0) }, /* EXP Quad, ext interface */
0821     { RP_ID(0x0067), RP_CAP(4,  0) }, /* EXP Quad, RJ45 */
0822     { RP_ID(0x0068), RP_CAP(8,  0) }, /* EXP Octa, RJ11 */
0823     { RP_ID(0x0072), RP_CAP(8,  1) }, /* EXP Octa, SMPTE */
0824     { }
0825 };
0826 MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
0827 
0828 static struct pci_driver rp2_pci_driver = {
0829     .name       = DRV_NAME,
0830     .id_table   = rp2_pci_tbl,
0831     .probe      = rp2_probe,
0832     .remove     = rp2_remove,
0833 };
0834 
0835 static int __init rp2_uart_init(void)
0836 {
0837     int rc;
0838 
0839     rc = uart_register_driver(&rp2_uart_driver);
0840     if (rc)
0841         return rc;
0842 
0843     rc = pci_register_driver(&rp2_pci_driver);
0844     if (rc) {
0845         uart_unregister_driver(&rp2_uart_driver);
0846         return rc;
0847     }
0848 
0849     return 0;
0850 }
0851 
0852 static void __exit rp2_uart_exit(void)
0853 {
0854     pci_unregister_driver(&rp2_pci_driver);
0855     uart_unregister_driver(&rp2_uart_driver);
0856 }
0857 
0858 module_init(rp2_uart_init);
0859 module_exit(rp2_uart_exit);
0860 
0861 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
0862 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
0863 MODULE_LICENSE("GPL v2");
0864 MODULE_FIRMWARE(RP2_FW_NAME);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!