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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
0003 
0004 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
0005 #define __DISABLE_TRACE_MMIO__
0006 
0007 #include <linux/clk.h>
0008 #include <linux/console.h>
0009 #include <linux/io.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/irq.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/pm_opp.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/qcom-geni-se.h>
0020 #include <linux/serial.h>
0021 #include <linux/serial_core.h>
0022 #include <linux/slab.h>
0023 #include <linux/tty.h>
0024 #include <linux/tty_flip.h>
0025 
0026 /* UART specific GENI registers */
0027 #define SE_UART_LOOPBACK_CFG        0x22c
0028 #define SE_UART_IO_MACRO_CTRL       0x240
0029 #define SE_UART_TX_TRANS_CFG        0x25c
0030 #define SE_UART_TX_WORD_LEN     0x268
0031 #define SE_UART_TX_STOP_BIT_LEN     0x26c
0032 #define SE_UART_TX_TRANS_LEN        0x270
0033 #define SE_UART_RX_TRANS_CFG        0x280
0034 #define SE_UART_RX_WORD_LEN     0x28c
0035 #define SE_UART_RX_STALE_CNT        0x294
0036 #define SE_UART_TX_PARITY_CFG       0x2a4
0037 #define SE_UART_RX_PARITY_CFG       0x2a8
0038 #define SE_UART_MANUAL_RFR      0x2ac
0039 
0040 /* SE_UART_TRANS_CFG */
0041 #define UART_TX_PAR_EN      BIT(0)
0042 #define UART_CTS_MASK       BIT(1)
0043 
0044 /* SE_UART_TX_WORD_LEN */
0045 #define TX_WORD_LEN_MSK     GENMASK(9, 0)
0046 
0047 /* SE_UART_TX_STOP_BIT_LEN */
0048 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
0049 #define TX_STOP_BIT_LEN_1   0
0050 #define TX_STOP_BIT_LEN_1_5 1
0051 #define TX_STOP_BIT_LEN_2   2
0052 
0053 /* SE_UART_TX_TRANS_LEN */
0054 #define TX_TRANS_LEN_MSK    GENMASK(23, 0)
0055 
0056 /* SE_UART_RX_TRANS_CFG */
0057 #define UART_RX_INS_STATUS_BIT  BIT(2)
0058 #define UART_RX_PAR_EN      BIT(3)
0059 
0060 /* SE_UART_RX_WORD_LEN */
0061 #define RX_WORD_LEN_MASK    GENMASK(9, 0)
0062 
0063 /* SE_UART_RX_STALE_CNT */
0064 #define RX_STALE_CNT        GENMASK(23, 0)
0065 
0066 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
0067 #define PAR_CALC_EN     BIT(0)
0068 #define PAR_MODE_MSK        GENMASK(2, 1)
0069 #define PAR_MODE_SHFT       1
0070 #define PAR_EVEN        0x00
0071 #define PAR_ODD         0x01
0072 #define PAR_SPACE       0x10
0073 #define PAR_MARK        0x11
0074 
0075 /* SE_UART_MANUAL_RFR register fields */
0076 #define UART_MANUAL_RFR_EN  BIT(31)
0077 #define UART_RFR_NOT_READY  BIT(1)
0078 #define UART_RFR_READY      BIT(0)
0079 
0080 /* UART M_CMD OP codes */
0081 #define UART_START_TX       0x1
0082 #define UART_START_BREAK    0x4
0083 #define UART_STOP_BREAK     0x5
0084 /* UART S_CMD OP codes */
0085 #define UART_START_READ     0x1
0086 #define UART_PARAM      0x1
0087 
0088 #define UART_OVERSAMPLING   32
0089 #define STALE_TIMEOUT       16
0090 #define DEFAULT_BITS_PER_CHAR   10
0091 #define GENI_UART_CONS_PORTS    1
0092 #define GENI_UART_PORTS     3
0093 #define DEF_FIFO_DEPTH_WORDS    16
0094 #define DEF_TX_WM       2
0095 #define DEF_FIFO_WIDTH_BITS 32
0096 #define UART_RX_WM      2
0097 
0098 /* SE_UART_LOOPBACK_CFG */
0099 #define RX_TX_SORTED    BIT(0)
0100 #define CTS_RTS_SORTED  BIT(1)
0101 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
0102 
0103 /* UART pin swap value */
0104 #define DEFAULT_IO_MACRO_IO0_IO1_MASK       GENMASK(3, 0)
0105 #define IO_MACRO_IO0_SEL        0x3
0106 #define DEFAULT_IO_MACRO_IO2_IO3_MASK       GENMASK(15, 4)
0107 #define IO_MACRO_IO2_IO3_SWAP       0x4640
0108 
0109 /* We always configure 4 bytes per FIFO word */
0110 #define BYTES_PER_FIFO_WORD     4
0111 
0112 struct qcom_geni_private_data {
0113     /* NOTE: earlycon port will have NULL here */
0114     struct uart_driver *drv;
0115 
0116     u32 poll_cached_bytes;
0117     unsigned int poll_cached_bytes_cnt;
0118 
0119     u32 write_cached_bytes;
0120     unsigned int write_cached_bytes_cnt;
0121 };
0122 
0123 struct qcom_geni_serial_port {
0124     struct uart_port uport;
0125     struct geni_se se;
0126     const char *name;
0127     u32 tx_fifo_depth;
0128     u32 tx_fifo_width;
0129     u32 rx_fifo_depth;
0130     bool setup;
0131     int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
0132     unsigned int baud;
0133     void *rx_fifo;
0134     u32 loopback;
0135     bool brk;
0136 
0137     unsigned int tx_remaining;
0138     int wakeup_irq;
0139     bool rx_tx_swap;
0140     bool cts_rts_swap;
0141 
0142     struct qcom_geni_private_data private_data;
0143 };
0144 
0145 static const struct uart_ops qcom_geni_console_pops;
0146 static const struct uart_ops qcom_geni_uart_pops;
0147 static struct uart_driver qcom_geni_console_driver;
0148 static struct uart_driver qcom_geni_uart_driver;
0149 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
0150 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
0151 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
0152 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
0153 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
0154 
0155 #define to_dev_port(ptr, member) \
0156         container_of(ptr, struct qcom_geni_serial_port, member)
0157 
0158 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
0159     [0] = {
0160         .uport = {
0161                 .iotype = UPIO_MEM,
0162                 .ops = &qcom_geni_uart_pops,
0163                 .flags = UPF_BOOT_AUTOCONF,
0164                 .line = 0,
0165         },
0166     },
0167     [1] = {
0168         .uport = {
0169                 .iotype = UPIO_MEM,
0170                 .ops = &qcom_geni_uart_pops,
0171                 .flags = UPF_BOOT_AUTOCONF,
0172                 .line = 1,
0173         },
0174     },
0175     [2] = {
0176         .uport = {
0177                 .iotype = UPIO_MEM,
0178                 .ops = &qcom_geni_uart_pops,
0179                 .flags = UPF_BOOT_AUTOCONF,
0180                 .line = 2,
0181         },
0182     },
0183 };
0184 
0185 static struct qcom_geni_serial_port qcom_geni_console_port = {
0186     .uport = {
0187         .iotype = UPIO_MEM,
0188         .ops = &qcom_geni_console_pops,
0189         .flags = UPF_BOOT_AUTOCONF,
0190         .line = 0,
0191     },
0192 };
0193 
0194 static int qcom_geni_serial_request_port(struct uart_port *uport)
0195 {
0196     struct platform_device *pdev = to_platform_device(uport->dev);
0197     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0198 
0199     uport->membase = devm_platform_ioremap_resource(pdev, 0);
0200     if (IS_ERR(uport->membase))
0201         return PTR_ERR(uport->membase);
0202     port->se.base = uport->membase;
0203     return 0;
0204 }
0205 
0206 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
0207 {
0208     if (cfg_flags & UART_CONFIG_TYPE) {
0209         uport->type = PORT_MSM;
0210         qcom_geni_serial_request_port(uport);
0211     }
0212 }
0213 
0214 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
0215 {
0216     unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
0217     u32 geni_ios;
0218 
0219     if (uart_console(uport)) {
0220         mctrl |= TIOCM_CTS;
0221     } else {
0222         geni_ios = readl(uport->membase + SE_GENI_IOS);
0223         if (!(geni_ios & IO2_DATA_IN))
0224             mctrl |= TIOCM_CTS;
0225     }
0226 
0227     return mctrl;
0228 }
0229 
0230 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
0231                             unsigned int mctrl)
0232 {
0233     u32 uart_manual_rfr = 0;
0234     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0235 
0236     if (uart_console(uport))
0237         return;
0238 
0239     if (mctrl & TIOCM_LOOP)
0240         port->loopback = RX_TX_CTS_RTS_SORTED;
0241 
0242     if (!(mctrl & TIOCM_RTS) && !uport->suspended)
0243         uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
0244     writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
0245 }
0246 
0247 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
0248 {
0249     return "MSM";
0250 }
0251 
0252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
0253 {
0254     struct qcom_geni_serial_port *port;
0255     int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
0256 
0257     if (line < 0 || line >= nr_ports)
0258         return ERR_PTR(-ENXIO);
0259 
0260     port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
0261     return port;
0262 }
0263 
0264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
0265                 int offset, int field, bool set)
0266 {
0267     u32 reg;
0268     struct qcom_geni_serial_port *port;
0269     unsigned int baud;
0270     unsigned int fifo_bits;
0271     unsigned long timeout_us = 20000;
0272     struct qcom_geni_private_data *private_data = uport->private_data;
0273 
0274     if (private_data->drv) {
0275         port = to_dev_port(uport, uport);
0276         baud = port->baud;
0277         if (!baud)
0278             baud = 115200;
0279         fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
0280         /*
0281          * Total polling iterations based on FIFO worth of bytes to be
0282          * sent at current baud. Add a little fluff to the wait.
0283          */
0284         timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
0285     }
0286 
0287     /*
0288      * Use custom implementation instead of readl_poll_atomic since ktimer
0289      * is not ready at the time of early console.
0290      */
0291     timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
0292     while (timeout_us) {
0293         reg = readl(uport->membase + offset);
0294         if ((bool)(reg & field) == set)
0295             return true;
0296         udelay(10);
0297         timeout_us -= 10;
0298     }
0299     return false;
0300 }
0301 
0302 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
0303 {
0304     u32 m_cmd;
0305 
0306     writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
0307     m_cmd = UART_START_TX << M_OPCODE_SHFT;
0308     writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
0309 }
0310 
0311 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
0312 {
0313     int done;
0314     u32 irq_clear = M_CMD_DONE_EN;
0315 
0316     done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0317                         M_CMD_DONE_EN, true);
0318     if (!done) {
0319         writel(M_GENI_CMD_ABORT, uport->membase +
0320                         SE_GENI_M_CMD_CTRL_REG);
0321         irq_clear |= M_CMD_ABORT_EN;
0322         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0323                             M_CMD_ABORT_EN, true);
0324     }
0325     writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
0326 }
0327 
0328 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
0329 {
0330     u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
0331 
0332     writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
0333     qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
0334                     S_GENI_CMD_ABORT, false);
0335     writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
0336     writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
0337 }
0338 
0339 #ifdef CONFIG_CONSOLE_POLL
0340 
0341 static int qcom_geni_serial_get_char(struct uart_port *uport)
0342 {
0343     struct qcom_geni_private_data *private_data = uport->private_data;
0344     u32 status;
0345     u32 word_cnt;
0346     int ret;
0347 
0348     if (!private_data->poll_cached_bytes_cnt) {
0349         status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
0350         writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
0351 
0352         status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
0353         writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
0354 
0355         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
0356         word_cnt = status & RX_FIFO_WC_MSK;
0357         if (!word_cnt)
0358             return NO_POLL_CHAR;
0359 
0360         if (word_cnt == 1 && (status & RX_LAST))
0361             /*
0362              * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
0363              * treated as if it was BYTES_PER_FIFO_WORD.
0364              */
0365             private_data->poll_cached_bytes_cnt =
0366                 (status & RX_LAST_BYTE_VALID_MSK) >>
0367                 RX_LAST_BYTE_VALID_SHFT;
0368 
0369         if (private_data->poll_cached_bytes_cnt == 0)
0370             private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
0371 
0372         private_data->poll_cached_bytes =
0373             readl(uport->membase + SE_GENI_RX_FIFOn);
0374     }
0375 
0376     private_data->poll_cached_bytes_cnt--;
0377     ret = private_data->poll_cached_bytes & 0xff;
0378     private_data->poll_cached_bytes >>= 8;
0379 
0380     return ret;
0381 }
0382 
0383 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
0384                             unsigned char c)
0385 {
0386     writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
0387     qcom_geni_serial_setup_tx(uport, 1);
0388     WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0389                         M_TX_FIFO_WATERMARK_EN, true));
0390     writel(c, uport->membase + SE_GENI_TX_FIFOn);
0391     writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
0392     qcom_geni_serial_poll_tx_done(uport);
0393 }
0394 #endif
0395 
0396 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
0397 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
0398 {
0399     struct qcom_geni_private_data *private_data = uport->private_data;
0400 
0401     private_data->write_cached_bytes =
0402         (private_data->write_cached_bytes >> 8) | (ch << 24);
0403     private_data->write_cached_bytes_cnt++;
0404 
0405     if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
0406         writel(private_data->write_cached_bytes,
0407                uport->membase + SE_GENI_TX_FIFOn);
0408         private_data->write_cached_bytes_cnt = 0;
0409     }
0410 }
0411 
0412 static void
0413 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
0414                  unsigned int count)
0415 {
0416     struct qcom_geni_private_data *private_data = uport->private_data;
0417 
0418     int i;
0419     u32 bytes_to_send = count;
0420 
0421     for (i = 0; i < count; i++) {
0422         /*
0423          * uart_console_write() adds a carriage return for each newline.
0424          * Account for additional bytes to be written.
0425          */
0426         if (s[i] == '\n')
0427             bytes_to_send++;
0428     }
0429 
0430     writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
0431     qcom_geni_serial_setup_tx(uport, bytes_to_send);
0432     for (i = 0; i < count; ) {
0433         size_t chars_to_write = 0;
0434         size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
0435 
0436         /*
0437          * If the WM bit never set, then the Tx state machine is not
0438          * in a valid state, so break, cancel/abort any existing
0439          * command. Unfortunately the current data being written is
0440          * lost.
0441          */
0442         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0443                         M_TX_FIFO_WATERMARK_EN, true))
0444             break;
0445         chars_to_write = min_t(size_t, count - i, avail / 2);
0446         uart_console_write(uport, s + i, chars_to_write,
0447                         qcom_geni_serial_wr_char);
0448         writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
0449                             SE_GENI_M_IRQ_CLEAR);
0450         i += chars_to_write;
0451     }
0452 
0453     if (private_data->write_cached_bytes_cnt) {
0454         private_data->write_cached_bytes >>= BITS_PER_BYTE *
0455             (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
0456         writel(private_data->write_cached_bytes,
0457                uport->membase + SE_GENI_TX_FIFOn);
0458         private_data->write_cached_bytes_cnt = 0;
0459     }
0460 
0461     qcom_geni_serial_poll_tx_done(uport);
0462 }
0463 
0464 static void qcom_geni_serial_console_write(struct console *co, const char *s,
0465                   unsigned int count)
0466 {
0467     struct uart_port *uport;
0468     struct qcom_geni_serial_port *port;
0469     bool locked = true;
0470     unsigned long flags;
0471     u32 geni_status;
0472     u32 irq_en;
0473 
0474     WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
0475 
0476     port = get_port_from_line(co->index, true);
0477     if (IS_ERR(port))
0478         return;
0479 
0480     uport = &port->uport;
0481     if (oops_in_progress)
0482         locked = spin_trylock_irqsave(&uport->lock, flags);
0483     else
0484         spin_lock_irqsave(&uport->lock, flags);
0485 
0486     geni_status = readl(uport->membase + SE_GENI_STATUS);
0487 
0488     /* Cancel the current write to log the fault */
0489     if (!locked) {
0490         geni_se_cancel_m_cmd(&port->se);
0491         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0492                         M_CMD_CANCEL_EN, true)) {
0493             geni_se_abort_m_cmd(&port->se);
0494             qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0495                             M_CMD_ABORT_EN, true);
0496             writel(M_CMD_ABORT_EN, uport->membase +
0497                             SE_GENI_M_IRQ_CLEAR);
0498         }
0499         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
0500     } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
0501         /*
0502          * It seems we can't interrupt existing transfers if all data
0503          * has been sent, in which case we need to look for done first.
0504          */
0505         qcom_geni_serial_poll_tx_done(uport);
0506 
0507         if (!uart_circ_empty(&uport->state->xmit)) {
0508             irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0509             writel(irq_en | M_TX_FIFO_WATERMARK_EN,
0510                     uport->membase + SE_GENI_M_IRQ_EN);
0511         }
0512     }
0513 
0514     __qcom_geni_serial_console_write(uport, s, count);
0515 
0516     if (port->tx_remaining)
0517         qcom_geni_serial_setup_tx(uport, port->tx_remaining);
0518 
0519     if (locked)
0520         spin_unlock_irqrestore(&uport->lock, flags);
0521 }
0522 
0523 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
0524 {
0525     u32 i;
0526     unsigned char buf[sizeof(u32)];
0527     struct tty_port *tport;
0528     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0529 
0530     tport = &uport->state->port;
0531     for (i = 0; i < bytes; ) {
0532         int c;
0533         int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
0534 
0535         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
0536         i += chunk;
0537         if (drop)
0538             continue;
0539 
0540         for (c = 0; c < chunk; c++) {
0541             int sysrq;
0542 
0543             uport->icount.rx++;
0544             if (port->brk && buf[c] == 0) {
0545                 port->brk = false;
0546                 if (uart_handle_break(uport))
0547                     continue;
0548             }
0549 
0550             sysrq = uart_prepare_sysrq_char(uport, buf[c]);
0551 
0552             if (!sysrq)
0553                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
0554         }
0555     }
0556     if (!drop)
0557         tty_flip_buffer_push(tport);
0558     return 0;
0559 }
0560 #else
0561 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
0562 {
0563     return -EPERM;
0564 }
0565 
0566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
0567 
0568 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
0569 {
0570     struct tty_port *tport;
0571     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0572     u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
0573     u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
0574     int ret;
0575 
0576     tport = &uport->state->port;
0577     ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
0578     if (drop)
0579         return 0;
0580 
0581     ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
0582     if (ret != bytes) {
0583         dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
0584                 __func__, ret, bytes);
0585         WARN_ON_ONCE(1);
0586     }
0587     uport->icount.rx += ret;
0588     tty_flip_buffer_push(tport);
0589     return ret;
0590 }
0591 
0592 static void qcom_geni_serial_start_tx(struct uart_port *uport)
0593 {
0594     u32 irq_en;
0595     u32 status;
0596 
0597     status = readl(uport->membase + SE_GENI_STATUS);
0598     if (status & M_GENI_CMD_ACTIVE)
0599         return;
0600 
0601     if (!qcom_geni_serial_tx_empty(uport))
0602         return;
0603 
0604     irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0605     irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
0606 
0607     writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
0608     writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
0609 }
0610 
0611 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
0612 {
0613     u32 irq_en;
0614     u32 status;
0615     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0616 
0617     irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0618     irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
0619     writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
0620     writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
0621     status = readl(uport->membase + SE_GENI_STATUS);
0622     /* Possible stop tx is called multiple times. */
0623     if (!(status & M_GENI_CMD_ACTIVE))
0624         return;
0625 
0626     geni_se_cancel_m_cmd(&port->se);
0627     if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0628                         M_CMD_CANCEL_EN, true)) {
0629         geni_se_abort_m_cmd(&port->se);
0630         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
0631                         M_CMD_ABORT_EN, true);
0632         writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
0633     }
0634     writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
0635 }
0636 
0637 static void qcom_geni_serial_start_rx(struct uart_port *uport)
0638 {
0639     u32 irq_en;
0640     u32 status;
0641     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0642 
0643     status = readl(uport->membase + SE_GENI_STATUS);
0644     if (status & S_GENI_CMD_ACTIVE)
0645         qcom_geni_serial_stop_rx(uport);
0646 
0647     geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
0648 
0649     irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
0650     irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
0651     writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
0652 
0653     irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0654     irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
0655     writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
0656 }
0657 
0658 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
0659 {
0660     u32 irq_en;
0661     u32 status;
0662     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0663     u32 s_irq_status;
0664 
0665     irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
0666     irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
0667     writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
0668 
0669     irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0670     irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
0671     writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
0672 
0673     status = readl(uport->membase + SE_GENI_STATUS);
0674     /* Possible stop rx is called multiple times. */
0675     if (!(status & S_GENI_CMD_ACTIVE))
0676         return;
0677 
0678     geni_se_cancel_s_cmd(&port->se);
0679     qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
0680                     S_CMD_CANCEL_EN, true);
0681     /*
0682      * If timeout occurs secondary engine remains active
0683      * and Abort sequence is executed.
0684      */
0685     s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
0686     /* Flush the Rx buffer */
0687     if (s_irq_status & S_RX_FIFO_LAST_EN)
0688         qcom_geni_serial_handle_rx(uport, true);
0689     writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
0690 
0691     status = readl(uport->membase + SE_GENI_STATUS);
0692     if (status & S_GENI_CMD_ACTIVE)
0693         qcom_geni_serial_abort_rx(uport);
0694 }
0695 
0696 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
0697 {
0698     u32 status;
0699     u32 word_cnt;
0700     u32 last_word_byte_cnt;
0701     u32 last_word_partial;
0702     u32 total_bytes;
0703     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0704 
0705     status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
0706     word_cnt = status & RX_FIFO_WC_MSK;
0707     last_word_partial = status & RX_LAST;
0708     last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
0709                         RX_LAST_BYTE_VALID_SHFT;
0710 
0711     if (!word_cnt)
0712         return;
0713     total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
0714     if (last_word_partial && last_word_byte_cnt)
0715         total_bytes += last_word_byte_cnt;
0716     else
0717         total_bytes += BYTES_PER_FIFO_WORD;
0718     port->handle_rx(uport, total_bytes, drop);
0719 }
0720 
0721 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
0722         bool active)
0723 {
0724     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0725     struct circ_buf *xmit = &uport->state->xmit;
0726     size_t avail;
0727     size_t remaining;
0728     size_t pending;
0729     int i;
0730     u32 status;
0731     u32 irq_en;
0732     unsigned int chunk;
0733     int tail;
0734 
0735     status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
0736 
0737     /* Complete the current tx command before taking newly added data */
0738     if (active)
0739         pending = port->tx_remaining;
0740     else
0741         pending = uart_circ_chars_pending(xmit);
0742 
0743     /* All data has been transmitted and acknowledged as received */
0744     if (!pending && !status && done) {
0745         qcom_geni_serial_stop_tx(uport);
0746         goto out_write_wakeup;
0747     }
0748 
0749     avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
0750     avail *= BYTES_PER_FIFO_WORD;
0751 
0752     tail = xmit->tail;
0753     chunk = min(avail, pending);
0754     if (!chunk)
0755         goto out_write_wakeup;
0756 
0757     if (!port->tx_remaining) {
0758         qcom_geni_serial_setup_tx(uport, pending);
0759         port->tx_remaining = pending;
0760 
0761         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0762         if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
0763             writel(irq_en | M_TX_FIFO_WATERMARK_EN,
0764                     uport->membase + SE_GENI_M_IRQ_EN);
0765     }
0766 
0767     remaining = chunk;
0768     for (i = 0; i < chunk; ) {
0769         unsigned int tx_bytes;
0770         u8 buf[sizeof(u32)];
0771         int c;
0772 
0773         memset(buf, 0, sizeof(buf));
0774         tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
0775 
0776         for (c = 0; c < tx_bytes ; c++) {
0777             buf[c] = xmit->buf[tail++];
0778             tail &= UART_XMIT_SIZE - 1;
0779         }
0780 
0781         iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
0782 
0783         i += tx_bytes;
0784         uport->icount.tx += tx_bytes;
0785         remaining -= tx_bytes;
0786         port->tx_remaining -= tx_bytes;
0787     }
0788 
0789     xmit->tail = tail;
0790 
0791     /*
0792      * The tx fifo watermark is level triggered and latched. Though we had
0793      * cleared it in qcom_geni_serial_isr it will have already reasserted
0794      * so we must clear it again here after our writes.
0795      */
0796     writel(M_TX_FIFO_WATERMARK_EN,
0797             uport->membase + SE_GENI_M_IRQ_CLEAR);
0798 
0799 out_write_wakeup:
0800     if (!port->tx_remaining) {
0801         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0802         if (irq_en & M_TX_FIFO_WATERMARK_EN)
0803             writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
0804                     uport->membase + SE_GENI_M_IRQ_EN);
0805     }
0806 
0807     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0808         uart_write_wakeup(uport);
0809 }
0810 
0811 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
0812 {
0813     u32 m_irq_en;
0814     u32 m_irq_status;
0815     u32 s_irq_status;
0816     u32 geni_status;
0817     struct uart_port *uport = dev;
0818     bool drop_rx = false;
0819     struct tty_port *tport = &uport->state->port;
0820     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0821 
0822     if (uport->suspended)
0823         return IRQ_NONE;
0824 
0825     spin_lock(&uport->lock);
0826 
0827     m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
0828     s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
0829     geni_status = readl(uport->membase + SE_GENI_STATUS);
0830     m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
0831     writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
0832     writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
0833 
0834     if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
0835         goto out_unlock;
0836 
0837     if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
0838         uport->icount.overrun++;
0839         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0840     }
0841 
0842     if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
0843         qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
0844                     geni_status & M_GENI_CMD_ACTIVE);
0845 
0846     if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
0847         if (s_irq_status & S_GP_IRQ_0_EN)
0848             uport->icount.parity++;
0849         drop_rx = true;
0850     } else if (s_irq_status & S_GP_IRQ_2_EN ||
0851                     s_irq_status & S_GP_IRQ_3_EN) {
0852         uport->icount.brk++;
0853         port->brk = true;
0854     }
0855 
0856     if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
0857                     s_irq_status & S_RX_FIFO_LAST_EN)
0858         qcom_geni_serial_handle_rx(uport, drop_rx);
0859 
0860 out_unlock:
0861     uart_unlock_and_check_sysrq(uport);
0862 
0863     return IRQ_HANDLED;
0864 }
0865 
0866 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
0867 {
0868     struct uart_port *uport;
0869 
0870     uport = &port->uport;
0871     port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
0872     port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
0873     port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
0874     uport->fifosize =
0875         (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
0876 }
0877 
0878 
0879 static void qcom_geni_serial_shutdown(struct uart_port *uport)
0880 {
0881     disable_irq(uport->irq);
0882 }
0883 
0884 static int qcom_geni_serial_port_setup(struct uart_port *uport)
0885 {
0886     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0887     u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
0888     u32 proto;
0889     u32 pin_swap;
0890 
0891     proto = geni_se_read_proto(&port->se);
0892     if (proto != GENI_SE_UART) {
0893         dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
0894         return -ENXIO;
0895     }
0896 
0897     qcom_geni_serial_stop_rx(uport);
0898 
0899     get_tx_fifo_size(port);
0900 
0901     writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
0902 
0903     pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
0904     if (port->rx_tx_swap) {
0905         pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
0906         pin_swap |= IO_MACRO_IO2_IO3_SWAP;
0907     }
0908     if (port->cts_rts_swap) {
0909         pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
0910         pin_swap |= IO_MACRO_IO0_SEL;
0911     }
0912     /* Configure this register if RX-TX, CTS-RTS pins are swapped */
0913     if (port->rx_tx_swap || port->cts_rts_swap)
0914         writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
0915 
0916     /*
0917      * Make an unconditional cancel on the main sequencer to reset
0918      * it else we could end up in data loss scenarios.
0919      */
0920     if (uart_console(uport))
0921         qcom_geni_serial_poll_tx_done(uport);
0922     geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
0923                    false, true, true);
0924     geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
0925     geni_se_select_mode(&port->se, GENI_SE_FIFO);
0926     port->setup = true;
0927 
0928     return 0;
0929 }
0930 
0931 static int qcom_geni_serial_startup(struct uart_port *uport)
0932 {
0933     int ret;
0934     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
0935 
0936     if (!port->setup) {
0937         ret = qcom_geni_serial_port_setup(uport);
0938         if (ret)
0939             return ret;
0940     }
0941     enable_irq(uport->irq);
0942 
0943     return 0;
0944 }
0945 
0946 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
0947             unsigned int *clk_div, unsigned int percent_tol)
0948 {
0949     unsigned long freq;
0950     unsigned long div, maxdiv;
0951     u64 mult;
0952     unsigned long offset, abs_tol, achieved;
0953 
0954     abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
0955     maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
0956     div = 1;
0957     while (div <= maxdiv) {
0958         mult = (u64)div * desired_clk;
0959         if (mult != (unsigned long)mult)
0960             break;
0961 
0962         offset = div * abs_tol;
0963         freq = clk_round_rate(clk, mult - offset);
0964 
0965         /* Can only get lower if we're done */
0966         if (freq < mult - offset)
0967             break;
0968 
0969         /*
0970          * Re-calculate div in case rounding skipped rates but we
0971          * ended up at a good one, then check for a match.
0972          */
0973         div = DIV_ROUND_CLOSEST(freq, desired_clk);
0974         achieved = DIV_ROUND_CLOSEST(freq, div);
0975         if (achieved <= desired_clk + abs_tol &&
0976             achieved >= desired_clk - abs_tol) {
0977             *clk_div = div;
0978             return freq;
0979         }
0980 
0981         div = DIV_ROUND_UP(freq, desired_clk);
0982     }
0983 
0984     return 0;
0985 }
0986 
0987 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
0988             unsigned int sampling_rate, unsigned int *clk_div)
0989 {
0990     unsigned long ser_clk;
0991     unsigned long desired_clk;
0992 
0993     desired_clk = baud * sampling_rate;
0994     if (!desired_clk)
0995         return 0;
0996 
0997     /*
0998      * try to find a clock rate within 2% tolerance, then within 5%
0999      */
1000     ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1001     if (!ser_clk)
1002         ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1003 
1004     return ser_clk;
1005 }
1006 
1007 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1008                 struct ktermios *termios, struct ktermios *old)
1009 {
1010     unsigned int baud;
1011     u32 bits_per_char;
1012     u32 tx_trans_cfg;
1013     u32 tx_parity_cfg;
1014     u32 rx_trans_cfg;
1015     u32 rx_parity_cfg;
1016     u32 stop_bit_len;
1017     unsigned int clk_div;
1018     u32 ser_clk_cfg;
1019     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1020     unsigned long clk_rate;
1021     u32 ver, sampling_rate;
1022     unsigned int avg_bw_core;
1023 
1024     qcom_geni_serial_stop_rx(uport);
1025     /* baud rate */
1026     baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1027     port->baud = baud;
1028 
1029     sampling_rate = UART_OVERSAMPLING;
1030     /* Sampling rate is halved for IP versions >= 2.5 */
1031     ver = geni_se_get_qup_hw_version(&port->se);
1032     if (ver >= QUP_SE_VERSION_2_5)
1033         sampling_rate /= 2;
1034 
1035     clk_rate = get_clk_div_rate(port->se.clk, baud,
1036         sampling_rate, &clk_div);
1037     if (!clk_rate) {
1038         dev_err(port->se.dev,
1039             "Couldn't find suitable clock rate for %u\n",
1040             baud * sampling_rate);
1041         goto out_restart_rx;
1042     }
1043 
1044     dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
1045             baud * sampling_rate, clk_rate, clk_div);
1046 
1047     uport->uartclk = clk_rate;
1048     dev_pm_opp_set_rate(uport->dev, clk_rate);
1049     ser_clk_cfg = SER_CLK_EN;
1050     ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1051 
1052     /*
1053      * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1054      * only.
1055      */
1056     avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1057                         : GENI_DEFAULT_BW;
1058     port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1059     port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1060     geni_icc_set_bw(&port->se);
1061 
1062     /* parity */
1063     tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1064     tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1065     rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1066     rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1067     if (termios->c_cflag & PARENB) {
1068         tx_trans_cfg |= UART_TX_PAR_EN;
1069         rx_trans_cfg |= UART_RX_PAR_EN;
1070         tx_parity_cfg |= PAR_CALC_EN;
1071         rx_parity_cfg |= PAR_CALC_EN;
1072         if (termios->c_cflag & PARODD) {
1073             tx_parity_cfg |= PAR_ODD;
1074             rx_parity_cfg |= PAR_ODD;
1075         } else if (termios->c_cflag & CMSPAR) {
1076             tx_parity_cfg |= PAR_SPACE;
1077             rx_parity_cfg |= PAR_SPACE;
1078         } else {
1079             tx_parity_cfg |= PAR_EVEN;
1080             rx_parity_cfg |= PAR_EVEN;
1081         }
1082     } else {
1083         tx_trans_cfg &= ~UART_TX_PAR_EN;
1084         rx_trans_cfg &= ~UART_RX_PAR_EN;
1085         tx_parity_cfg &= ~PAR_CALC_EN;
1086         rx_parity_cfg &= ~PAR_CALC_EN;
1087     }
1088 
1089     /* bits per char */
1090     bits_per_char = tty_get_char_size(termios->c_cflag);
1091 
1092     /* stop bits */
1093     if (termios->c_cflag & CSTOPB)
1094         stop_bit_len = TX_STOP_BIT_LEN_2;
1095     else
1096         stop_bit_len = TX_STOP_BIT_LEN_1;
1097 
1098     /* flow control, clear the CTS_MASK bit if using flow control. */
1099     if (termios->c_cflag & CRTSCTS)
1100         tx_trans_cfg &= ~UART_CTS_MASK;
1101     else
1102         tx_trans_cfg |= UART_CTS_MASK;
1103 
1104     if (baud)
1105         uart_update_timeout(uport, termios->c_cflag, baud);
1106 
1107     if (!uart_console(uport))
1108         writel(port->loopback,
1109                 uport->membase + SE_UART_LOOPBACK_CFG);
1110     writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1111     writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1112     writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1113     writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1114     writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1115     writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1116     writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1117     writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1118     writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1119 out_restart_rx:
1120     qcom_geni_serial_start_rx(uport);
1121 }
1122 
1123 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1124 {
1125     return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1126 }
1127 
1128 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1129 static int qcom_geni_console_setup(struct console *co, char *options)
1130 {
1131     struct uart_port *uport;
1132     struct qcom_geni_serial_port *port;
1133     int baud = 115200;
1134     int bits = 8;
1135     int parity = 'n';
1136     int flow = 'n';
1137     int ret;
1138 
1139     if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1140         return -ENXIO;
1141 
1142     port = get_port_from_line(co->index, true);
1143     if (IS_ERR(port)) {
1144         pr_err("Invalid line %d\n", co->index);
1145         return PTR_ERR(port);
1146     }
1147 
1148     uport = &port->uport;
1149 
1150     if (unlikely(!uport->membase))
1151         return -ENXIO;
1152 
1153     if (!port->setup) {
1154         ret = qcom_geni_serial_port_setup(uport);
1155         if (ret)
1156             return ret;
1157     }
1158 
1159     if (options)
1160         uart_parse_options(options, &baud, &parity, &bits, &flow);
1161 
1162     return uart_set_options(uport, co, baud, parity, bits, flow);
1163 }
1164 
1165 static void qcom_geni_serial_earlycon_write(struct console *con,
1166                     const char *s, unsigned int n)
1167 {
1168     struct earlycon_device *dev = con->data;
1169 
1170     __qcom_geni_serial_console_write(&dev->port, s, n);
1171 }
1172 
1173 #ifdef CONFIG_CONSOLE_POLL
1174 static int qcom_geni_serial_earlycon_read(struct console *con,
1175                       char *s, unsigned int n)
1176 {
1177     struct earlycon_device *dev = con->data;
1178     struct uart_port *uport = &dev->port;
1179     int num_read = 0;
1180     int ch;
1181 
1182     while (num_read < n) {
1183         ch = qcom_geni_serial_get_char(uport);
1184         if (ch == NO_POLL_CHAR)
1185             break;
1186         s[num_read++] = ch;
1187     }
1188 
1189     return num_read;
1190 }
1191 
1192 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1193                               struct console *con)
1194 {
1195     geni_se_setup_s_cmd(se, UART_START_READ, 0);
1196     con->read = qcom_geni_serial_earlycon_read;
1197 }
1198 #else
1199 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1200                               struct console *con) { }
1201 #endif
1202 
1203 static struct qcom_geni_private_data earlycon_private_data;
1204 
1205 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1206                                 const char *opt)
1207 {
1208     struct uart_port *uport = &dev->port;
1209     u32 tx_trans_cfg;
1210     u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1211     u32 rx_trans_cfg = 0;
1212     u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1213     u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1214     u32 bits_per_char;
1215     struct geni_se se;
1216 
1217     if (!uport->membase)
1218         return -EINVAL;
1219 
1220     uport->private_data = &earlycon_private_data;
1221 
1222     memset(&se, 0, sizeof(se));
1223     se.base = uport->membase;
1224     if (geni_se_read_proto(&se) != GENI_SE_UART)
1225         return -ENXIO;
1226     /*
1227      * Ignore Flow control.
1228      * n = 8.
1229      */
1230     tx_trans_cfg = UART_CTS_MASK;
1231     bits_per_char = BITS_PER_BYTE;
1232 
1233     /*
1234      * Make an unconditional cancel on the main sequencer to reset
1235      * it else we could end up in data loss scenarios.
1236      */
1237     qcom_geni_serial_poll_tx_done(uport);
1238     qcom_geni_serial_abort_rx(uport);
1239     geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1240                    false, true, true);
1241     geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1242     geni_se_select_mode(&se, GENI_SE_FIFO);
1243 
1244     writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1245     writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1246     writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1247     writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1248     writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1249     writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1250     writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1251 
1252     dev->con->write = qcom_geni_serial_earlycon_write;
1253     dev->con->setup = NULL;
1254     qcom_geni_serial_enable_early_read(&se, dev->con);
1255 
1256     return 0;
1257 }
1258 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1259                 qcom_geni_serial_earlycon_setup);
1260 
1261 static int __init console_register(struct uart_driver *drv)
1262 {
1263     return uart_register_driver(drv);
1264 }
1265 
1266 static void console_unregister(struct uart_driver *drv)
1267 {
1268     uart_unregister_driver(drv);
1269 }
1270 
1271 static struct console cons_ops = {
1272     .name = "ttyMSM",
1273     .write = qcom_geni_serial_console_write,
1274     .device = uart_console_device,
1275     .setup = qcom_geni_console_setup,
1276     .flags = CON_PRINTBUFFER,
1277     .index = -1,
1278     .data = &qcom_geni_console_driver,
1279 };
1280 
1281 static struct uart_driver qcom_geni_console_driver = {
1282     .owner = THIS_MODULE,
1283     .driver_name = "qcom_geni_console",
1284     .dev_name = "ttyMSM",
1285     .nr =  GENI_UART_CONS_PORTS,
1286     .cons = &cons_ops,
1287 };
1288 #else
1289 static int console_register(struct uart_driver *drv)
1290 {
1291     return 0;
1292 }
1293 
1294 static void console_unregister(struct uart_driver *drv)
1295 {
1296 }
1297 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1298 
1299 static struct uart_driver qcom_geni_uart_driver = {
1300     .owner = THIS_MODULE,
1301     .driver_name = "qcom_geni_uart",
1302     .dev_name = "ttyHS",
1303     .nr =  GENI_UART_PORTS,
1304 };
1305 
1306 static void qcom_geni_serial_pm(struct uart_port *uport,
1307         unsigned int new_state, unsigned int old_state)
1308 {
1309     struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1310 
1311     /* If we've never been called, treat it as off */
1312     if (old_state == UART_PM_STATE_UNDEFINED)
1313         old_state = UART_PM_STATE_OFF;
1314 
1315     if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1316         geni_icc_enable(&port->se);
1317         geni_se_resources_on(&port->se);
1318     } else if (new_state == UART_PM_STATE_OFF &&
1319             old_state == UART_PM_STATE_ON) {
1320         geni_se_resources_off(&port->se);
1321         geni_icc_disable(&port->se);
1322     }
1323 }
1324 
1325 static const struct uart_ops qcom_geni_console_pops = {
1326     .tx_empty = qcom_geni_serial_tx_empty,
1327     .stop_tx = qcom_geni_serial_stop_tx,
1328     .start_tx = qcom_geni_serial_start_tx,
1329     .stop_rx = qcom_geni_serial_stop_rx,
1330     .start_rx = qcom_geni_serial_start_rx,
1331     .set_termios = qcom_geni_serial_set_termios,
1332     .startup = qcom_geni_serial_startup,
1333     .request_port = qcom_geni_serial_request_port,
1334     .config_port = qcom_geni_serial_config_port,
1335     .shutdown = qcom_geni_serial_shutdown,
1336     .type = qcom_geni_serial_get_type,
1337     .set_mctrl = qcom_geni_serial_set_mctrl,
1338     .get_mctrl = qcom_geni_serial_get_mctrl,
1339 #ifdef CONFIG_CONSOLE_POLL
1340     .poll_get_char  = qcom_geni_serial_get_char,
1341     .poll_put_char  = qcom_geni_serial_poll_put_char,
1342 #endif
1343     .pm = qcom_geni_serial_pm,
1344 };
1345 
1346 static const struct uart_ops qcom_geni_uart_pops = {
1347     .tx_empty = qcom_geni_serial_tx_empty,
1348     .stop_tx = qcom_geni_serial_stop_tx,
1349     .start_tx = qcom_geni_serial_start_tx,
1350     .stop_rx = qcom_geni_serial_stop_rx,
1351     .set_termios = qcom_geni_serial_set_termios,
1352     .startup = qcom_geni_serial_startup,
1353     .request_port = qcom_geni_serial_request_port,
1354     .config_port = qcom_geni_serial_config_port,
1355     .shutdown = qcom_geni_serial_shutdown,
1356     .type = qcom_geni_serial_get_type,
1357     .set_mctrl = qcom_geni_serial_set_mctrl,
1358     .get_mctrl = qcom_geni_serial_get_mctrl,
1359     .pm = qcom_geni_serial_pm,
1360 };
1361 
1362 static int qcom_geni_serial_probe(struct platform_device *pdev)
1363 {
1364     int ret = 0;
1365     int line;
1366     struct qcom_geni_serial_port *port;
1367     struct uart_port *uport;
1368     struct resource *res;
1369     int irq;
1370     bool console = false;
1371     struct uart_driver *drv;
1372 
1373     if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1374         console = true;
1375 
1376     if (console) {
1377         drv = &qcom_geni_console_driver;
1378         line = of_alias_get_id(pdev->dev.of_node, "serial");
1379     } else {
1380         drv = &qcom_geni_uart_driver;
1381         line = of_alias_get_id(pdev->dev.of_node, "serial");
1382         if (line == -ENODEV) /* compat with non-standard aliases */
1383             line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1384     }
1385 
1386     port = get_port_from_line(line, console);
1387     if (IS_ERR(port)) {
1388         dev_err(&pdev->dev, "Invalid line %d\n", line);
1389         return PTR_ERR(port);
1390     }
1391 
1392     uport = &port->uport;
1393     /* Don't allow 2 drivers to access the same port */
1394     if (uport->private_data)
1395         return -ENODEV;
1396 
1397     uport->dev = &pdev->dev;
1398     port->se.dev = &pdev->dev;
1399     port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1400     port->se.clk = devm_clk_get(&pdev->dev, "se");
1401     if (IS_ERR(port->se.clk)) {
1402         ret = PTR_ERR(port->se.clk);
1403         dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1404         return ret;
1405     }
1406 
1407     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1408     if (!res)
1409         return -EINVAL;
1410     uport->mapbase = res->start;
1411 
1412     port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1413     port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1414     port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1415 
1416     if (!console) {
1417         port->rx_fifo = devm_kcalloc(uport->dev,
1418             port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1419         if (!port->rx_fifo)
1420             return -ENOMEM;
1421     }
1422 
1423     ret = geni_icc_get(&port->se, NULL);
1424     if (ret)
1425         return ret;
1426     port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1427     port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1428 
1429     /* Set BW for register access */
1430     ret = geni_icc_set_bw(&port->se);
1431     if (ret)
1432         return ret;
1433 
1434     port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1435             "qcom_geni_serial_%s%d",
1436             uart_console(uport) ? "console" : "uart", uport->line);
1437     if (!port->name)
1438         return -ENOMEM;
1439 
1440     irq = platform_get_irq(pdev, 0);
1441     if (irq < 0)
1442         return irq;
1443     uport->irq = irq;
1444     uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1445 
1446     if (!console)
1447         port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1448 
1449     if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1450         port->rx_tx_swap = true;
1451 
1452     if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1453         port->cts_rts_swap = true;
1454 
1455     ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1456     if (ret)
1457         return ret;
1458     /* OPP table is optional */
1459     ret = devm_pm_opp_of_add_table(&pdev->dev);
1460     if (ret && ret != -ENODEV) {
1461         dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1462         return ret;
1463     }
1464 
1465     port->private_data.drv = drv;
1466     uport->private_data = &port->private_data;
1467     platform_set_drvdata(pdev, port);
1468     port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1469 
1470     ret = uart_add_one_port(drv, uport);
1471     if (ret)
1472         return ret;
1473 
1474     irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1475     ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1476             IRQF_TRIGGER_HIGH, port->name, uport);
1477     if (ret) {
1478         dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1479         uart_remove_one_port(drv, uport);
1480         return ret;
1481     }
1482 
1483     /*
1484      * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1485      * enabled/disabled from dev_pm_arm_wake_irq during system
1486      * suspend/resume respectively.
1487      */
1488     pm_runtime_set_active(&pdev->dev);
1489 
1490     if (port->wakeup_irq > 0) {
1491         device_init_wakeup(&pdev->dev, true);
1492         ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1493                         port->wakeup_irq);
1494         if (ret) {
1495             device_init_wakeup(&pdev->dev, false);
1496             uart_remove_one_port(drv, uport);
1497             return ret;
1498         }
1499     }
1500 
1501     return 0;
1502 }
1503 
1504 static int qcom_geni_serial_remove(struct platform_device *pdev)
1505 {
1506     struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1507     struct uart_driver *drv = port->private_data.drv;
1508 
1509     dev_pm_clear_wake_irq(&pdev->dev);
1510     device_init_wakeup(&pdev->dev, false);
1511     uart_remove_one_port(drv, &port->uport);
1512 
1513     return 0;
1514 }
1515 
1516 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1517 {
1518     struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1519     struct uart_port *uport = &port->uport;
1520     struct qcom_geni_private_data *private_data = uport->private_data;
1521 
1522     /*
1523      * This is done so we can hit the lowest possible state in suspend
1524      * even with no_console_suspend
1525      */
1526     if (uart_console(uport)) {
1527         geni_icc_set_tag(&port->se, 0x3);
1528         geni_icc_set_bw(&port->se);
1529     }
1530     return uart_suspend_port(private_data->drv, uport);
1531 }
1532 
1533 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1534 {
1535     int ret;
1536     struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1537     struct uart_port *uport = &port->uport;
1538     struct qcom_geni_private_data *private_data = uport->private_data;
1539 
1540     ret = uart_resume_port(private_data->drv, uport);
1541     if (uart_console(uport)) {
1542         geni_icc_set_tag(&port->se, 0x7);
1543         geni_icc_set_bw(&port->se);
1544     }
1545     return ret;
1546 }
1547 
1548 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1549     SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1550                     qcom_geni_serial_sys_resume)
1551 };
1552 
1553 static const struct of_device_id qcom_geni_serial_match_table[] = {
1554     { .compatible = "qcom,geni-debug-uart", },
1555     { .compatible = "qcom,geni-uart", },
1556     {}
1557 };
1558 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1559 
1560 static struct platform_driver qcom_geni_serial_platform_driver = {
1561     .remove = qcom_geni_serial_remove,
1562     .probe = qcom_geni_serial_probe,
1563     .driver = {
1564         .name = "qcom_geni_serial",
1565         .of_match_table = qcom_geni_serial_match_table,
1566         .pm = &qcom_geni_serial_pm_ops,
1567     },
1568 };
1569 
1570 static int __init qcom_geni_serial_init(void)
1571 {
1572     int ret;
1573 
1574     ret = console_register(&qcom_geni_console_driver);
1575     if (ret)
1576         return ret;
1577 
1578     ret = uart_register_driver(&qcom_geni_uart_driver);
1579     if (ret) {
1580         console_unregister(&qcom_geni_console_driver);
1581         return ret;
1582     }
1583 
1584     ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1585     if (ret) {
1586         console_unregister(&qcom_geni_console_driver);
1587         uart_unregister_driver(&qcom_geni_uart_driver);
1588     }
1589     return ret;
1590 }
1591 module_init(qcom_geni_serial_init);
1592 
1593 static void __exit qcom_geni_serial_exit(void)
1594 {
1595     platform_driver_unregister(&qcom_geni_serial_platform_driver);
1596     console_unregister(&qcom_geni_console_driver);
1597     uart_unregister_driver(&qcom_geni_uart_driver);
1598 }
1599 module_exit(qcom_geni_serial_exit);
1600 
1601 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1602 MODULE_LICENSE("GPL v2");
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