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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Based on drivers/serial/8250.c by Russell King.
0004  *
0005  *  Author: Nicolas Pitre
0006  *  Created:    Feb 20, 2003
0007  *  Copyright:  (C) 2003 Monta Vista Software, Inc.
0008  *
0009  * Note 1: This driver is made separate from the already too overloaded
0010  * 8250.c because it needs some kirks of its own and that'll make it
0011  * easier to add DMA support.
0012  *
0013  * Note 2: I'm too sick of device allocation policies for serial ports.
0014  * If someone else wants to request an "official" allocation of major/minor
0015  * for this driver please be my guest.  And don't forget that new hardware
0016  * to come from Intel might have more than 3 or 4 of those UARTs.  Let's
0017  * hope for a better port registration and dynamic device allocation scheme
0018  * with the serial core maintainer satisfaction to appear soon.
0019  */
0020 
0021 
0022 #include <linux/ioport.h>
0023 #include <linux/init.h>
0024 #include <linux/console.h>
0025 #include <linux/sysrq.h>
0026 #include <linux/serial.h>
0027 #include <linux/serial_reg.h>
0028 #include <linux/circ_buf.h>
0029 #include <linux/delay.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/of.h>
0032 #include <linux/platform_device.h>
0033 #include <linux/tty.h>
0034 #include <linux/tty_flip.h>
0035 #include <linux/serial_core.h>
0036 #include <linux/clk.h>
0037 #include <linux/io.h>
0038 #include <linux/slab.h>
0039 
0040 #define PXA_NAME_LEN        8
0041 
0042 struct uart_pxa_port {
0043     struct uart_port        port;
0044     unsigned char           ier;
0045     unsigned char           lcr;
0046     unsigned char           mcr;
0047     unsigned int            lsr_break_flag;
0048     struct clk      *clk;
0049     char            name[PXA_NAME_LEN];
0050 };
0051 
0052 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
0053 {
0054     offset <<= 2;
0055     return readl(up->port.membase + offset);
0056 }
0057 
0058 static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
0059 {
0060     offset <<= 2;
0061     writel(value, up->port.membase + offset);
0062 }
0063 
0064 static void serial_pxa_enable_ms(struct uart_port *port)
0065 {
0066     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0067 
0068     up->ier |= UART_IER_MSI;
0069     serial_out(up, UART_IER, up->ier);
0070 }
0071 
0072 static void serial_pxa_stop_tx(struct uart_port *port)
0073 {
0074     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0075 
0076     if (up->ier & UART_IER_THRI) {
0077         up->ier &= ~UART_IER_THRI;
0078         serial_out(up, UART_IER, up->ier);
0079     }
0080 }
0081 
0082 static void serial_pxa_stop_rx(struct uart_port *port)
0083 {
0084     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0085 
0086     up->ier &= ~UART_IER_RLSI;
0087     up->port.read_status_mask &= ~UART_LSR_DR;
0088     serial_out(up, UART_IER, up->ier);
0089 }
0090 
0091 static inline void receive_chars(struct uart_pxa_port *up, int *status)
0092 {
0093     unsigned int ch, flag;
0094     int max_count = 256;
0095 
0096     do {
0097         /* work around Errata #20 according to
0098          * Intel(R) PXA27x Processor Family
0099          * Specification Update (May 2005)
0100          *
0101          * Step 2
0102          * Disable the Reciever Time Out Interrupt via IER[RTOEI]
0103          */
0104         up->ier &= ~UART_IER_RTOIE;
0105         serial_out(up, UART_IER, up->ier);
0106 
0107         ch = serial_in(up, UART_RX);
0108         flag = TTY_NORMAL;
0109         up->port.icount.rx++;
0110 
0111         if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
0112                        UART_LSR_FE | UART_LSR_OE))) {
0113             /*
0114              * For statistics only
0115              */
0116             if (*status & UART_LSR_BI) {
0117                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
0118                 up->port.icount.brk++;
0119                 /*
0120                  * We do the SysRQ and SAK checking
0121                  * here because otherwise the break
0122                  * may get masked by ignore_status_mask
0123                  * or read_status_mask.
0124                  */
0125                 if (uart_handle_break(&up->port))
0126                     goto ignore_char;
0127             } else if (*status & UART_LSR_PE)
0128                 up->port.icount.parity++;
0129             else if (*status & UART_LSR_FE)
0130                 up->port.icount.frame++;
0131             if (*status & UART_LSR_OE)
0132                 up->port.icount.overrun++;
0133 
0134             /*
0135              * Mask off conditions which should be ignored.
0136              */
0137             *status &= up->port.read_status_mask;
0138 
0139 #ifdef CONFIG_SERIAL_PXA_CONSOLE
0140             if (up->port.line == up->port.cons->index) {
0141                 /* Recover the break flag from console xmit */
0142                 *status |= up->lsr_break_flag;
0143                 up->lsr_break_flag = 0;
0144             }
0145 #endif
0146             if (*status & UART_LSR_BI) {
0147                 flag = TTY_BREAK;
0148             } else if (*status & UART_LSR_PE)
0149                 flag = TTY_PARITY;
0150             else if (*status & UART_LSR_FE)
0151                 flag = TTY_FRAME;
0152         }
0153 
0154         if (uart_handle_sysrq_char(&up->port, ch))
0155             goto ignore_char;
0156 
0157         uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
0158 
0159     ignore_char:
0160         *status = serial_in(up, UART_LSR);
0161     } while ((*status & UART_LSR_DR) && (max_count-- > 0));
0162     tty_flip_buffer_push(&up->port.state->port);
0163 
0164     /* work around Errata #20 according to
0165      * Intel(R) PXA27x Processor Family
0166      * Specification Update (May 2005)
0167      *
0168      * Step 6:
0169      * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
0170      */
0171     up->ier |= UART_IER_RTOIE;
0172     serial_out(up, UART_IER, up->ier);
0173 }
0174 
0175 static void transmit_chars(struct uart_pxa_port *up)
0176 {
0177     struct circ_buf *xmit = &up->port.state->xmit;
0178     int count;
0179 
0180     if (up->port.x_char) {
0181         serial_out(up, UART_TX, up->port.x_char);
0182         up->port.icount.tx++;
0183         up->port.x_char = 0;
0184         return;
0185     }
0186     if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
0187         serial_pxa_stop_tx(&up->port);
0188         return;
0189     }
0190 
0191     count = up->port.fifosize / 2;
0192     do {
0193         serial_out(up, UART_TX, xmit->buf[xmit->tail]);
0194         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0195         up->port.icount.tx++;
0196         if (uart_circ_empty(xmit))
0197             break;
0198     } while (--count > 0);
0199 
0200     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0201         uart_write_wakeup(&up->port);
0202 
0203 
0204     if (uart_circ_empty(xmit))
0205         serial_pxa_stop_tx(&up->port);
0206 }
0207 
0208 static void serial_pxa_start_tx(struct uart_port *port)
0209 {
0210     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0211 
0212     if (!(up->ier & UART_IER_THRI)) {
0213         up->ier |= UART_IER_THRI;
0214         serial_out(up, UART_IER, up->ier);
0215     }
0216 }
0217 
0218 /* should hold up->port.lock */
0219 static inline void check_modem_status(struct uart_pxa_port *up)
0220 {
0221     int status;
0222 
0223     status = serial_in(up, UART_MSR);
0224 
0225     if ((status & UART_MSR_ANY_DELTA) == 0)
0226         return;
0227 
0228     if (status & UART_MSR_TERI)
0229         up->port.icount.rng++;
0230     if (status & UART_MSR_DDSR)
0231         up->port.icount.dsr++;
0232     if (status & UART_MSR_DDCD)
0233         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
0234     if (status & UART_MSR_DCTS)
0235         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
0236 
0237     wake_up_interruptible(&up->port.state->port.delta_msr_wait);
0238 }
0239 
0240 /*
0241  * This handles the interrupt from one port.
0242  */
0243 static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
0244 {
0245     struct uart_pxa_port *up = dev_id;
0246     unsigned int iir, lsr;
0247 
0248     iir = serial_in(up, UART_IIR);
0249     if (iir & UART_IIR_NO_INT)
0250         return IRQ_NONE;
0251     spin_lock(&up->port.lock);
0252     lsr = serial_in(up, UART_LSR);
0253     if (lsr & UART_LSR_DR)
0254         receive_chars(up, &lsr);
0255     check_modem_status(up);
0256     if (lsr & UART_LSR_THRE)
0257         transmit_chars(up);
0258     spin_unlock(&up->port.lock);
0259     return IRQ_HANDLED;
0260 }
0261 
0262 static unsigned int serial_pxa_tx_empty(struct uart_port *port)
0263 {
0264     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0265     unsigned long flags;
0266     unsigned int ret;
0267 
0268     spin_lock_irqsave(&up->port.lock, flags);
0269     ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
0270     spin_unlock_irqrestore(&up->port.lock, flags);
0271 
0272     return ret;
0273 }
0274 
0275 static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
0276 {
0277     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0278     unsigned char status;
0279     unsigned int ret;
0280 
0281     status = serial_in(up, UART_MSR);
0282 
0283     ret = 0;
0284     if (status & UART_MSR_DCD)
0285         ret |= TIOCM_CAR;
0286     if (status & UART_MSR_RI)
0287         ret |= TIOCM_RNG;
0288     if (status & UART_MSR_DSR)
0289         ret |= TIOCM_DSR;
0290     if (status & UART_MSR_CTS)
0291         ret |= TIOCM_CTS;
0292     return ret;
0293 }
0294 
0295 static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
0296 {
0297     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0298     unsigned char mcr = 0;
0299 
0300     if (mctrl & TIOCM_RTS)
0301         mcr |= UART_MCR_RTS;
0302     if (mctrl & TIOCM_DTR)
0303         mcr |= UART_MCR_DTR;
0304     if (mctrl & TIOCM_OUT1)
0305         mcr |= UART_MCR_OUT1;
0306     if (mctrl & TIOCM_OUT2)
0307         mcr |= UART_MCR_OUT2;
0308     if (mctrl & TIOCM_LOOP)
0309         mcr |= UART_MCR_LOOP;
0310 
0311     mcr |= up->mcr;
0312 
0313     serial_out(up, UART_MCR, mcr);
0314 }
0315 
0316 static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
0317 {
0318     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0319     unsigned long flags;
0320 
0321     spin_lock_irqsave(&up->port.lock, flags);
0322     if (break_state == -1)
0323         up->lcr |= UART_LCR_SBC;
0324     else
0325         up->lcr &= ~UART_LCR_SBC;
0326     serial_out(up, UART_LCR, up->lcr);
0327     spin_unlock_irqrestore(&up->port.lock, flags);
0328 }
0329 
0330 static int serial_pxa_startup(struct uart_port *port)
0331 {
0332     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0333     unsigned long flags;
0334     int retval;
0335 
0336     if (port->line == 3) /* HWUART */
0337         up->mcr |= UART_MCR_AFE;
0338     else
0339         up->mcr = 0;
0340 
0341     up->port.uartclk = clk_get_rate(up->clk);
0342 
0343     /*
0344      * Allocate the IRQ
0345      */
0346     retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
0347     if (retval)
0348         return retval;
0349 
0350     /*
0351      * Clear the FIFO buffers and disable them.
0352      * (they will be reenabled in set_termios())
0353      */
0354     serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
0355     serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
0356             UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0357     serial_out(up, UART_FCR, 0);
0358 
0359     /*
0360      * Clear the interrupt registers.
0361      */
0362     (void) serial_in(up, UART_LSR);
0363     (void) serial_in(up, UART_RX);
0364     (void) serial_in(up, UART_IIR);
0365     (void) serial_in(up, UART_MSR);
0366 
0367     /*
0368      * Now, initialize the UART
0369      */
0370     serial_out(up, UART_LCR, UART_LCR_WLEN8);
0371 
0372     spin_lock_irqsave(&up->port.lock, flags);
0373     up->port.mctrl |= TIOCM_OUT2;
0374     serial_pxa_set_mctrl(&up->port, up->port.mctrl);
0375     spin_unlock_irqrestore(&up->port.lock, flags);
0376 
0377     /*
0378      * Finally, enable interrupts.  Note: Modem status interrupts
0379      * are set via set_termios(), which will be occurring imminently
0380      * anyway, so we don't enable them here.
0381      */
0382     up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
0383     serial_out(up, UART_IER, up->ier);
0384 
0385     /*
0386      * And clear the interrupt registers again for luck.
0387      */
0388     (void) serial_in(up, UART_LSR);
0389     (void) serial_in(up, UART_RX);
0390     (void) serial_in(up, UART_IIR);
0391     (void) serial_in(up, UART_MSR);
0392 
0393     return 0;
0394 }
0395 
0396 static void serial_pxa_shutdown(struct uart_port *port)
0397 {
0398     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0399     unsigned long flags;
0400 
0401     free_irq(up->port.irq, up);
0402 
0403     /*
0404      * Disable interrupts from this port
0405      */
0406     up->ier = 0;
0407     serial_out(up, UART_IER, 0);
0408 
0409     spin_lock_irqsave(&up->port.lock, flags);
0410     up->port.mctrl &= ~TIOCM_OUT2;
0411     serial_pxa_set_mctrl(&up->port, up->port.mctrl);
0412     spin_unlock_irqrestore(&up->port.lock, flags);
0413 
0414     /*
0415      * Disable break condition and FIFOs
0416      */
0417     serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
0418     serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
0419                   UART_FCR_CLEAR_RCVR |
0420                   UART_FCR_CLEAR_XMIT);
0421     serial_out(up, UART_FCR, 0);
0422 }
0423 
0424 static void
0425 serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
0426                struct ktermios *old)
0427 {
0428     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0429     unsigned char cval, fcr = 0;
0430     unsigned long flags;
0431     unsigned int baud, quot;
0432     unsigned int dll;
0433 
0434     cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
0435 
0436     if (termios->c_cflag & CSTOPB)
0437         cval |= UART_LCR_STOP;
0438     if (termios->c_cflag & PARENB)
0439         cval |= UART_LCR_PARITY;
0440     if (!(termios->c_cflag & PARODD))
0441         cval |= UART_LCR_EPAR;
0442 
0443     /*
0444      * Ask the core to calculate the divisor for us.
0445      */
0446     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
0447     quot = uart_get_divisor(port, baud);
0448 
0449     if ((up->port.uartclk / quot) < (2400 * 16))
0450         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
0451     else if ((up->port.uartclk / quot) < (230400 * 16))
0452         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
0453     else
0454         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
0455 
0456     /*
0457      * Ok, we're now changing the port state.  Do it with
0458      * interrupts disabled.
0459      */
0460     spin_lock_irqsave(&up->port.lock, flags);
0461 
0462     /*
0463      * Ensure the port will be enabled.
0464      * This is required especially for serial console.
0465      */
0466     up->ier |= UART_IER_UUE;
0467 
0468     /*
0469      * Update the per-port timeout.
0470      */
0471     uart_update_timeout(port, termios->c_cflag, baud);
0472 
0473     up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
0474     if (termios->c_iflag & INPCK)
0475         up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
0476     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0477         up->port.read_status_mask |= UART_LSR_BI;
0478 
0479     /*
0480      * Characters to ignore
0481      */
0482     up->port.ignore_status_mask = 0;
0483     if (termios->c_iflag & IGNPAR)
0484         up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
0485     if (termios->c_iflag & IGNBRK) {
0486         up->port.ignore_status_mask |= UART_LSR_BI;
0487         /*
0488          * If we're ignoring parity and break indicators,
0489          * ignore overruns too (for real raw support).
0490          */
0491         if (termios->c_iflag & IGNPAR)
0492             up->port.ignore_status_mask |= UART_LSR_OE;
0493     }
0494 
0495     /*
0496      * ignore all characters if CREAD is not set
0497      */
0498     if ((termios->c_cflag & CREAD) == 0)
0499         up->port.ignore_status_mask |= UART_LSR_DR;
0500 
0501     /*
0502      * CTS flow control flag and modem status interrupts
0503      */
0504     up->ier &= ~UART_IER_MSI;
0505     if (UART_ENABLE_MS(&up->port, termios->c_cflag))
0506         up->ier |= UART_IER_MSI;
0507 
0508     serial_out(up, UART_IER, up->ier);
0509 
0510     if (termios->c_cflag & CRTSCTS)
0511         up->mcr |= UART_MCR_AFE;
0512     else
0513         up->mcr &= ~UART_MCR_AFE;
0514 
0515     serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
0516     serial_out(up, UART_DLL, quot & 0xff);      /* LS of divisor */
0517 
0518     /*
0519      * work around Errata #75 according to Intel(R) PXA27x Processor Family
0520      * Specification Update (Nov 2005)
0521      */
0522     dll = serial_in(up, UART_DLL);
0523     WARN_ON(dll != (quot & 0xff));
0524 
0525     serial_out(up, UART_DLM, quot >> 8);        /* MS of divisor */
0526     serial_out(up, UART_LCR, cval);         /* reset DLAB */
0527     up->lcr = cval;                 /* Save LCR */
0528     serial_pxa_set_mctrl(&up->port, up->port.mctrl);
0529     serial_out(up, UART_FCR, fcr);
0530     spin_unlock_irqrestore(&up->port.lock, flags);
0531 }
0532 
0533 static void
0534 serial_pxa_pm(struct uart_port *port, unsigned int state,
0535           unsigned int oldstate)
0536 {
0537     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0538 
0539     if (!state)
0540         clk_prepare_enable(up->clk);
0541     else
0542         clk_disable_unprepare(up->clk);
0543 }
0544 
0545 static void serial_pxa_release_port(struct uart_port *port)
0546 {
0547 }
0548 
0549 static int serial_pxa_request_port(struct uart_port *port)
0550 {
0551     return 0;
0552 }
0553 
0554 static void serial_pxa_config_port(struct uart_port *port, int flags)
0555 {
0556     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0557     up->port.type = PORT_PXA;
0558 }
0559 
0560 static int
0561 serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
0562 {
0563     /* we don't want the core code to modify any port params */
0564     return -EINVAL;
0565 }
0566 
0567 static const char *
0568 serial_pxa_type(struct uart_port *port)
0569 {
0570     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0571     return up->name;
0572 }
0573 
0574 static struct uart_pxa_port *serial_pxa_ports[4];
0575 static struct uart_driver serial_pxa_reg;
0576 
0577 #ifdef CONFIG_SERIAL_PXA_CONSOLE
0578 
0579 /*
0580  *  Wait for transmitter & holding register to empty
0581  */
0582 static void wait_for_xmitr(struct uart_pxa_port *up)
0583 {
0584     unsigned int status, tmout = 10000;
0585 
0586     /* Wait up to 10ms for the character(s) to be sent. */
0587     do {
0588         status = serial_in(up, UART_LSR);
0589 
0590         if (status & UART_LSR_BI)
0591             up->lsr_break_flag = UART_LSR_BI;
0592 
0593         if (--tmout == 0)
0594             break;
0595         udelay(1);
0596     } while (!uart_lsr_tx_empty(status));
0597 
0598     /* Wait up to 1s for flow control if necessary */
0599     if (up->port.flags & UPF_CONS_FLOW) {
0600         tmout = 1000000;
0601         while (--tmout &&
0602                ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
0603             udelay(1);
0604     }
0605 }
0606 
0607 static void serial_pxa_console_putchar(struct uart_port *port, unsigned char ch)
0608 {
0609     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0610 
0611     wait_for_xmitr(up);
0612     serial_out(up, UART_TX, ch);
0613 }
0614 
0615 /*
0616  * Print a string to the serial port trying not to disturb
0617  * any possible real use of the port...
0618  *
0619  *  The console_lock must be held when we get here.
0620  */
0621 static void
0622 serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
0623 {
0624     struct uart_pxa_port *up = serial_pxa_ports[co->index];
0625     unsigned int ier;
0626     unsigned long flags;
0627     int locked = 1;
0628 
0629     clk_enable(up->clk);
0630     local_irq_save(flags);
0631     if (up->port.sysrq)
0632         locked = 0;
0633     else if (oops_in_progress)
0634         locked = spin_trylock(&up->port.lock);
0635     else
0636         spin_lock(&up->port.lock);
0637 
0638     /*
0639      *  First save the IER then disable the interrupts
0640      */
0641     ier = serial_in(up, UART_IER);
0642     serial_out(up, UART_IER, UART_IER_UUE);
0643 
0644     uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
0645 
0646     /*
0647      *  Finally, wait for transmitter to become empty
0648      *  and restore the IER
0649      */
0650     wait_for_xmitr(up);
0651     serial_out(up, UART_IER, ier);
0652 
0653     if (locked)
0654         spin_unlock(&up->port.lock);
0655     local_irq_restore(flags);
0656     clk_disable(up->clk);
0657 
0658 }
0659 
0660 #ifdef CONFIG_CONSOLE_POLL
0661 /*
0662  * Console polling routines for writing and reading from the uart while
0663  * in an interrupt or debug context.
0664  */
0665 
0666 static int serial_pxa_get_poll_char(struct uart_port *port)
0667 {
0668     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0669     unsigned char lsr = serial_in(up, UART_LSR);
0670 
0671     while (!(lsr & UART_LSR_DR))
0672         lsr = serial_in(up, UART_LSR);
0673 
0674     return serial_in(up, UART_RX);
0675 }
0676 
0677 
0678 static void serial_pxa_put_poll_char(struct uart_port *port,
0679              unsigned char c)
0680 {
0681     unsigned int ier;
0682     struct uart_pxa_port *up = (struct uart_pxa_port *)port;
0683 
0684     /*
0685      *  First save the IER then disable the interrupts
0686      */
0687     ier = serial_in(up, UART_IER);
0688     serial_out(up, UART_IER, UART_IER_UUE);
0689 
0690     wait_for_xmitr(up);
0691     /*
0692      *  Send the character out.
0693      */
0694     serial_out(up, UART_TX, c);
0695 
0696     /*
0697      *  Finally, wait for transmitter to become empty
0698      *  and restore the IER
0699      */
0700     wait_for_xmitr(up);
0701     serial_out(up, UART_IER, ier);
0702 }
0703 
0704 #endif /* CONFIG_CONSOLE_POLL */
0705 
0706 static int __init
0707 serial_pxa_console_setup(struct console *co, char *options)
0708 {
0709     struct uart_pxa_port *up;
0710     int baud = 9600;
0711     int bits = 8;
0712     int parity = 'n';
0713     int flow = 'n';
0714 
0715     if (co->index == -1 || co->index >= serial_pxa_reg.nr)
0716         co->index = 0;
0717     up = serial_pxa_ports[co->index];
0718     if (!up)
0719         return -ENODEV;
0720 
0721     if (options)
0722         uart_parse_options(options, &baud, &parity, &bits, &flow);
0723 
0724     return uart_set_options(&up->port, co, baud, parity, bits, flow);
0725 }
0726 
0727 static struct console serial_pxa_console = {
0728     .name       = "ttyS",
0729     .write      = serial_pxa_console_write,
0730     .device     = uart_console_device,
0731     .setup      = serial_pxa_console_setup,
0732     .flags      = CON_PRINTBUFFER,
0733     .index      = -1,
0734     .data       = &serial_pxa_reg,
0735 };
0736 
0737 #define PXA_CONSOLE &serial_pxa_console
0738 #else
0739 #define PXA_CONSOLE NULL
0740 #endif
0741 
0742 static const struct uart_ops serial_pxa_pops = {
0743     .tx_empty   = serial_pxa_tx_empty,
0744     .set_mctrl  = serial_pxa_set_mctrl,
0745     .get_mctrl  = serial_pxa_get_mctrl,
0746     .stop_tx    = serial_pxa_stop_tx,
0747     .start_tx   = serial_pxa_start_tx,
0748     .stop_rx    = serial_pxa_stop_rx,
0749     .enable_ms  = serial_pxa_enable_ms,
0750     .break_ctl  = serial_pxa_break_ctl,
0751     .startup    = serial_pxa_startup,
0752     .shutdown   = serial_pxa_shutdown,
0753     .set_termios    = serial_pxa_set_termios,
0754     .pm     = serial_pxa_pm,
0755     .type       = serial_pxa_type,
0756     .release_port   = serial_pxa_release_port,
0757     .request_port   = serial_pxa_request_port,
0758     .config_port    = serial_pxa_config_port,
0759     .verify_port    = serial_pxa_verify_port,
0760 #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
0761     .poll_get_char = serial_pxa_get_poll_char,
0762     .poll_put_char = serial_pxa_put_poll_char,
0763 #endif
0764 };
0765 
0766 static struct uart_driver serial_pxa_reg = {
0767     .owner      = THIS_MODULE,
0768     .driver_name    = "PXA serial",
0769     .dev_name   = "ttyS",
0770     .major      = TTY_MAJOR,
0771     .minor      = 64,
0772     .nr     = 4,
0773     .cons       = PXA_CONSOLE,
0774 };
0775 
0776 #ifdef CONFIG_PM
0777 static int serial_pxa_suspend(struct device *dev)
0778 {
0779         struct uart_pxa_port *sport = dev_get_drvdata(dev);
0780 
0781         if (sport)
0782                 uart_suspend_port(&serial_pxa_reg, &sport->port);
0783 
0784         return 0;
0785 }
0786 
0787 static int serial_pxa_resume(struct device *dev)
0788 {
0789         struct uart_pxa_port *sport = dev_get_drvdata(dev);
0790 
0791         if (sport)
0792                 uart_resume_port(&serial_pxa_reg, &sport->port);
0793 
0794         return 0;
0795 }
0796 
0797 static const struct dev_pm_ops serial_pxa_pm_ops = {
0798     .suspend    = serial_pxa_suspend,
0799     .resume     = serial_pxa_resume,
0800 };
0801 #endif
0802 
0803 static const struct of_device_id serial_pxa_dt_ids[] = {
0804     { .compatible = "mrvl,pxa-uart", },
0805     { .compatible = "mrvl,mmp-uart", },
0806     {}
0807 };
0808 
0809 static int serial_pxa_probe_dt(struct platform_device *pdev,
0810                    struct uart_pxa_port *sport)
0811 {
0812     struct device_node *np = pdev->dev.of_node;
0813     int ret;
0814 
0815     if (!np)
0816         return 1;
0817 
0818     ret = of_alias_get_id(np, "serial");
0819     if (ret < 0) {
0820         dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
0821         return ret;
0822     }
0823     sport->port.line = ret;
0824     return 0;
0825 }
0826 
0827 static int serial_pxa_probe(struct platform_device *dev)
0828 {
0829     struct uart_pxa_port *sport;
0830     struct resource *mmres;
0831     int ret;
0832     int irq;
0833 
0834     mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
0835     if (!mmres)
0836         return -ENODEV;
0837 
0838     irq = platform_get_irq(dev, 0);
0839     if (irq < 0)
0840         return irq;
0841 
0842     sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
0843     if (!sport)
0844         return -ENOMEM;
0845 
0846     sport->clk = clk_get(&dev->dev, NULL);
0847     if (IS_ERR(sport->clk)) {
0848         ret = PTR_ERR(sport->clk);
0849         goto err_free;
0850     }
0851 
0852     ret = clk_prepare(sport->clk);
0853     if (ret) {
0854         clk_put(sport->clk);
0855         goto err_free;
0856     }
0857 
0858     sport->port.type = PORT_PXA;
0859     sport->port.iotype = UPIO_MEM;
0860     sport->port.mapbase = mmres->start;
0861     sport->port.irq = irq;
0862     sport->port.fifosize = 64;
0863     sport->port.ops = &serial_pxa_pops;
0864     sport->port.dev = &dev->dev;
0865     sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
0866     sport->port.uartclk = clk_get_rate(sport->clk);
0867     sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
0868 
0869     ret = serial_pxa_probe_dt(dev, sport);
0870     if (ret > 0)
0871         sport->port.line = dev->id;
0872     else if (ret < 0)
0873         goto err_clk;
0874     if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
0875         dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
0876         ret = -EINVAL;
0877         goto err_clk;
0878     }
0879     snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
0880 
0881     sport->port.membase = ioremap(mmres->start, resource_size(mmres));
0882     if (!sport->port.membase) {
0883         ret = -ENOMEM;
0884         goto err_clk;
0885     }
0886 
0887     serial_pxa_ports[sport->port.line] = sport;
0888 
0889     uart_add_one_port(&serial_pxa_reg, &sport->port);
0890     platform_set_drvdata(dev, sport);
0891 
0892     return 0;
0893 
0894  err_clk:
0895     clk_unprepare(sport->clk);
0896     clk_put(sport->clk);
0897  err_free:
0898     kfree(sport);
0899     return ret;
0900 }
0901 
0902 static struct platform_driver serial_pxa_driver = {
0903         .probe          = serial_pxa_probe,
0904 
0905     .driver     = {
0906             .name   = "pxa2xx-uart",
0907 #ifdef CONFIG_PM
0908         .pm = &serial_pxa_pm_ops,
0909 #endif
0910         .suppress_bind_attrs = true,
0911         .of_match_table = serial_pxa_dt_ids,
0912     },
0913 };
0914 
0915 
0916 /* 8250 driver for PXA serial ports should be used */
0917 static int __init serial_pxa_init(void)
0918 {
0919     int ret;
0920 
0921     ret = uart_register_driver(&serial_pxa_reg);
0922     if (ret != 0)
0923         return ret;
0924 
0925     ret = platform_driver_register(&serial_pxa_driver);
0926     if (ret != 0)
0927         uart_unregister_driver(&serial_pxa_reg);
0928 
0929     return ret;
0930 }
0931 device_initcall(serial_pxa_init);
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