tty/serial/pmac_zilog.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __PMAC_ZILOG_H__
0003 #define __PMAC_ZILOG_H__
0004
0005 /*
0006  * At most 2 ESCCs with 2 ports each
0007  */
0008 #define MAX_ZS_PORTS    4
0009
0010 /*
0011  * We wrap our port structure around the generic uart_port.
0012  */
0013 #define NUM_ZSREGS    17
0014
0015 struct uart_pmac_port {
0016     struct uart_port        port;
0017     struct uart_pmac_port       *mate;
0018
0019 #ifdef CONFIG_PPC_PMAC
0020     /* macio_dev for the escc holding this port (maybe be null on
0021      * early inited port)
0022      */
0023     struct macio_dev        *dev;
0024     /* device node to this port, this points to one of 2 childs
0025      * of "escc" node (ie. ch-a or ch-b)
0026      */
0027     struct device_node      *node;
0028 #else
0029     struct platform_device      *pdev;
0030 #endif
0031
0032     /* Port type as obtained from device tree (IRDA, modem, ...) */
0033     int             port_type;
0034     u8              curregs[NUM_ZSREGS];
0035
0036     unsigned int            flags;
0037 #define PMACZILOG_FLAG_IS_CONS      0x00000001
0038 #define PMACZILOG_FLAG_IS_KGDB      0x00000002
0039 #define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
0040 #define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
0041 #define PMACZILOG_FLAG_REGS_HELD    0x00000010
0042 #define PMACZILOG_FLAG_TX_STOPPED   0x00000020
0043 #define PMACZILOG_FLAG_TX_ACTIVE    0x00000040
0044 #define PMACZILOG_FLAG_IS_IRDA      0x00000100
0045 #define PMACZILOG_FLAG_IS_INTMODEM  0x00000200
0046 #define PMACZILOG_FLAG_RSRC_REQUESTED   0x00000800
0047 #define PMACZILOG_FLAG_IS_OPEN      0x00002000
0048 #define PMACZILOG_FLAG_IS_EXTCLK    0x00008000
0049 #define PMACZILOG_FLAG_BREAK        0x00010000
0050
0051     unsigned char           parity_mask;
0052     unsigned char           prev_status;
0053
0054     volatile u8         __iomem *control_reg;
0055     volatile u8         __iomem *data_reg;
0056
0057     unsigned char           irq_name[8];
0058 };
0059
0060 #define to_pmz(p) ((struct uart_pmac_port *)(p))
0061
0062 static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
0063 {
0064     if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
0065         return uap;
0066     return uap->mate;
0067 }
0068
0069 /*
0070  * Register accessors. Note that we don't need to enforce a recovery
0071  * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
0072  * though if we try to use this driver on older machines, we might have
0073  * to add it back
0074  */
0075 static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
0076 {
0077     if (reg != 0)
0078         writeb(reg, port->control_reg);
0079     return readb(port->control_reg);
0080 }
0081
0082 static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
0083 {
0084     if (reg != 0)
0085         writeb(reg, port->control_reg);
0086     writeb(value, port->control_reg);
0087 }
0088
0089 static inline u8 read_zsdata(struct uart_pmac_port *port)
0090 {
0091     return readb(port->data_reg);
0092 }
0093
0094 static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
0095 {
0096     writeb(data, port->data_reg);
0097 }
0098
0099 static inline void zssync(struct uart_pmac_port *port)
0100 {
0101     (void)readb(port->control_reg);
0102 }
0103
0104 /* Conversion routines to/from brg time constants from/to bits
0105  * per second.
0106  */
0107 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
0108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
0109
0110 #define ZS_CLOCK         3686400    /* Z8530 RTxC input clock rate */
0111
0112 /* The Zilog register set */
0113
0114 #define FLAG    0x7e
0115
0116 /* Write Register 0 */
0117 #define R0  0       /* Register selects */
0118 #define R1  1
0119 #define R2  2
0120 #define R3  3
0121 #define R4  4
0122 #define R5  5
0123 #define R6  6
0124 #define R7  7
0125 #define R8  8
0126 #define R9  9
0127 #define R10 10
0128 #define R11 11
0129 #define R12 12
0130 #define R13 13
0131 #define R14 14
0132 #define R15 15
0133 #define R7P 16
0134
0135 #define NULLCODE    0   /* Null Code */
0136 #define POINT_HIGH  0x8 /* Select upper half of registers */
0137 #define RES_EXT_INT 0x10    /* Reset Ext. Status Interrupts */
0138 #define SEND_ABORT  0x18    /* HDLC Abort */
0139 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
0140 #define RES_Tx_P    0x28    /* Reset TxINT Pending */
0141 #define ERR_RES     0x30    /* Error Reset */
0142 #define RES_H_IUS   0x38    /* Reset highest IUS */
0143
0144 #define RES_Rx_CRC  0x40    /* Reset Rx CRC Checker */
0145 #define RES_Tx_CRC  0x80    /* Reset Tx CRC Checker */
0146 #define RES_EOM_L   0xC0    /* Reset EOM latch */
0147
0148 /* Write Register 1 */
0149
0150 #define EXT_INT_ENAB    0x1 /* Ext Int Enable */
0151 #define TxINT_ENAB  0x2 /* Tx Int Enable */
0152 #define PAR_SPEC    0x4 /* Parity is special condition */
0153
0154 #define RxINT_DISAB 0   /* Rx Int Disable */
0155 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
0156 #define INT_ALL_Rx  0x10    /* Int on all Rx Characters or error */
0157 #define INT_ERR_Rx  0x18    /* Int on error only */
0158 #define RxINT_MASK  0x18
0159
0160 #define WT_RDY_RT   0x20    /* W/Req reflects recv if 1, xmit if 0 */
0161 #define WT_FN_RDYFN 0x40    /* W/Req pin is DMA request if 1, wait if 0 */
0162 #define WT_RDY_ENAB 0x80    /* Enable W/Req pin */
0163
0164 /* Write Register #2 (Interrupt Vector) */
0165
0166 /* Write Register 3 */
0167
0168 #define RxENABLE    0x1 /* Rx Enable */
0169 #define SYNC_L_INH  0x2 /* Sync Character Load Inhibit */
0170 #define ADD_SM      0x4 /* Address Search Mode (SDLC) */
0171 #define RxCRC_ENAB  0x8 /* Rx CRC Enable */
0172 #define ENT_HM      0x10    /* Enter Hunt Mode */
0173 #define AUTO_ENAB   0x20    /* Auto Enables */
0174 #define Rx5     0x0 /* Rx 5 Bits/Character */
0175 #define Rx7     0x40    /* Rx 7 Bits/Character */
0176 #define Rx6     0x80    /* Rx 6 Bits/Character */
0177 #define Rx8     0xc0    /* Rx 8 Bits/Character */
0178 #define RxN_MASK    0xc0
0179
0180 /* Write Register 4 */
0181
0182 #define PAR_ENAB    0x1 /* Parity Enable */
0183 #define PAR_EVEN    0x2 /* Parity Even/Odd* */
0184
0185 #define SYNC_ENAB   0   /* Sync Modes Enable */
0186 #define SB1     0x4 /* 1 stop bit/char */
0187 #define SB15        0x8 /* 1.5 stop bits/char */
0188 #define SB2     0xc /* 2 stop bits/char */
0189 #define SB_MASK     0xc
0190
0191 #define MONSYNC     0   /* 8 Bit Sync character */
0192 #define BISYNC      0x10    /* 16 bit sync character */
0193 #define SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
0194 #define EXTSYNC     0x30    /* External Sync Mode */
0195
0196 #define X1CLK       0x0 /* x1 clock mode */
0197 #define X16CLK      0x40    /* x16 clock mode */
0198 #define X32CLK      0x80    /* x32 clock mode */
0199 #define X64CLK      0xC0    /* x64 clock mode */
0200 #define XCLK_MASK   0xC0
0201
0202 /* Write Register 5 */
0203
0204 #define TxCRC_ENAB  0x1 /* Tx CRC Enable */
0205 #define RTS     0x2 /* RTS */
0206 #define SDLC_CRC    0x4 /* SDLC/CRC-16 */
0207 #define TxENABLE    0x8 /* Tx Enable */
0208 #define SND_BRK     0x10    /* Send Break */
0209 #define Tx5     0x0 /* Tx 5 bits (or less)/character */
0210 #define Tx7     0x20    /* Tx 7 bits/character */
0211 #define Tx6     0x40    /* Tx 6 bits/character */
0212 #define Tx8     0x60    /* Tx 8 bits/character */
0213 #define TxN_MASK    0x60
0214 #define DTR     0x80    /* DTR */
0215
0216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
0217
0218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
0219
0220 /* Write Register 7' (Some enhanced feature control) */
0221 #define ENEXREAD    0x40    /* Enable read of some write registers */
0222
0223 /* Write Register 8 (transmit buffer) */
0224
0225 /* Write Register 9 (Master interrupt control) */
0226 #define VIS 1   /* Vector Includes Status */
0227 #define NV  2   /* No Vector */
0228 #define DLC 4   /* Disable Lower Chain */
0229 #define MIE 8   /* Master Interrupt Enable */
0230 #define STATHI  0x10    /* Status high */
0231 #define NORESET 0   /* No reset on write to R9 */
0232 #define CHRB    0x40    /* Reset channel B */
0233 #define CHRA    0x80    /* Reset channel A */
0234 #define FHWRES  0xc0    /* Force hardware reset */
0235
0236 /* Write Register 10 (misc control bits) */
0237 #define BIT6    1   /* 6 bit/8bit sync */
0238 #define LOOPMODE 2  /* SDLC Loop mode */
0239 #define ABUNDER 4   /* Abort/flag on SDLC xmit underrun */
0240 #define MARKIDLE 8  /* Mark/flag on idle */
0241 #define GAOP    0x10    /* Go active on poll */
0242 #define NRZ 0   /* NRZ mode */
0243 #define NRZI    0x20    /* NRZI mode */
0244 #define FM1 0x40    /* FM1 (transition = 1) */
0245 #define FM0 0x60    /* FM0 (transition = 0) */
0246 #define CRCPS   0x80    /* CRC Preset I/O */
0247
0248 /* Write Register 11 (Clock Mode control) */
0249 #define TRxCXT  0   /* TRxC = Xtal output */
0250 #define TRxCTC  1   /* TRxC = Transmit clock */
0251 #define TRxCBR  2   /* TRxC = BR Generator Output */
0252 #define TRxCDP  3   /* TRxC = DPLL output */
0253 #define TRxCOI  4   /* TRxC O/I */
0254 #define TCRTxCP 0   /* Transmit clock = RTxC pin */
0255 #define TCTRxCP 8   /* Transmit clock = TRxC pin */
0256 #define TCBR    0x10    /* Transmit clock = BR Generator output */
0257 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
0258 #define RCRTxCP 0   /* Receive clock = RTxC pin */
0259 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
0260 #define RCBR    0x40    /* Receive clock = BR Generator output */
0261 #define RCDPLL  0x60    /* Receive clock = DPLL output */
0262 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
0263
0264 /* Write Register 12 (lower byte of baud rate generator time constant) */
0265
0266 /* Write Register 13 (upper byte of baud rate generator time constant) */
0267
0268 /* Write Register 14 (Misc control bits) */
0269 #define BRENAB  1   /* Baud rate generator enable */
0270 #define BRSRC   2   /* Baud rate generator source */
0271 #define DTRREQ  4   /* DTR/Request function */
0272 #define AUTOECHO 8  /* Auto Echo */
0273 #define LOOPBAK 0x10    /* Local loopback */
0274 #define SEARCH  0x20    /* Enter search mode */
0275 #define RMC 0x40    /* Reset missing clock */
0276 #define DISDPLL 0x60    /* Disable DPLL */
0277 #define SSBR    0x80    /* Set DPLL source = BR generator */
0278 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
0279 #define SFMM    0xc0    /* Set FM mode */
0280 #define SNRZI   0xe0    /* Set NRZI mode */
0281
0282 /* Write Register 15 (external/status interrupt control) */
0283 #define EN85C30 1   /* Enable some 85c30-enhanced registers */
0284 #define ZCIE    2   /* Zero count IE */
0285 #define ENSTFIFO 4  /* Enable status FIFO (SDLC) */
0286 #define DCDIE   8   /* DCD IE */
0287 #define SYNCIE  0x10    /* Sync/hunt IE */
0288 #define CTSIE   0x20    /* CTS IE */
0289 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
0290 #define BRKIE   0x80    /* Break/Abort IE */
0291
0292
0293 /* Read Register 0 */
0294 #define Rx_CH_AV    0x1 /* Rx Character Available */
0295 #define ZCOUNT      0x2 /* Zero count */
0296 #define Tx_BUF_EMP  0x4 /* Tx Buffer empty */
0297 #define DCD     0x8 /* DCD */
0298 #define SYNC_HUNT   0x10    /* Sync/hunt */
0299 #define CTS     0x20    /* CTS */
0300 #define TxEOM       0x40    /* Tx underrun */
0301 #define BRK_ABRT    0x80    /* Break/Abort */
0302
0303 /* Read Register 1 */
0304 #define ALL_SNT     0x1 /* All sent */
0305 /* Residue Data for 8 Rx bits/char programmed */
0306 #define RES3        0x8 /* 0/3 */
0307 #define RES4        0x4 /* 0/4 */
0308 #define RES5        0xc /* 0/5 */
0309 #define RES6        0x2 /* 0/6 */
0310 #define RES7        0xa /* 0/7 */
0311 #define RES8        0x6 /* 0/8 */
0312 #define RES18       0xe /* 1/8 */
0313 #define RES28       0x0 /* 2/8 */
0314 /* Special Rx Condition Interrupts */
0315 #define PAR_ERR     0x10    /* Parity error */
0316 #define Rx_OVR      0x20    /* Rx Overrun Error */
0317 #define CRC_ERR     0x40    /* CRC/Framing Error */
0318 #define END_FR      0x80    /* End of Frame (SDLC) */
0319
0320 /* Read Register 2 (channel b only) - Interrupt vector */
0321 #define CHB_Tx_EMPTY    0x00
0322 #define CHB_EXT_STAT    0x02
0323 #define CHB_Rx_AVAIL    0x04
0324 #define CHB_SPECIAL 0x06
0325 #define CHA_Tx_EMPTY    0x08
0326 #define CHA_EXT_STAT    0x0a
0327 #define CHA_Rx_AVAIL    0x0c
0328 #define CHA_SPECIAL 0x0e
0329 #define STATUS_MASK 0x06
0330
0331 /* Read Register 3 (interrupt pending register) ch a only */
0332 #define CHBEXT  0x1     /* Channel B Ext/Stat IP */
0333 #define CHBTxIP 0x2     /* Channel B Tx IP */
0334 #define CHBRxIP 0x4     /* Channel B Rx IP */
0335 #define CHAEXT  0x8     /* Channel A Ext/Stat IP */
0336 #define CHATxIP 0x10        /* Channel A Tx IP */
0337 #define CHARxIP 0x20        /* Channel A Rx IP */
0338
0339 /* Read Register 8 (receive data register) */
0340
0341 /* Read Register 10  (misc status bits) */
0342 #define ONLOOP  2       /* On loop */
0343 #define LOOPSEND 0x10       /* Loop sending */
0344 #define CLK2MIS 0x40        /* Two clocks missing */
0345 #define CLK1MIS 0x80        /* One clock missing */
0346
0347 /* Read Register 12 (lower byte of baud rate generator constant) */
0348
0349 /* Read Register 13 (upper byte of baud rate generator constant) */
0350
0351 /* Read Register 15 (value of WR 15) */
0352
0353 /* Misc macros */
0354 #define ZS_CLEARERR(port)    (write_zsreg(port, 0, ERR_RES))
0355 #define ZS_CLEARFIFO(port)   do {                       \
0356                      read_zsdata(port); \
0357                      read_zsdata(port); \
0358                      read_zsdata(port); \
0359                 } while(0)
0360
0361 #define ZS_IS_CONS(UP)          ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
0362 #define ZS_IS_KGDB(UP)          ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
0363 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
0364 #define ZS_REGS_HELD(UP)        ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
0365 #define ZS_TX_STOPPED(UP)       ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
0366 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
0367 #define ZS_WANTS_MODEM_STATUS(UP)   ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
0368 #define ZS_IS_IRDA(UP)          ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
0369 #define ZS_IS_INTMODEM(UP)      ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
0370 #define ZS_IS_OPEN(UP)          ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
0371 #define ZS_IS_EXTCLK(UP)        ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
0372
0373 #endif /* __PMAC_ZILOG_H__ */