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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * PIC32 Integrated Serial Driver.
0004  *
0005  * Copyright (C) 2015 Microchip Technology, Inc.
0006  *
0007  * Authors:
0008  *   Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/init.h>
0018 #include <linux/module.h>
0019 #include <linux/slab.h>
0020 #include <linux/console.h>
0021 #include <linux/clk.h>
0022 #include <linux/tty.h>
0023 #include <linux/tty_flip.h>
0024 #include <linux/serial_core.h>
0025 #include <linux/delay.h>
0026 
0027 #include <asm/mach-pic32/pic32.h>
0028 
0029 /* UART name and device definitions */
0030 #define PIC32_DEV_NAME      "pic32-uart"
0031 #define PIC32_MAX_UARTS     6
0032 #define PIC32_SDEV_NAME     "ttyPIC"
0033 
0034 #define PIC32_UART_DFLT_BRATE       9600
0035 #define PIC32_UART_TX_FIFO_DEPTH    8
0036 #define PIC32_UART_RX_FIFO_DEPTH    8
0037 
0038 #define PIC32_UART_MODE     0x00
0039 #define PIC32_UART_STA      0x10
0040 #define PIC32_UART_TX       0x20
0041 #define PIC32_UART_RX       0x30
0042 #define PIC32_UART_BRG      0x40
0043 
0044 /* struct pic32_sport - pic32 serial port descriptor
0045  * @port: uart port descriptor
0046  * @idx: port index
0047  * @irq_fault: virtual fault interrupt number
0048  * @irq_fault_name: irq fault name
0049  * @irq_rx: virtual rx interrupt number
0050  * @irq_rx_name: irq rx name
0051  * @irq_tx: virtual tx interrupt number
0052  * @irq_tx_name: irq tx name
0053  * @cts_gpio: clear to send gpio
0054  * @dev: device descriptor
0055  **/
0056 struct pic32_sport {
0057     struct uart_port port;
0058     int idx;
0059 
0060     int irq_fault;
0061     const char *irq_fault_name;
0062     int irq_rx;
0063     const char *irq_rx_name;
0064     int irq_tx;
0065     const char *irq_tx_name;
0066     bool enable_tx_irq;
0067 
0068     bool hw_flow_ctrl;
0069     int cts_gpio;
0070 
0071     struct clk *clk;
0072 
0073     struct device *dev;
0074 };
0075 
0076 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
0077 {
0078     return container_of(port, struct pic32_sport, port);
0079 }
0080 
0081 static inline void pic32_uart_writel(struct pic32_sport *sport,
0082                     u32 reg, u32 val)
0083 {
0084     __raw_writel(val, sport->port.membase + reg);
0085 }
0086 
0087 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
0088 {
0089     return  __raw_readl(sport->port.membase + reg);
0090 }
0091 
0092 /* pic32 uart mode register bits */
0093 #define PIC32_UART_MODE_ON        BIT(15)
0094 #define PIC32_UART_MODE_FRZ       BIT(14)
0095 #define PIC32_UART_MODE_SIDL      BIT(13)
0096 #define PIC32_UART_MODE_IREN      BIT(12)
0097 #define PIC32_UART_MODE_RTSMD     BIT(11)
0098 #define PIC32_UART_MODE_RESV1     BIT(10)
0099 #define PIC32_UART_MODE_UEN1      BIT(9)
0100 #define PIC32_UART_MODE_UEN0      BIT(8)
0101 #define PIC32_UART_MODE_WAKE      BIT(7)
0102 #define PIC32_UART_MODE_LPBK      BIT(6)
0103 #define PIC32_UART_MODE_ABAUD     BIT(5)
0104 #define PIC32_UART_MODE_RXINV     BIT(4)
0105 #define PIC32_UART_MODE_BRGH      BIT(3)
0106 #define PIC32_UART_MODE_PDSEL1    BIT(2)
0107 #define PIC32_UART_MODE_PDSEL0    BIT(1)
0108 #define PIC32_UART_MODE_STSEL     BIT(0)
0109 
0110 /* pic32 uart status register bits */
0111 #define PIC32_UART_STA_UTXISEL1   BIT(15)
0112 #define PIC32_UART_STA_UTXISEL0   BIT(14)
0113 #define PIC32_UART_STA_UTXINV     BIT(13)
0114 #define PIC32_UART_STA_URXEN      BIT(12)
0115 #define PIC32_UART_STA_UTXBRK     BIT(11)
0116 #define PIC32_UART_STA_UTXEN      BIT(10)
0117 #define PIC32_UART_STA_UTXBF      BIT(9)
0118 #define PIC32_UART_STA_TRMT       BIT(8)
0119 #define PIC32_UART_STA_URXISEL1   BIT(7)
0120 #define PIC32_UART_STA_URXISEL0   BIT(6)
0121 #define PIC32_UART_STA_ADDEN      BIT(5)
0122 #define PIC32_UART_STA_RIDLE      BIT(4)
0123 #define PIC32_UART_STA_PERR       BIT(3)
0124 #define PIC32_UART_STA_FERR       BIT(2)
0125 #define PIC32_UART_STA_OERR       BIT(1)
0126 #define PIC32_UART_STA_URXDA      BIT(0)
0127 
0128 /* pic32_sport pointer for console use */
0129 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
0130 
0131 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
0132 {
0133     /* wait for tx empty, otherwise chars will be lost or corrupted */
0134     while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
0135         udelay(1);
0136 }
0137 
0138 /* serial core request to check if uart tx buffer is empty */
0139 static unsigned int pic32_uart_tx_empty(struct uart_port *port)
0140 {
0141     struct pic32_sport *sport = to_pic32_sport(port);
0142     u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
0143 
0144     return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
0145 }
0146 
0147 /* serial core request to set UART outputs */
0148 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0149 {
0150     struct pic32_sport *sport = to_pic32_sport(port);
0151 
0152     /* set loopback mode */
0153     if (mctrl & TIOCM_LOOP)
0154         pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0155                     PIC32_UART_MODE_LPBK);
0156     else
0157         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0158                     PIC32_UART_MODE_LPBK);
0159 }
0160 
0161 /* get the state of CTS input pin for this port */
0162 static unsigned int get_cts_state(struct pic32_sport *sport)
0163 {
0164     /* read and invert UxCTS */
0165     if (gpio_is_valid(sport->cts_gpio))
0166         return !gpio_get_value(sport->cts_gpio);
0167 
0168     return 1;
0169 }
0170 
0171 /* serial core request to return the state of misc UART input pins */
0172 static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
0173 {
0174     struct pic32_sport *sport = to_pic32_sport(port);
0175     unsigned int mctrl = 0;
0176 
0177     if (!sport->hw_flow_ctrl)
0178         mctrl |= TIOCM_CTS;
0179     else if (get_cts_state(sport))
0180         mctrl |= TIOCM_CTS;
0181 
0182     /* DSR and CD are not supported in PIC32, so return 1
0183      * RI is not supported in PIC32, so return 0
0184      */
0185     mctrl |= TIOCM_CD;
0186     mctrl |= TIOCM_DSR;
0187 
0188     return mctrl;
0189 }
0190 
0191 /* stop tx and start tx are not called in pairs, therefore a flag indicates
0192  * the status of irq to control the irq-depth.
0193  */
0194 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
0195 {
0196     if (en && !sport->enable_tx_irq) {
0197         enable_irq(sport->irq_tx);
0198         sport->enable_tx_irq = true;
0199     } else if (!en && sport->enable_tx_irq) {
0200         /* use disable_irq_nosync() and not disable_irq() to avoid self
0201          * imposed deadlock by not waiting for irq handler to end,
0202          * since this callback is called from interrupt context.
0203          */
0204         disable_irq_nosync(sport->irq_tx);
0205         sport->enable_tx_irq = false;
0206     }
0207 }
0208 
0209 /* serial core request to disable tx ASAP (used for flow control) */
0210 static void pic32_uart_stop_tx(struct uart_port *port)
0211 {
0212     struct pic32_sport *sport = to_pic32_sport(port);
0213 
0214     if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
0215         return;
0216 
0217     if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
0218         return;
0219 
0220     /* wait for tx empty */
0221     pic32_wait_deplete_txbuf(sport);
0222 
0223     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0224                 PIC32_UART_STA_UTXEN);
0225     pic32_uart_irqtxen(sport, 0);
0226 }
0227 
0228 /* serial core request to (re)enable tx */
0229 static void pic32_uart_start_tx(struct uart_port *port)
0230 {
0231     struct pic32_sport *sport = to_pic32_sport(port);
0232 
0233     pic32_uart_irqtxen(sport, 1);
0234     pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
0235                 PIC32_UART_STA_UTXEN);
0236 }
0237 
0238 /* serial core request to stop rx, called before port shutdown */
0239 static void pic32_uart_stop_rx(struct uart_port *port)
0240 {
0241     struct pic32_sport *sport = to_pic32_sport(port);
0242 
0243     /* disable rx interrupts */
0244     disable_irq(sport->irq_rx);
0245 
0246     /* receiver Enable bit OFF */
0247     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0248                 PIC32_UART_STA_URXEN);
0249 }
0250 
0251 /* serial core request to start/stop emitting break char */
0252 static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
0253 {
0254     struct pic32_sport *sport = to_pic32_sport(port);
0255     unsigned long flags;
0256 
0257     spin_lock_irqsave(&port->lock, flags);
0258 
0259     if (ctl)
0260         pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
0261                     PIC32_UART_STA_UTXBRK);
0262     else
0263         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0264                     PIC32_UART_STA_UTXBRK);
0265 
0266     spin_unlock_irqrestore(&port->lock, flags);
0267 }
0268 
0269 /* get port type in string format */
0270 static const char *pic32_uart_type(struct uart_port *port)
0271 {
0272     return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
0273 }
0274 
0275 /* read all chars in rx fifo and send them to core */
0276 static void pic32_uart_do_rx(struct uart_port *port)
0277 {
0278     struct pic32_sport *sport = to_pic32_sport(port);
0279     struct tty_port *tty;
0280     unsigned int max_count;
0281 
0282     /* limit number of char read in interrupt, should not be
0283      * higher than fifo size anyway since we're much faster than
0284      * serial port
0285      */
0286     max_count = PIC32_UART_RX_FIFO_DEPTH;
0287 
0288     spin_lock(&port->lock);
0289 
0290     tty = &port->state->port;
0291 
0292     do {
0293         u32 sta_reg, c;
0294         char flag;
0295 
0296         /* get overrun/fifo empty information from status register */
0297         sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
0298         if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
0299 
0300             /* fifo reset is required to clear interrupt */
0301             pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0302                         PIC32_UART_STA_OERR);
0303 
0304             port->icount.overrun++;
0305             tty_insert_flip_char(tty, 0, TTY_OVERRUN);
0306         }
0307 
0308         /* Can at least one more character can be read? */
0309         if (!(sta_reg & PIC32_UART_STA_URXDA))
0310             break;
0311 
0312         /* read the character and increment the rx counter */
0313         c = pic32_uart_readl(sport, PIC32_UART_RX);
0314 
0315         port->icount.rx++;
0316         flag = TTY_NORMAL;
0317         c &= 0xff;
0318 
0319         if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
0320                  (sta_reg & PIC32_UART_STA_FERR))) {
0321 
0322             /* do stats first */
0323             if (sta_reg & PIC32_UART_STA_PERR)
0324                 port->icount.parity++;
0325             if (sta_reg & PIC32_UART_STA_FERR)
0326                 port->icount.frame++;
0327 
0328             /* update flag wrt read_status_mask */
0329             sta_reg &= port->read_status_mask;
0330 
0331             if (sta_reg & PIC32_UART_STA_FERR)
0332                 flag = TTY_FRAME;
0333             if (sta_reg & PIC32_UART_STA_PERR)
0334                 flag = TTY_PARITY;
0335         }
0336 
0337         if (uart_handle_sysrq_char(port, c))
0338             continue;
0339 
0340         if ((sta_reg & port->ignore_status_mask) == 0)
0341             tty_insert_flip_char(tty, c, flag);
0342 
0343     } while (--max_count);
0344 
0345     spin_unlock(&port->lock);
0346 
0347     tty_flip_buffer_push(tty);
0348 }
0349 
0350 /* fill tx fifo with chars to send, stop when fifo is about to be full
0351  * or when all chars have been sent.
0352  */
0353 static void pic32_uart_do_tx(struct uart_port *port)
0354 {
0355     struct pic32_sport *sport = to_pic32_sport(port);
0356     struct circ_buf *xmit = &port->state->xmit;
0357     unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
0358 
0359     if (port->x_char) {
0360         pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
0361         port->icount.tx++;
0362         port->x_char = 0;
0363         return;
0364     }
0365 
0366     if (uart_tx_stopped(port)) {
0367         pic32_uart_stop_tx(port);
0368         return;
0369     }
0370 
0371     if (uart_circ_empty(xmit))
0372         goto txq_empty;
0373 
0374     /* keep stuffing chars into uart tx buffer
0375      * 1) until uart fifo is full
0376      * or
0377      * 2) until the circ buffer is empty
0378      * (all chars have been sent)
0379      * or
0380      * 3) until the max count is reached
0381      * (prevents lingering here for too long in certain cases)
0382      */
0383     while (!(PIC32_UART_STA_UTXBF &
0384         pic32_uart_readl(sport, PIC32_UART_STA))) {
0385         unsigned int c = xmit->buf[xmit->tail];
0386 
0387         pic32_uart_writel(sport, PIC32_UART_TX, c);
0388 
0389         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0390         port->icount.tx++;
0391         if (uart_circ_empty(xmit))
0392             break;
0393         if (--max_count == 0)
0394             break;
0395     }
0396 
0397     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0398         uart_write_wakeup(port);
0399 
0400     if (uart_circ_empty(xmit))
0401         goto txq_empty;
0402 
0403     return;
0404 
0405 txq_empty:
0406     pic32_uart_irqtxen(sport, 0);
0407 }
0408 
0409 /* RX interrupt handler */
0410 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
0411 {
0412     struct uart_port *port = dev_id;
0413 
0414     pic32_uart_do_rx(port);
0415 
0416     return IRQ_HANDLED;
0417 }
0418 
0419 /* TX interrupt handler */
0420 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
0421 {
0422     struct uart_port *port = dev_id;
0423     unsigned long flags;
0424 
0425     spin_lock_irqsave(&port->lock, flags);
0426     pic32_uart_do_tx(port);
0427     spin_unlock_irqrestore(&port->lock, flags);
0428 
0429     return IRQ_HANDLED;
0430 }
0431 
0432 /* FAULT interrupt handler */
0433 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
0434 {
0435     /* do nothing: pic32_uart_do_rx() handles faults. */
0436     return IRQ_HANDLED;
0437 }
0438 
0439 /* enable rx & tx operation on uart */
0440 static void pic32_uart_en_and_unmask(struct uart_port *port)
0441 {
0442     struct pic32_sport *sport = to_pic32_sport(port);
0443 
0444     pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
0445                 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
0446     pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0447                 PIC32_UART_MODE_ON);
0448 }
0449 
0450 /* disable rx & tx operation on uart */
0451 static void pic32_uart_dsbl_and_mask(struct uart_port *port)
0452 {
0453     struct pic32_sport *sport = to_pic32_sport(port);
0454 
0455     /* wait for tx empty, otherwise chars will be lost or corrupted */
0456     pic32_wait_deplete_txbuf(sport);
0457 
0458     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0459                 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
0460     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0461                 PIC32_UART_MODE_ON);
0462 }
0463 
0464 /* serial core request to initialize uart and start rx operation */
0465 static int pic32_uart_startup(struct uart_port *port)
0466 {
0467     struct pic32_sport *sport = to_pic32_sport(port);
0468     u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
0469     unsigned long flags;
0470     int ret;
0471 
0472     local_irq_save(flags);
0473 
0474     ret = clk_prepare_enable(sport->clk);
0475     if (ret) {
0476         local_irq_restore(flags);
0477         goto out_done;
0478     }
0479 
0480     /* clear status and mode registers */
0481     pic32_uart_writel(sport, PIC32_UART_MODE, 0);
0482     pic32_uart_writel(sport, PIC32_UART_STA, 0);
0483 
0484     /* disable uart and mask all interrupts */
0485     pic32_uart_dsbl_and_mask(port);
0486 
0487     /* set default baud */
0488     pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
0489 
0490     local_irq_restore(flags);
0491 
0492     /* Each UART of a PIC32 has three interrupts therefore,
0493      * we setup driver to register the 3 irqs for the device.
0494      *
0495      * For each irq request_irq() is called with interrupt disabled.
0496      * And the irq is enabled as soon as we are ready to handle them.
0497      */
0498     sport->enable_tx_irq = false;
0499 
0500     sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
0501                       pic32_uart_type(port),
0502                       sport->idx);
0503     if (!sport->irq_fault_name) {
0504         dev_err(port->dev, "%s: kasprintf err!", __func__);
0505         ret = -ENOMEM;
0506         goto out_disable_clk;
0507     }
0508     irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
0509     ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
0510               IRQF_NO_THREAD, sport->irq_fault_name, port);
0511     if (ret) {
0512         dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
0513             __func__, sport->irq_fault, ret,
0514             pic32_uart_type(port));
0515         goto out_f;
0516     }
0517 
0518     sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
0519                        pic32_uart_type(port),
0520                        sport->idx);
0521     if (!sport->irq_rx_name) {
0522         dev_err(port->dev, "%s: kasprintf err!", __func__);
0523         ret = -ENOMEM;
0524         goto out_f;
0525     }
0526     irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
0527     ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
0528               IRQF_NO_THREAD, sport->irq_rx_name, port);
0529     if (ret) {
0530         dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
0531             __func__, sport->irq_rx, ret,
0532             pic32_uart_type(port));
0533         goto out_r;
0534     }
0535 
0536     sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
0537                        pic32_uart_type(port),
0538                        sport->idx);
0539     if (!sport->irq_tx_name) {
0540         dev_err(port->dev, "%s: kasprintf err!", __func__);
0541         ret = -ENOMEM;
0542         goto out_r;
0543     }
0544     irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
0545     ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
0546               IRQF_NO_THREAD, sport->irq_tx_name, port);
0547     if (ret) {
0548         dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
0549             __func__, sport->irq_tx, ret,
0550             pic32_uart_type(port));
0551         goto out_t;
0552     }
0553 
0554     local_irq_save(flags);
0555 
0556     /* set rx interrupt on first receive */
0557     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0558             PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
0559 
0560     /* set interrupt on empty */
0561     pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
0562             PIC32_UART_STA_UTXISEL1);
0563 
0564     /* enable all interrupts and eanable uart */
0565     pic32_uart_en_and_unmask(port);
0566 
0567     local_irq_restore(flags);
0568 
0569     enable_irq(sport->irq_rx);
0570 
0571     return 0;
0572 
0573 out_t:
0574     free_irq(sport->irq_tx, port);
0575     kfree(sport->irq_tx_name);
0576 out_r:
0577     free_irq(sport->irq_rx, port);
0578     kfree(sport->irq_rx_name);
0579 out_f:
0580     free_irq(sport->irq_fault, port);
0581     kfree(sport->irq_fault_name);
0582 out_disable_clk:
0583     clk_disable_unprepare(sport->clk);
0584 out_done:
0585     return ret;
0586 }
0587 
0588 /* serial core request to flush & disable uart */
0589 static void pic32_uart_shutdown(struct uart_port *port)
0590 {
0591     struct pic32_sport *sport = to_pic32_sport(port);
0592     unsigned long flags;
0593 
0594     /* disable uart */
0595     spin_lock_irqsave(&port->lock, flags);
0596     pic32_uart_dsbl_and_mask(port);
0597     spin_unlock_irqrestore(&port->lock, flags);
0598     clk_disable_unprepare(sport->clk);
0599 
0600     /* free all 3 interrupts for this UART */
0601     free_irq(sport->irq_fault, port);
0602     kfree(sport->irq_fault_name);
0603     free_irq(sport->irq_tx, port);
0604     kfree(sport->irq_tx_name);
0605     free_irq(sport->irq_rx, port);
0606     kfree(sport->irq_rx_name);
0607 }
0608 
0609 /* serial core request to change current uart setting */
0610 static void pic32_uart_set_termios(struct uart_port *port,
0611                    struct ktermios *new,
0612                    struct ktermios *old)
0613 {
0614     struct pic32_sport *sport = to_pic32_sport(port);
0615     unsigned int baud;
0616     unsigned int quot;
0617     unsigned long flags;
0618 
0619     spin_lock_irqsave(&port->lock, flags);
0620 
0621     /* disable uart and mask all interrupts while changing speed */
0622     pic32_uart_dsbl_and_mask(port);
0623 
0624     /* stop bit options */
0625     if (new->c_cflag & CSTOPB)
0626         pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0627                     PIC32_UART_MODE_STSEL);
0628     else
0629         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0630                     PIC32_UART_MODE_STSEL);
0631 
0632     /* parity options */
0633     if (new->c_cflag & PARENB) {
0634         if (new->c_cflag & PARODD) {
0635             pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0636                     PIC32_UART_MODE_PDSEL1);
0637             pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0638                     PIC32_UART_MODE_PDSEL0);
0639         } else {
0640             pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0641                     PIC32_UART_MODE_PDSEL0);
0642             pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0643                     PIC32_UART_MODE_PDSEL1);
0644         }
0645     } else {
0646         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0647                     PIC32_UART_MODE_PDSEL1 |
0648                     PIC32_UART_MODE_PDSEL0);
0649     }
0650     /* if hw flow ctrl, then the pins must be specified in device tree */
0651     if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
0652         /* enable hardware flow control */
0653         pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
0654                     PIC32_UART_MODE_UEN1);
0655         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0656                     PIC32_UART_MODE_UEN0);
0657         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0658                     PIC32_UART_MODE_RTSMD);
0659     } else {
0660         /* disable hardware flow control */
0661         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0662                     PIC32_UART_MODE_UEN1);
0663         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0664                     PIC32_UART_MODE_UEN0);
0665         pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
0666                     PIC32_UART_MODE_RTSMD);
0667     }
0668 
0669     /* Always 8-bit */
0670     new->c_cflag |= CS8;
0671 
0672     /* Mark/Space parity is not supported */
0673     new->c_cflag &= ~CMSPAR;
0674 
0675     /* update baud */
0676     baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
0677     quot = uart_get_divisor(port, baud) - 1;
0678     pic32_uart_writel(sport, PIC32_UART_BRG, quot);
0679     uart_update_timeout(port, new->c_cflag, baud);
0680 
0681     if (tty_termios_baud_rate(new))
0682         tty_termios_encode_baud_rate(new, baud, baud);
0683 
0684     /* enable uart */
0685     pic32_uart_en_and_unmask(port);
0686 
0687     spin_unlock_irqrestore(&port->lock, flags);
0688 }
0689 
0690 /* serial core request to claim uart iomem */
0691 static int pic32_uart_request_port(struct uart_port *port)
0692 {
0693     struct platform_device *pdev = to_platform_device(port->dev);
0694     struct resource *res_mem;
0695 
0696     res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0697     if (unlikely(!res_mem))
0698         return -EINVAL;
0699 
0700     if (!request_mem_region(port->mapbase, resource_size(res_mem),
0701                 "pic32_uart_mem"))
0702         return -EBUSY;
0703 
0704     port->membase = devm_ioremap(port->dev, port->mapbase,
0705                         resource_size(res_mem));
0706     if (!port->membase) {
0707         dev_err(port->dev, "Unable to map registers\n");
0708         release_mem_region(port->mapbase, resource_size(res_mem));
0709         return -ENOMEM;
0710     }
0711 
0712     return 0;
0713 }
0714 
0715 /* serial core request to release uart iomem */
0716 static void pic32_uart_release_port(struct uart_port *port)
0717 {
0718     struct platform_device *pdev = to_platform_device(port->dev);
0719     struct resource *res_mem;
0720     unsigned int res_size;
0721 
0722     res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0723     if (unlikely(!res_mem))
0724         return;
0725     res_size = resource_size(res_mem);
0726 
0727     release_mem_region(port->mapbase, res_size);
0728 }
0729 
0730 /* serial core request to do any port required auto-configuration */
0731 static void pic32_uart_config_port(struct uart_port *port, int flags)
0732 {
0733     if (flags & UART_CONFIG_TYPE) {
0734         if (pic32_uart_request_port(port))
0735             return;
0736         port->type = PORT_PIC32;
0737     }
0738 }
0739 
0740 /* serial core request to check that port information in serinfo are suitable */
0741 static int pic32_uart_verify_port(struct uart_port *port,
0742                   struct serial_struct *serinfo)
0743 {
0744     if (port->type != PORT_PIC32)
0745         return -EINVAL;
0746     if (port->irq != serinfo->irq)
0747         return -EINVAL;
0748     if (port->iotype != serinfo->io_type)
0749         return -EINVAL;
0750     if (port->mapbase != (unsigned long)serinfo->iomem_base)
0751         return -EINVAL;
0752 
0753     return 0;
0754 }
0755 
0756 /* serial core callbacks */
0757 static const struct uart_ops pic32_uart_ops = {
0758     .tx_empty   = pic32_uart_tx_empty,
0759     .get_mctrl  = pic32_uart_get_mctrl,
0760     .set_mctrl  = pic32_uart_set_mctrl,
0761     .start_tx   = pic32_uart_start_tx,
0762     .stop_tx    = pic32_uart_stop_tx,
0763     .stop_rx    = pic32_uart_stop_rx,
0764     .break_ctl  = pic32_uart_break_ctl,
0765     .startup    = pic32_uart_startup,
0766     .shutdown   = pic32_uart_shutdown,
0767     .set_termios    = pic32_uart_set_termios,
0768     .type       = pic32_uart_type,
0769     .release_port   = pic32_uart_release_port,
0770     .request_port   = pic32_uart_request_port,
0771     .config_port    = pic32_uart_config_port,
0772     .verify_port    = pic32_uart_verify_port,
0773 };
0774 
0775 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
0776 /* output given char */
0777 static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
0778 {
0779     struct pic32_sport *sport = to_pic32_sport(port);
0780 
0781     if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
0782         return;
0783 
0784     if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
0785         return;
0786 
0787     /* wait for tx empty */
0788     pic32_wait_deplete_txbuf(sport);
0789 
0790     pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
0791 }
0792 
0793 /* console core request to output given string */
0794 static void pic32_console_write(struct console *co, const char *s,
0795                 unsigned int count)
0796 {
0797     struct pic32_sport *sport = pic32_sports[co->index];
0798 
0799     /* call uart helper to deal with \r\n */
0800     uart_console_write(&sport->port, s, count, pic32_console_putchar);
0801 }
0802 
0803 /* console core request to setup given console, find matching uart
0804  * port and setup it.
0805  */
0806 static int pic32_console_setup(struct console *co, char *options)
0807 {
0808     struct pic32_sport *sport;
0809     int baud = 115200;
0810     int bits = 8;
0811     int parity = 'n';
0812     int flow = 'n';
0813     int ret = 0;
0814 
0815     if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
0816         return -ENODEV;
0817 
0818     sport = pic32_sports[co->index];
0819     if (!sport)
0820         return -ENODEV;
0821 
0822     ret = clk_prepare_enable(sport->clk);
0823     if (ret)
0824         return ret;
0825 
0826     if (options)
0827         uart_parse_options(options, &baud, &parity, &bits, &flow);
0828 
0829     return uart_set_options(&sport->port, co, baud, parity, bits, flow);
0830 }
0831 
0832 static struct uart_driver pic32_uart_driver;
0833 static struct console pic32_console = {
0834     .name       = PIC32_SDEV_NAME,
0835     .write      = pic32_console_write,
0836     .device     = uart_console_device,
0837     .setup      = pic32_console_setup,
0838     .flags      = CON_PRINTBUFFER,
0839     .index      = -1,
0840     .data       = &pic32_uart_driver,
0841 };
0842 #define PIC32_SCONSOLE (&pic32_console)
0843 
0844 static int __init pic32_console_init(void)
0845 {
0846     register_console(&pic32_console);
0847     return 0;
0848 }
0849 console_initcall(pic32_console_init);
0850 
0851 /*
0852  * Late console initialization.
0853  */
0854 static int __init pic32_late_console_init(void)
0855 {
0856     if (!(pic32_console.flags & CON_ENABLED))
0857         register_console(&pic32_console);
0858 
0859     return 0;
0860 }
0861 
0862 core_initcall(pic32_late_console_init);
0863 
0864 #else
0865 #define PIC32_SCONSOLE NULL
0866 #endif
0867 
0868 static struct uart_driver pic32_uart_driver = {
0869     .owner          = THIS_MODULE,
0870     .driver_name        = PIC32_DEV_NAME,
0871     .dev_name       = PIC32_SDEV_NAME,
0872     .nr         = PIC32_MAX_UARTS,
0873     .cons           = PIC32_SCONSOLE,
0874 };
0875 
0876 static int pic32_uart_probe(struct platform_device *pdev)
0877 {
0878     struct device_node *np = pdev->dev.of_node;
0879     struct pic32_sport *sport;
0880     int uart_idx = 0;
0881     struct resource *res_mem;
0882     struct uart_port *port;
0883     int ret;
0884 
0885     uart_idx = of_alias_get_id(np, "serial");
0886     if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
0887         return -EINVAL;
0888 
0889     res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0890     if (!res_mem)
0891         return -EINVAL;
0892 
0893     sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
0894     if (!sport)
0895         return -ENOMEM;
0896 
0897     sport->idx      = uart_idx;
0898     sport->irq_fault    = irq_of_parse_and_map(np, 0);
0899     sport->irq_rx       = irq_of_parse_and_map(np, 1);
0900     sport->irq_tx       = irq_of_parse_and_map(np, 2);
0901     sport->clk      = devm_clk_get(&pdev->dev, NULL);
0902     sport->dev      = &pdev->dev;
0903 
0904     /* Hardware flow control: gpios
0905      * !Note: Basically, CTS is needed for reading the status.
0906      */
0907     sport->hw_flow_ctrl = false;
0908     sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
0909     if (gpio_is_valid(sport->cts_gpio)) {
0910         sport->hw_flow_ctrl = true;
0911 
0912         ret = devm_gpio_request(sport->dev,
0913                     sport->cts_gpio, "CTS");
0914         if (ret) {
0915             dev_err(&pdev->dev,
0916                 "error requesting CTS GPIO\n");
0917             goto err;
0918         }
0919 
0920         ret = gpio_direction_input(sport->cts_gpio);
0921         if (ret) {
0922             dev_err(&pdev->dev, "error setting CTS GPIO\n");
0923             goto err;
0924         }
0925     }
0926 
0927     pic32_sports[uart_idx] = sport;
0928     port = &sport->port;
0929     port->iotype    = UPIO_MEM;
0930     port->mapbase   = res_mem->start;
0931     port->ops   = &pic32_uart_ops;
0932     port->flags = UPF_BOOT_AUTOCONF;
0933     port->dev   = &pdev->dev;
0934     port->fifosize  = PIC32_UART_TX_FIFO_DEPTH;
0935     port->uartclk   = clk_get_rate(sport->clk);
0936     port->line  = uart_idx;
0937 
0938     ret = uart_add_one_port(&pic32_uart_driver, port);
0939     if (ret) {
0940         port->membase = NULL;
0941         dev_err(port->dev, "%s: uart add port error!\n", __func__);
0942         goto err;
0943     }
0944 
0945 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
0946     if (uart_console(port) && (pic32_console.flags & CON_ENABLED)) {
0947         /* The peripheral clock has been enabled by console_setup,
0948          * so disable it till the port is used.
0949          */
0950         clk_disable_unprepare(sport->clk);
0951     }
0952 #endif
0953 
0954     platform_set_drvdata(pdev, port);
0955 
0956     dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
0957          __func__, uart_idx);
0958 
0959     return 0;
0960 err:
0961     /* automatic unroll of sport and gpios */
0962     return ret;
0963 }
0964 
0965 static int pic32_uart_remove(struct platform_device *pdev)
0966 {
0967     struct uart_port *port = platform_get_drvdata(pdev);
0968     struct pic32_sport *sport = to_pic32_sport(port);
0969 
0970     uart_remove_one_port(&pic32_uart_driver, port);
0971     clk_disable_unprepare(sport->clk);
0972     platform_set_drvdata(pdev, NULL);
0973     pic32_sports[sport->idx] = NULL;
0974 
0975     /* automatic unroll of sport and gpios */
0976     return 0;
0977 }
0978 
0979 static const struct of_device_id pic32_serial_dt_ids[] = {
0980     { .compatible = "microchip,pic32mzda-uart" },
0981     { /* sentinel */ }
0982 };
0983 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
0984 
0985 static struct platform_driver pic32_uart_platform_driver = {
0986     .probe      = pic32_uart_probe,
0987     .remove     = pic32_uart_remove,
0988     .driver     = {
0989         .name   = PIC32_DEV_NAME,
0990         .of_match_table = of_match_ptr(pic32_serial_dt_ids),
0991         .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
0992     },
0993 };
0994 
0995 static int __init pic32_uart_init(void)
0996 {
0997     int ret;
0998 
0999     ret = uart_register_driver(&pic32_uart_driver);
1000     if (ret) {
1001         pr_err("failed to register %s:%d\n",
1002                pic32_uart_driver.driver_name, ret);
1003         return ret;
1004     }
1005 
1006     ret = platform_driver_register(&pic32_uart_platform_driver);
1007     if (ret) {
1008         pr_err("fail to register pic32 uart\n");
1009         uart_unregister_driver(&pic32_uart_driver);
1010     }
1011 
1012     return ret;
1013 }
1014 arch_initcall(pic32_uart_init);
1015 
1016 static void __exit pic32_uart_exit(void)
1017 {
1018 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
1019     unregister_console(&pic32_console);
1020 #endif
1021     platform_driver_unregister(&pic32_uart_platform_driver);
1022     uart_unregister_driver(&pic32_uart_driver);
1023 }
1024 module_exit(pic32_uart_exit);
1025 
1026 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1027 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1028 MODULE_LICENSE("GPL v2");
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