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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
0004  */
0005 #include <linux/kernel.h>
0006 #include <linux/serial.h>
0007 #include <linux/serial_reg.h>
0008 #include <linux/slab.h>
0009 #include <linux/module.h>
0010 #include <linux/pci.h>
0011 #include <linux/console.h>
0012 #include <linux/serial_core.h>
0013 #include <linux/tty.h>
0014 #include <linux/tty_flip.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/dmi.h>
0018 #include <linux/nmi.h>
0019 #include <linux/delay.h>
0020 #include <linux/of.h>
0021 
0022 #include <linux/debugfs.h>
0023 #include <linux/dmaengine.h>
0024 #include <linux/pch_dma.h>
0025 
0026 enum {
0027     PCH_UART_HANDLED_RX_INT_SHIFT,
0028     PCH_UART_HANDLED_TX_INT_SHIFT,
0029     PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
0030     PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
0031     PCH_UART_HANDLED_MS_INT_SHIFT,
0032     PCH_UART_HANDLED_LS_INT_SHIFT,
0033 };
0034 
0035 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
0036 
0037 /* Set the max number of UART port
0038  * Intel EG20T PCH: 4 port
0039  * LAPIS Semiconductor ML7213 IOH: 3 port
0040  * LAPIS Semiconductor ML7223 IOH: 2 port
0041 */
0042 #define PCH_UART_NR 4
0043 
0044 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
0045 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
0046 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
0047                     PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
0048 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
0049                     PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
0050 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
0051 
0052 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
0053 
0054 #define PCH_UART_RBR        0x00
0055 #define PCH_UART_THR        0x00
0056 
0057 #define PCH_UART_IER_MASK   (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
0058                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
0059 #define PCH_UART_IER_ERBFI  0x00000001
0060 #define PCH_UART_IER_ETBEI  0x00000002
0061 #define PCH_UART_IER_ELSI   0x00000004
0062 #define PCH_UART_IER_EDSSI  0x00000008
0063 
0064 #define PCH_UART_IIR_IP         0x00000001
0065 #define PCH_UART_IIR_IID        0x00000006
0066 #define PCH_UART_IIR_MSI        0x00000000
0067 #define PCH_UART_IIR_TRI        0x00000002
0068 #define PCH_UART_IIR_RRI        0x00000004
0069 #define PCH_UART_IIR_REI        0x00000006
0070 #define PCH_UART_IIR_TOI        0x00000008
0071 #define PCH_UART_IIR_FIFO256        0x00000020
0072 #define PCH_UART_IIR_FIFO64     PCH_UART_IIR_FIFO256
0073 #define PCH_UART_IIR_FE         0x000000C0
0074 
0075 #define PCH_UART_FCR_FIFOE      0x00000001
0076 #define PCH_UART_FCR_RFR        0x00000002
0077 #define PCH_UART_FCR_TFR        0x00000004
0078 #define PCH_UART_FCR_DMS        0x00000008
0079 #define PCH_UART_FCR_FIFO256        0x00000020
0080 #define PCH_UART_FCR_RFTL       0x000000C0
0081 
0082 #define PCH_UART_FCR_RFTL1      0x00000000
0083 #define PCH_UART_FCR_RFTL64     0x00000040
0084 #define PCH_UART_FCR_RFTL128        0x00000080
0085 #define PCH_UART_FCR_RFTL224        0x000000C0
0086 #define PCH_UART_FCR_RFTL16     PCH_UART_FCR_RFTL64
0087 #define PCH_UART_FCR_RFTL32     PCH_UART_FCR_RFTL128
0088 #define PCH_UART_FCR_RFTL56     PCH_UART_FCR_RFTL224
0089 #define PCH_UART_FCR_RFTL4      PCH_UART_FCR_RFTL64
0090 #define PCH_UART_FCR_RFTL8      PCH_UART_FCR_RFTL128
0091 #define PCH_UART_FCR_RFTL14     PCH_UART_FCR_RFTL224
0092 #define PCH_UART_FCR_RFTL_SHIFT     6
0093 
0094 #define PCH_UART_LCR_WLS    0x00000003
0095 #define PCH_UART_LCR_STB    0x00000004
0096 #define PCH_UART_LCR_PEN    0x00000008
0097 #define PCH_UART_LCR_EPS    0x00000010
0098 #define PCH_UART_LCR_SP     0x00000020
0099 #define PCH_UART_LCR_SB     0x00000040
0100 #define PCH_UART_LCR_DLAB   0x00000080
0101 #define PCH_UART_LCR_NP     0x00000000
0102 #define PCH_UART_LCR_OP     PCH_UART_LCR_PEN
0103 #define PCH_UART_LCR_EP     (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
0104 #define PCH_UART_LCR_1P     (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
0105 #define PCH_UART_LCR_0P     (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
0106                 PCH_UART_LCR_SP)
0107 
0108 #define PCH_UART_LCR_5BIT   0x00000000
0109 #define PCH_UART_LCR_6BIT   0x00000001
0110 #define PCH_UART_LCR_7BIT   0x00000002
0111 #define PCH_UART_LCR_8BIT   0x00000003
0112 
0113 #define PCH_UART_MCR_DTR    0x00000001
0114 #define PCH_UART_MCR_RTS    0x00000002
0115 #define PCH_UART_MCR_OUT    0x0000000C
0116 #define PCH_UART_MCR_LOOP   0x00000010
0117 #define PCH_UART_MCR_AFE    0x00000020
0118 
0119 #define PCH_UART_LSR_DR     0x00000001
0120 #define PCH_UART_LSR_ERR    (1<<7)
0121 
0122 #define PCH_UART_MSR_DCTS   0x00000001
0123 #define PCH_UART_MSR_DDSR   0x00000002
0124 #define PCH_UART_MSR_TERI   0x00000004
0125 #define PCH_UART_MSR_DDCD   0x00000008
0126 #define PCH_UART_MSR_CTS    0x00000010
0127 #define PCH_UART_MSR_DSR    0x00000020
0128 #define PCH_UART_MSR_RI     0x00000040
0129 #define PCH_UART_MSR_DCD    0x00000080
0130 #define PCH_UART_MSR_DELTA  (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
0131                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
0132 
0133 #define PCH_UART_DLL        0x00
0134 #define PCH_UART_DLM        0x01
0135 
0136 #define PCH_UART_BRCSR      0x0E
0137 
0138 #define PCH_UART_IID_RLS    (PCH_UART_IIR_REI)
0139 #define PCH_UART_IID_RDR    (PCH_UART_IIR_RRI)
0140 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
0141 #define PCH_UART_IID_THRE   (PCH_UART_IIR_TRI)
0142 #define PCH_UART_IID_MS     (PCH_UART_IIR_MSI)
0143 
0144 #define PCH_UART_HAL_PARITY_NONE    (PCH_UART_LCR_NP)
0145 #define PCH_UART_HAL_PARITY_ODD     (PCH_UART_LCR_OP)
0146 #define PCH_UART_HAL_PARITY_EVEN    (PCH_UART_LCR_EP)
0147 #define PCH_UART_HAL_PARITY_FIX1    (PCH_UART_LCR_1P)
0148 #define PCH_UART_HAL_PARITY_FIX0    (PCH_UART_LCR_0P)
0149 #define PCH_UART_HAL_5BIT       (PCH_UART_LCR_5BIT)
0150 #define PCH_UART_HAL_6BIT       (PCH_UART_LCR_6BIT)
0151 #define PCH_UART_HAL_7BIT       (PCH_UART_LCR_7BIT)
0152 #define PCH_UART_HAL_8BIT       (PCH_UART_LCR_8BIT)
0153 #define PCH_UART_HAL_STB1       0
0154 #define PCH_UART_HAL_STB2       (PCH_UART_LCR_STB)
0155 
0156 #define PCH_UART_HAL_CLR_TX_FIFO    (PCH_UART_FCR_TFR)
0157 #define PCH_UART_HAL_CLR_RX_FIFO    (PCH_UART_FCR_RFR)
0158 #define PCH_UART_HAL_CLR_ALL_FIFO   (PCH_UART_HAL_CLR_TX_FIFO | \
0159                     PCH_UART_HAL_CLR_RX_FIFO)
0160 
0161 #define PCH_UART_HAL_DMA_MODE0      0
0162 #define PCH_UART_HAL_FIFO_DIS       0
0163 #define PCH_UART_HAL_FIFO16     (PCH_UART_FCR_FIFOE)
0164 #define PCH_UART_HAL_FIFO256        (PCH_UART_FCR_FIFOE | \
0165                     PCH_UART_FCR_FIFO256)
0166 #define PCH_UART_HAL_FIFO64     (PCH_UART_HAL_FIFO256)
0167 #define PCH_UART_HAL_TRIGGER1       (PCH_UART_FCR_RFTL1)
0168 #define PCH_UART_HAL_TRIGGER64      (PCH_UART_FCR_RFTL64)
0169 #define PCH_UART_HAL_TRIGGER128     (PCH_UART_FCR_RFTL128)
0170 #define PCH_UART_HAL_TRIGGER224     (PCH_UART_FCR_RFTL224)
0171 #define PCH_UART_HAL_TRIGGER16      (PCH_UART_FCR_RFTL16)
0172 #define PCH_UART_HAL_TRIGGER32      (PCH_UART_FCR_RFTL32)
0173 #define PCH_UART_HAL_TRIGGER56      (PCH_UART_FCR_RFTL56)
0174 #define PCH_UART_HAL_TRIGGER4       (PCH_UART_FCR_RFTL4)
0175 #define PCH_UART_HAL_TRIGGER8       (PCH_UART_FCR_RFTL8)
0176 #define PCH_UART_HAL_TRIGGER14      (PCH_UART_FCR_RFTL14)
0177 #define PCH_UART_HAL_TRIGGER_L      (PCH_UART_FCR_RFTL64)
0178 #define PCH_UART_HAL_TRIGGER_M      (PCH_UART_FCR_RFTL128)
0179 #define PCH_UART_HAL_TRIGGER_H      (PCH_UART_FCR_RFTL224)
0180 
0181 #define PCH_UART_HAL_RX_INT     (PCH_UART_IER_ERBFI)
0182 #define PCH_UART_HAL_TX_INT     (PCH_UART_IER_ETBEI)
0183 #define PCH_UART_HAL_RX_ERR_INT     (PCH_UART_IER_ELSI)
0184 #define PCH_UART_HAL_MS_INT     (PCH_UART_IER_EDSSI)
0185 #define PCH_UART_HAL_ALL_INT        (PCH_UART_IER_MASK)
0186 
0187 #define PCH_UART_HAL_DTR        (PCH_UART_MCR_DTR)
0188 #define PCH_UART_HAL_RTS        (PCH_UART_MCR_RTS)
0189 #define PCH_UART_HAL_OUT        (PCH_UART_MCR_OUT)
0190 #define PCH_UART_HAL_LOOP       (PCH_UART_MCR_LOOP)
0191 #define PCH_UART_HAL_AFE        (PCH_UART_MCR_AFE)
0192 
0193 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
0194 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
0195 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
0196 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
0197 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
0198 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
0199 
0200 struct pch_uart_buffer {
0201     unsigned char *buf;
0202     int size;
0203 };
0204 
0205 struct eg20t_port {
0206     struct uart_port port;
0207     int port_type;
0208     void __iomem *membase;
0209     resource_size_t mapbase;
0210     unsigned int iobase;
0211     struct pci_dev *pdev;
0212     int fifo_size;
0213     unsigned int uartclk;
0214     int start_tx;
0215     int start_rx;
0216     int tx_empty;
0217     int trigger;
0218     int trigger_level;
0219     struct pch_uart_buffer rxbuf;
0220     unsigned int dmsr;
0221     unsigned int fcr;
0222     unsigned int mcr;
0223     unsigned int use_dma;
0224     struct dma_async_tx_descriptor  *desc_tx;
0225     struct dma_async_tx_descriptor  *desc_rx;
0226     struct pch_dma_slave        param_tx;
0227     struct pch_dma_slave        param_rx;
0228     struct dma_chan         *chan_tx;
0229     struct dma_chan         *chan_rx;
0230     struct scatterlist      *sg_tx_p;
0231     int             nent;
0232     int             orig_nent;
0233     struct scatterlist      sg_rx;
0234     int             tx_dma_use;
0235     void                *rx_buf_virt;
0236     dma_addr_t          rx_buf_dma;
0237 
0238 #define IRQ_NAME_SIZE 17
0239     char                irq_name[IRQ_NAME_SIZE];
0240 
0241     /* protect the eg20t_port private structure and io access to membase */
0242     spinlock_t lock;
0243 };
0244 
0245 /**
0246  * struct pch_uart_driver_data - private data structure for UART-DMA
0247  * @port_type:          The type of UART port
0248  * @line_no:            UART port line number (0, 1, 2...)
0249  */
0250 struct pch_uart_driver_data {
0251     int port_type;
0252     int line_no;
0253 };
0254 
0255 enum pch_uart_num_t {
0256     pch_et20t_uart0 = 0,
0257     pch_et20t_uart1,
0258     pch_et20t_uart2,
0259     pch_et20t_uart3,
0260     pch_ml7213_uart0,
0261     pch_ml7213_uart1,
0262     pch_ml7213_uart2,
0263     pch_ml7223_uart0,
0264     pch_ml7223_uart1,
0265     pch_ml7831_uart0,
0266     pch_ml7831_uart1,
0267 };
0268 
0269 static struct pch_uart_driver_data drv_dat[] = {
0270     [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
0271     [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
0272     [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
0273     [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
0274     [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
0275     [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
0276     [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
0277     [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
0278     [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
0279     [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
0280     [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
0281 };
0282 
0283 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
0284 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
0285 #endif
0286 static unsigned int default_baud = 9600;
0287 static unsigned int user_uartclk = 0;
0288 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
0289 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
0290 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
0291 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
0292 
0293 #define PCH_REGS_BUFSIZE    1024
0294 
0295 
0296 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
0297                 size_t count, loff_t *ppos)
0298 {
0299     struct eg20t_port *priv = file->private_data;
0300     char *buf;
0301     u32 len = 0;
0302     ssize_t ret;
0303     unsigned char lcr;
0304 
0305     buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
0306     if (!buf)
0307         return 0;
0308 
0309     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0310             "PCH EG20T port[%d] regs:\n", priv->port.line);
0311 
0312     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0313             "=================================\n");
0314     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0315             "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
0316     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0317             "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
0318     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0319             "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
0320     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0321             "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
0322     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0323             "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
0324     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0325             "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
0326     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0327             "BRCSR: \t0x%02x\n",
0328             ioread8(priv->membase + PCH_UART_BRCSR));
0329 
0330     lcr = ioread8(priv->membase + UART_LCR);
0331     iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
0332     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0333             "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
0334     len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
0335             "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
0336     iowrite8(lcr, priv->membase + UART_LCR);
0337 
0338     if (len > PCH_REGS_BUFSIZE)
0339         len = PCH_REGS_BUFSIZE;
0340 
0341     ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
0342     kfree(buf);
0343     return ret;
0344 }
0345 
0346 static const struct file_operations port_regs_ops = {
0347     .owner      = THIS_MODULE,
0348     .open       = simple_open,
0349     .read       = port_show_regs,
0350     .llseek     = default_llseek,
0351 };
0352 
0353 static const struct dmi_system_id pch_uart_dmi_table[] = {
0354     {
0355         .ident = "CM-iTC",
0356         {
0357             DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
0358         },
0359         (void *)CMITC_UARTCLK,
0360     },
0361     {
0362         .ident = "FRI2",
0363         {
0364             DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
0365         },
0366         (void *)FRI2_64_UARTCLK,
0367     },
0368     {
0369         .ident = "Fish River Island II",
0370         {
0371             DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
0372         },
0373         (void *)FRI2_48_UARTCLK,
0374     },
0375     {
0376         .ident = "COMe-mTT",
0377         {
0378             DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
0379         },
0380         (void *)NTC1_UARTCLK,
0381     },
0382     {
0383         .ident = "nanoETXexpress-TT",
0384         {
0385             DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
0386         },
0387         (void *)NTC1_UARTCLK,
0388     },
0389     {
0390         .ident = "MinnowBoard",
0391         {
0392             DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
0393         },
0394         (void *)MINNOW_UARTCLK,
0395     },
0396     { }
0397 };
0398 
0399 /* Return UART clock, checking for board specific clocks. */
0400 static unsigned int pch_uart_get_uartclk(void)
0401 {
0402     const struct dmi_system_id *d;
0403 
0404     if (user_uartclk)
0405         return user_uartclk;
0406 
0407     d = dmi_first_match(pch_uart_dmi_table);
0408     if (d)
0409         return (unsigned long)d->driver_data;
0410 
0411     return DEFAULT_UARTCLK;
0412 }
0413 
0414 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
0415                       unsigned int flag)
0416 {
0417     u8 ier = ioread8(priv->membase + UART_IER);
0418     ier |= flag & PCH_UART_IER_MASK;
0419     iowrite8(ier, priv->membase + UART_IER);
0420 }
0421 
0422 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
0423                        unsigned int flag)
0424 {
0425     u8 ier = ioread8(priv->membase + UART_IER);
0426     ier &= ~(flag & PCH_UART_IER_MASK);
0427     iowrite8(ier, priv->membase + UART_IER);
0428 }
0429 
0430 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
0431                  unsigned int parity, unsigned int bits,
0432                  unsigned int stb)
0433 {
0434     unsigned int dll, dlm, lcr;
0435     int div;
0436 
0437     div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
0438     if (div < 0 || USHRT_MAX <= div) {
0439         dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
0440         return -EINVAL;
0441     }
0442 
0443     dll = (unsigned int)div & 0x00FFU;
0444     dlm = ((unsigned int)div >> 8) & 0x00FFU;
0445 
0446     if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
0447         dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
0448         return -EINVAL;
0449     }
0450 
0451     if (bits & ~PCH_UART_LCR_WLS) {
0452         dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
0453         return -EINVAL;
0454     }
0455 
0456     if (stb & ~PCH_UART_LCR_STB) {
0457         dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
0458         return -EINVAL;
0459     }
0460 
0461     lcr = parity;
0462     lcr |= bits;
0463     lcr |= stb;
0464 
0465     dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
0466          __func__, baud, div, lcr, jiffies);
0467     iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
0468     iowrite8(dll, priv->membase + PCH_UART_DLL);
0469     iowrite8(dlm, priv->membase + PCH_UART_DLM);
0470     iowrite8(lcr, priv->membase + UART_LCR);
0471 
0472     return 0;
0473 }
0474 
0475 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
0476                     unsigned int flag)
0477 {
0478     if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
0479         dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
0480             __func__, flag);
0481         return -EINVAL;
0482     }
0483 
0484     iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
0485     iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
0486          priv->membase + UART_FCR);
0487     iowrite8(priv->fcr, priv->membase + UART_FCR);
0488 
0489     return 0;
0490 }
0491 
0492 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
0493                  unsigned int dmamode,
0494                  unsigned int fifo_size, unsigned int trigger)
0495 {
0496     u8 fcr;
0497 
0498     if (dmamode & ~PCH_UART_FCR_DMS) {
0499         dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
0500             __func__, dmamode);
0501         return -EINVAL;
0502     }
0503 
0504     if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
0505         dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
0506             __func__, fifo_size);
0507         return -EINVAL;
0508     }
0509 
0510     if (trigger & ~PCH_UART_FCR_RFTL) {
0511         dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
0512             __func__, trigger);
0513         return -EINVAL;
0514     }
0515 
0516     switch (priv->fifo_size) {
0517     case 256:
0518         priv->trigger_level =
0519             trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
0520         break;
0521     case 64:
0522         priv->trigger_level =
0523             trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
0524         break;
0525     case 16:
0526         priv->trigger_level =
0527             trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
0528         break;
0529     default:
0530         priv->trigger_level =
0531             trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
0532         break;
0533     }
0534     fcr =
0535         dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
0536     iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
0537     iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
0538          priv->membase + UART_FCR);
0539     iowrite8(fcr, priv->membase + UART_FCR);
0540     priv->fcr = fcr;
0541 
0542     return 0;
0543 }
0544 
0545 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
0546 {
0547     unsigned int msr = ioread8(priv->membase + UART_MSR);
0548     priv->dmsr = msr & PCH_UART_MSR_DELTA;
0549     return (u8)msr;
0550 }
0551 
0552 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
0553                  int rx_size)
0554 {
0555     int i;
0556     u8 rbr, lsr;
0557     struct uart_port *port = &priv->port;
0558 
0559     lsr = ioread8(priv->membase + UART_LSR);
0560     for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
0561          i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
0562          lsr = ioread8(priv->membase + UART_LSR)) {
0563         rbr = ioread8(priv->membase + PCH_UART_RBR);
0564 
0565         if (lsr & UART_LSR_BI) {
0566             port->icount.brk++;
0567             if (uart_handle_break(port))
0568                 continue;
0569         }
0570         if (uart_handle_sysrq_char(port, rbr))
0571             continue;
0572 
0573         buf[i++] = rbr;
0574     }
0575     return i;
0576 }
0577 
0578 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
0579 {
0580     return ioread8(priv->membase + UART_IIR) &\
0581               (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
0582 }
0583 
0584 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
0585 {
0586     return ioread8(priv->membase + UART_LSR);
0587 }
0588 
0589 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
0590 {
0591     unsigned int lcr;
0592 
0593     lcr = ioread8(priv->membase + UART_LCR);
0594     if (on)
0595         lcr |= PCH_UART_LCR_SB;
0596     else
0597         lcr &= ~PCH_UART_LCR_SB;
0598 
0599     iowrite8(lcr, priv->membase + UART_LCR);
0600 }
0601 
0602 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
0603            int size)
0604 {
0605     struct uart_port *port = &priv->port;
0606     struct tty_port *tport = &port->state->port;
0607 
0608     tty_insert_flip_string(tport, buf, size);
0609     tty_flip_buffer_push(tport);
0610 
0611     return 0;
0612 }
0613 
0614 static int dma_push_rx(struct eg20t_port *priv, int size)
0615 {
0616     int room;
0617     struct uart_port *port = &priv->port;
0618     struct tty_port *tport = &port->state->port;
0619 
0620     room = tty_buffer_request_room(tport, size);
0621 
0622     if (room < size)
0623         dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
0624              size - room);
0625     if (!room)
0626         return 0;
0627 
0628     tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
0629 
0630     port->icount.rx += room;
0631 
0632     return room;
0633 }
0634 
0635 static void pch_free_dma(struct uart_port *port)
0636 {
0637     struct eg20t_port *priv;
0638     priv = container_of(port, struct eg20t_port, port);
0639 
0640     if (priv->chan_tx) {
0641         dma_release_channel(priv->chan_tx);
0642         priv->chan_tx = NULL;
0643     }
0644     if (priv->chan_rx) {
0645         dma_release_channel(priv->chan_rx);
0646         priv->chan_rx = NULL;
0647     }
0648 
0649     if (priv->rx_buf_dma) {
0650         dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
0651                   priv->rx_buf_dma);
0652         priv->rx_buf_virt = NULL;
0653         priv->rx_buf_dma = 0;
0654     }
0655 
0656     return;
0657 }
0658 
0659 static bool filter(struct dma_chan *chan, void *slave)
0660 {
0661     struct pch_dma_slave *param = slave;
0662 
0663     if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
0664                           chan->device->dev)) {
0665         chan->private = param;
0666         return true;
0667     } else {
0668         return false;
0669     }
0670 }
0671 
0672 static void pch_request_dma(struct uart_port *port)
0673 {
0674     dma_cap_mask_t mask;
0675     struct dma_chan *chan;
0676     struct pci_dev *dma_dev;
0677     struct pch_dma_slave *param;
0678     struct eg20t_port *priv =
0679                 container_of(port, struct eg20t_port, port);
0680     dma_cap_zero(mask);
0681     dma_cap_set(DMA_SLAVE, mask);
0682 
0683     /* Get DMA's dev information */
0684     dma_dev = pci_get_slot(priv->pdev->bus,
0685             PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
0686 
0687     /* Set Tx DMA */
0688     param = &priv->param_tx;
0689     param->dma_dev = &dma_dev->dev;
0690     param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
0691 
0692     param->tx_reg = port->mapbase + UART_TX;
0693     chan = dma_request_channel(mask, filter, param);
0694     if (!chan) {
0695         dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
0696             __func__);
0697         return;
0698     }
0699     priv->chan_tx = chan;
0700 
0701     /* Set Rx DMA */
0702     param = &priv->param_rx;
0703     param->dma_dev = &dma_dev->dev;
0704     param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
0705 
0706     param->rx_reg = port->mapbase + UART_RX;
0707     chan = dma_request_channel(mask, filter, param);
0708     if (!chan) {
0709         dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
0710             __func__);
0711         dma_release_channel(priv->chan_tx);
0712         priv->chan_tx = NULL;
0713         return;
0714     }
0715 
0716     /* Get Consistent memory for DMA */
0717     priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
0718                     &priv->rx_buf_dma, GFP_KERNEL);
0719     priv->chan_rx = chan;
0720 }
0721 
0722 static void pch_dma_rx_complete(void *arg)
0723 {
0724     struct eg20t_port *priv = arg;
0725     struct uart_port *port = &priv->port;
0726     int count;
0727 
0728     dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
0729     count = dma_push_rx(priv, priv->trigger_level);
0730     if (count)
0731         tty_flip_buffer_push(&port->state->port);
0732     async_tx_ack(priv->desc_rx);
0733     pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
0734                         PCH_UART_HAL_RX_ERR_INT);
0735 }
0736 
0737 static void pch_dma_tx_complete(void *arg)
0738 {
0739     struct eg20t_port *priv = arg;
0740     struct uart_port *port = &priv->port;
0741     struct circ_buf *xmit = &port->state->xmit;
0742     struct scatterlist *sg = priv->sg_tx_p;
0743     int i;
0744 
0745     for (i = 0; i < priv->nent; i++, sg++) {
0746         xmit->tail += sg_dma_len(sg);
0747         port->icount.tx += sg_dma_len(sg);
0748     }
0749     xmit->tail &= UART_XMIT_SIZE - 1;
0750     async_tx_ack(priv->desc_tx);
0751     dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
0752     priv->tx_dma_use = 0;
0753     priv->nent = 0;
0754     priv->orig_nent = 0;
0755     kfree(priv->sg_tx_p);
0756     pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
0757 }
0758 
0759 static int handle_rx_to(struct eg20t_port *priv)
0760 {
0761     struct pch_uart_buffer *buf;
0762     int rx_size;
0763     int ret;
0764     if (!priv->start_rx) {
0765         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
0766                              PCH_UART_HAL_RX_ERR_INT);
0767         return 0;
0768     }
0769     buf = &priv->rxbuf;
0770     do {
0771         rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
0772         ret = push_rx(priv, buf->buf, rx_size);
0773         if (ret)
0774             return 0;
0775     } while (rx_size == buf->size);
0776 
0777     return PCH_UART_HANDLED_RX_INT;
0778 }
0779 
0780 static int handle_rx(struct eg20t_port *priv)
0781 {
0782     return handle_rx_to(priv);
0783 }
0784 
0785 static int dma_handle_rx(struct eg20t_port *priv)
0786 {
0787     struct uart_port *port = &priv->port;
0788     struct dma_async_tx_descriptor *desc;
0789     struct scatterlist *sg;
0790 
0791     priv = container_of(port, struct eg20t_port, port);
0792     sg = &priv->sg_rx;
0793 
0794     sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
0795 
0796     sg_dma_len(sg) = priv->trigger_level;
0797 
0798     sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
0799              sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
0800 
0801     sg_dma_address(sg) = priv->rx_buf_dma;
0802 
0803     desc = dmaengine_prep_slave_sg(priv->chan_rx,
0804             sg, 1, DMA_DEV_TO_MEM,
0805             DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0806 
0807     if (!desc)
0808         return 0;
0809 
0810     priv->desc_rx = desc;
0811     desc->callback = pch_dma_rx_complete;
0812     desc->callback_param = priv;
0813     desc->tx_submit(desc);
0814     dma_async_issue_pending(priv->chan_rx);
0815 
0816     return PCH_UART_HANDLED_RX_INT;
0817 }
0818 
0819 static unsigned int handle_tx(struct eg20t_port *priv)
0820 {
0821     struct uart_port *port = &priv->port;
0822     struct circ_buf *xmit = &port->state->xmit;
0823     int fifo_size;
0824     int tx_empty;
0825 
0826     if (!priv->start_tx) {
0827         dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
0828             __func__, jiffies);
0829         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
0830         priv->tx_empty = 1;
0831         return 0;
0832     }
0833 
0834     fifo_size = max(priv->fifo_size, 1);
0835     tx_empty = 1;
0836     if (port->x_char) {
0837         iowrite8(port->x_char, priv->membase + PCH_UART_THR);
0838         port->icount.tx++;
0839         port->x_char = 0;
0840         tx_empty = 0;
0841         fifo_size--;
0842     }
0843 
0844     while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
0845         iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
0846         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0847         port->icount.tx++;
0848         fifo_size--;
0849         tx_empty = 0;
0850     }
0851 
0852     priv->tx_empty = tx_empty;
0853 
0854     if (tx_empty) {
0855         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
0856         uart_write_wakeup(port);
0857     }
0858 
0859     return PCH_UART_HANDLED_TX_INT;
0860 }
0861 
0862 static unsigned int dma_handle_tx(struct eg20t_port *priv)
0863 {
0864     struct uart_port *port = &priv->port;
0865     struct circ_buf *xmit = &port->state->xmit;
0866     struct scatterlist *sg;
0867     int nent;
0868     int fifo_size;
0869     struct dma_async_tx_descriptor *desc;
0870     int num;
0871     int i;
0872     int bytes;
0873     int size;
0874     int rem;
0875 
0876     if (!priv->start_tx) {
0877         dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
0878             __func__, jiffies);
0879         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
0880         priv->tx_empty = 1;
0881         return 0;
0882     }
0883 
0884     if (priv->tx_dma_use) {
0885         dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
0886             __func__, jiffies);
0887         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
0888         priv->tx_empty = 1;
0889         return 0;
0890     }
0891 
0892     fifo_size = max(priv->fifo_size, 1);
0893 
0894     if (port->x_char) {
0895         iowrite8(port->x_char, priv->membase + PCH_UART_THR);
0896         port->icount.tx++;
0897         port->x_char = 0;
0898         fifo_size--;
0899     }
0900 
0901     bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
0902                  UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
0903                  xmit->tail, UART_XMIT_SIZE));
0904     if (!bytes) {
0905         dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
0906         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
0907         uart_write_wakeup(port);
0908         return 0;
0909     }
0910 
0911     if (bytes > fifo_size) {
0912         num = bytes / fifo_size + 1;
0913         size = fifo_size;
0914         rem = bytes % fifo_size;
0915     } else {
0916         num = 1;
0917         size = bytes;
0918         rem = bytes;
0919     }
0920 
0921     dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
0922         __func__, num, size, rem);
0923 
0924     priv->tx_dma_use = 1;
0925 
0926     priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
0927     if (!priv->sg_tx_p) {
0928         dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
0929         return 0;
0930     }
0931 
0932     sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
0933     sg = priv->sg_tx_p;
0934 
0935     for (i = 0; i < num; i++, sg++) {
0936         if (i == (num - 1))
0937             sg_set_page(sg, virt_to_page(xmit->buf),
0938                     rem, fifo_size * i);
0939         else
0940             sg_set_page(sg, virt_to_page(xmit->buf),
0941                     size, fifo_size * i);
0942     }
0943 
0944     sg = priv->sg_tx_p;
0945     nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
0946     if (!nent) {
0947         dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
0948         return 0;
0949     }
0950     priv->orig_nent = num;
0951     priv->nent = nent;
0952 
0953     for (i = 0; i < nent; i++, sg++) {
0954         sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
0955                   fifo_size * i;
0956         sg_dma_address(sg) = (sg_dma_address(sg) &
0957                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
0958         if (i == (nent - 1))
0959             sg_dma_len(sg) = rem;
0960         else
0961             sg_dma_len(sg) = size;
0962     }
0963 
0964     desc = dmaengine_prep_slave_sg(priv->chan_tx,
0965                     priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
0966                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0967     if (!desc) {
0968         dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
0969             __func__);
0970         return 0;
0971     }
0972     dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
0973     priv->desc_tx = desc;
0974     desc->callback = pch_dma_tx_complete;
0975     desc->callback_param = priv;
0976 
0977     desc->tx_submit(desc);
0978 
0979     dma_async_issue_pending(priv->chan_tx);
0980 
0981     return PCH_UART_HANDLED_TX_INT;
0982 }
0983 
0984 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
0985 {
0986     struct uart_port *port = &priv->port;
0987     struct tty_struct *tty = tty_port_tty_get(&port->state->port);
0988     char   *error_msg[5] = {};
0989     int    i = 0;
0990 
0991     if (lsr & PCH_UART_LSR_ERR)
0992         error_msg[i++] = "Error data in FIFO\n";
0993 
0994     if (lsr & UART_LSR_FE) {
0995         port->icount.frame++;
0996         error_msg[i++] = "  Framing Error\n";
0997     }
0998 
0999     if (lsr & UART_LSR_PE) {
1000         port->icount.parity++;
1001         error_msg[i++] = "  Parity Error\n";
1002     }
1003 
1004     if (lsr & UART_LSR_OE) {
1005         port->icount.overrun++;
1006         error_msg[i++] = "  Overrun Error\n";
1007     }
1008 
1009     if (tty == NULL) {
1010         for (i = 0; error_msg[i] != NULL; i++)
1011             dev_err(&priv->pdev->dev, error_msg[i]);
1012     } else {
1013         tty_kref_put(tty);
1014     }
1015 }
1016 
1017 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1018 {
1019     struct eg20t_port *priv = dev_id;
1020     unsigned int handled;
1021     u8 lsr;
1022     int ret = 0;
1023     unsigned char iid;
1024     unsigned long flags;
1025     int next = 1;
1026     u8 msr;
1027 
1028     spin_lock_irqsave(&priv->lock, flags);
1029     handled = 0;
1030     while (next) {
1031         iid = pch_uart_hal_get_iid(priv);
1032         if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1033             break;
1034         switch (iid) {
1035         case PCH_UART_IID_RLS:  /* Receiver Line Status */
1036             lsr = pch_uart_hal_get_line_status(priv);
1037             if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1038                         UART_LSR_PE | UART_LSR_OE)) {
1039                 pch_uart_err_ir(priv, lsr);
1040                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1041             } else {
1042                 ret = PCH_UART_HANDLED_LS_INT;
1043             }
1044             break;
1045         case PCH_UART_IID_RDR:  /* Received Data Ready */
1046             if (priv->use_dma) {
1047                 pch_uart_hal_disable_interrupt(priv,
1048                         PCH_UART_HAL_RX_INT |
1049                         PCH_UART_HAL_RX_ERR_INT);
1050                 ret = dma_handle_rx(priv);
1051                 if (!ret)
1052                     pch_uart_hal_enable_interrupt(priv,
1053                         PCH_UART_HAL_RX_INT |
1054                         PCH_UART_HAL_RX_ERR_INT);
1055             } else {
1056                 ret = handle_rx(priv);
1057             }
1058             break;
1059         case PCH_UART_IID_RDR_TO:   /* Received Data Ready
1060                            (FIFO Timeout) */
1061             ret = handle_rx_to(priv);
1062             break;
1063         case PCH_UART_IID_THRE: /* Transmitter Holding Register
1064                            Empty */
1065             if (priv->use_dma)
1066                 ret = dma_handle_tx(priv);
1067             else
1068                 ret = handle_tx(priv);
1069             break;
1070         case PCH_UART_IID_MS:   /* Modem Status */
1071             msr = pch_uart_hal_get_modem(priv);
1072             next = 0; /* MS ir prioirty is the lowest. So, MS ir
1073                      means final interrupt */
1074             if ((msr & UART_MSR_ANY_DELTA) == 0)
1075                 break;
1076             ret |= PCH_UART_HANDLED_MS_INT;
1077             break;
1078         default:    /* Never junp to this label */
1079             dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1080                 iid, jiffies);
1081             ret = -1;
1082             next = 0;
1083             break;
1084         }
1085         handled |= (unsigned int)ret;
1086     }
1087 
1088     spin_unlock_irqrestore(&priv->lock, flags);
1089     return IRQ_RETVAL(handled);
1090 }
1091 
1092 /* This function tests whether the transmitter fifo and shifter for the port
1093                         described by 'port' is empty. */
1094 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1095 {
1096     struct eg20t_port *priv;
1097 
1098     priv = container_of(port, struct eg20t_port, port);
1099     if (priv->tx_empty)
1100         return TIOCSER_TEMT;
1101     else
1102         return 0;
1103 }
1104 
1105 /* Returns the current state of modem control inputs. */
1106 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1107 {
1108     struct eg20t_port *priv;
1109     u8 modem;
1110     unsigned int ret = 0;
1111 
1112     priv = container_of(port, struct eg20t_port, port);
1113     modem = pch_uart_hal_get_modem(priv);
1114 
1115     if (modem & UART_MSR_DCD)
1116         ret |= TIOCM_CAR;
1117 
1118     if (modem & UART_MSR_RI)
1119         ret |= TIOCM_RNG;
1120 
1121     if (modem & UART_MSR_DSR)
1122         ret |= TIOCM_DSR;
1123 
1124     if (modem & UART_MSR_CTS)
1125         ret |= TIOCM_CTS;
1126 
1127     return ret;
1128 }
1129 
1130 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1131 {
1132     u32 mcr = 0;
1133     struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1134 
1135     if (mctrl & TIOCM_DTR)
1136         mcr |= UART_MCR_DTR;
1137     if (mctrl & TIOCM_RTS)
1138         mcr |= UART_MCR_RTS;
1139     if (mctrl & TIOCM_LOOP)
1140         mcr |= UART_MCR_LOOP;
1141 
1142     if (priv->mcr & UART_MCR_AFE)
1143         mcr |= UART_MCR_AFE;
1144 
1145     if (mctrl)
1146         iowrite8(mcr, priv->membase + UART_MCR);
1147 }
1148 
1149 static void pch_uart_stop_tx(struct uart_port *port)
1150 {
1151     struct eg20t_port *priv;
1152     priv = container_of(port, struct eg20t_port, port);
1153     priv->start_tx = 0;
1154     priv->tx_dma_use = 0;
1155 }
1156 
1157 static void pch_uart_start_tx(struct uart_port *port)
1158 {
1159     struct eg20t_port *priv;
1160 
1161     priv = container_of(port, struct eg20t_port, port);
1162 
1163     if (priv->use_dma) {
1164         if (priv->tx_dma_use) {
1165             dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1166                 __func__);
1167             return;
1168         }
1169     }
1170 
1171     priv->start_tx = 1;
1172     pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1173 }
1174 
1175 static void pch_uart_stop_rx(struct uart_port *port)
1176 {
1177     struct eg20t_port *priv;
1178     priv = container_of(port, struct eg20t_port, port);
1179     priv->start_rx = 0;
1180     pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1181                          PCH_UART_HAL_RX_ERR_INT);
1182 }
1183 
1184 /* Enable the modem status interrupts. */
1185 static void pch_uart_enable_ms(struct uart_port *port)
1186 {
1187     struct eg20t_port *priv;
1188     priv = container_of(port, struct eg20t_port, port);
1189     pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1190 }
1191 
1192 /* Control the transmission of a break signal. */
1193 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1194 {
1195     struct eg20t_port *priv;
1196     unsigned long flags;
1197 
1198     priv = container_of(port, struct eg20t_port, port);
1199     spin_lock_irqsave(&priv->lock, flags);
1200     pch_uart_hal_set_break(priv, ctl);
1201     spin_unlock_irqrestore(&priv->lock, flags);
1202 }
1203 
1204 /* Grab any interrupt resources and initialise any low level driver state. */
1205 static int pch_uart_startup(struct uart_port *port)
1206 {
1207     struct eg20t_port *priv;
1208     int ret;
1209     int fifo_size;
1210     int trigger_level;
1211 
1212     priv = container_of(port, struct eg20t_port, port);
1213     priv->tx_empty = 1;
1214 
1215     if (port->uartclk)
1216         priv->uartclk = port->uartclk;
1217     else
1218         port->uartclk = priv->uartclk;
1219 
1220     pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1221     ret = pch_uart_hal_set_line(priv, default_baud,
1222                   PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1223                   PCH_UART_HAL_STB1);
1224     if (ret)
1225         return ret;
1226 
1227     switch (priv->fifo_size) {
1228     case 256:
1229         fifo_size = PCH_UART_HAL_FIFO256;
1230         break;
1231     case 64:
1232         fifo_size = PCH_UART_HAL_FIFO64;
1233         break;
1234     case 16:
1235         fifo_size = PCH_UART_HAL_FIFO16;
1236         break;
1237     case 1:
1238     default:
1239         fifo_size = PCH_UART_HAL_FIFO_DIS;
1240         break;
1241     }
1242 
1243     switch (priv->trigger) {
1244     case PCH_UART_HAL_TRIGGER1:
1245         trigger_level = 1;
1246         break;
1247     case PCH_UART_HAL_TRIGGER_L:
1248         trigger_level = priv->fifo_size / 4;
1249         break;
1250     case PCH_UART_HAL_TRIGGER_M:
1251         trigger_level = priv->fifo_size / 2;
1252         break;
1253     case PCH_UART_HAL_TRIGGER_H:
1254     default:
1255         trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1256         break;
1257     }
1258 
1259     priv->trigger_level = trigger_level;
1260     ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1261                     fifo_size, priv->trigger);
1262     if (ret < 0)
1263         return ret;
1264 
1265     ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1266             priv->irq_name, priv);
1267     if (ret < 0)
1268         return ret;
1269 
1270     if (priv->use_dma)
1271         pch_request_dma(port);
1272 
1273     priv->start_rx = 1;
1274     pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1275                         PCH_UART_HAL_RX_ERR_INT);
1276     uart_update_timeout(port, CS8, default_baud);
1277 
1278     return 0;
1279 }
1280 
1281 static void pch_uart_shutdown(struct uart_port *port)
1282 {
1283     struct eg20t_port *priv;
1284     int ret;
1285 
1286     priv = container_of(port, struct eg20t_port, port);
1287     pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1288     pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1289     ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1290                   PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1291     if (ret)
1292         dev_err(priv->port.dev,
1293             "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1294 
1295     pch_free_dma(port);
1296 
1297     free_irq(priv->port.irq, priv);
1298 }
1299 
1300 /* Change the port parameters, including word length, parity, stop
1301  *bits.  Update read_status_mask and ignore_status_mask to indicate
1302  *the types of events we are interested in receiving.  */
1303 static void pch_uart_set_termios(struct uart_port *port,
1304                  struct ktermios *termios, struct ktermios *old)
1305 {
1306     int rtn;
1307     unsigned int baud, parity, bits, stb;
1308     struct eg20t_port *priv;
1309     unsigned long flags;
1310 
1311     priv = container_of(port, struct eg20t_port, port);
1312     switch (termios->c_cflag & CSIZE) {
1313     case CS5:
1314         bits = PCH_UART_HAL_5BIT;
1315         break;
1316     case CS6:
1317         bits = PCH_UART_HAL_6BIT;
1318         break;
1319     case CS7:
1320         bits = PCH_UART_HAL_7BIT;
1321         break;
1322     default:        /* CS8 */
1323         bits = PCH_UART_HAL_8BIT;
1324         break;
1325     }
1326     if (termios->c_cflag & CSTOPB)
1327         stb = PCH_UART_HAL_STB2;
1328     else
1329         stb = PCH_UART_HAL_STB1;
1330 
1331     if (termios->c_cflag & PARENB) {
1332         if (termios->c_cflag & PARODD)
1333             parity = PCH_UART_HAL_PARITY_ODD;
1334         else
1335             parity = PCH_UART_HAL_PARITY_EVEN;
1336 
1337     } else
1338         parity = PCH_UART_HAL_PARITY_NONE;
1339 
1340     /* Only UART0 has auto hardware flow function */
1341     if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1342         priv->mcr |= UART_MCR_AFE;
1343     else
1344         priv->mcr &= ~UART_MCR_AFE;
1345 
1346     termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1347 
1348     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1349 
1350     spin_lock_irqsave(&priv->lock, flags);
1351     spin_lock(&port->lock);
1352 
1353     uart_update_timeout(port, termios->c_cflag, baud);
1354     rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1355     if (rtn)
1356         goto out;
1357 
1358     pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1359     /* Don't rewrite B0 */
1360     if (tty_termios_baud_rate(termios))
1361         tty_termios_encode_baud_rate(termios, baud, baud);
1362 
1363 out:
1364     spin_unlock(&port->lock);
1365     spin_unlock_irqrestore(&priv->lock, flags);
1366 }
1367 
1368 static const char *pch_uart_type(struct uart_port *port)
1369 {
1370     return KBUILD_MODNAME;
1371 }
1372 
1373 static void pch_uart_release_port(struct uart_port *port)
1374 {
1375     struct eg20t_port *priv;
1376 
1377     priv = container_of(port, struct eg20t_port, port);
1378     pci_iounmap(priv->pdev, priv->membase);
1379     pci_release_regions(priv->pdev);
1380 }
1381 
1382 static int pch_uart_request_port(struct uart_port *port)
1383 {
1384     struct eg20t_port *priv;
1385     int ret;
1386     void __iomem *membase;
1387 
1388     priv = container_of(port, struct eg20t_port, port);
1389     ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1390     if (ret < 0)
1391         return -EBUSY;
1392 
1393     membase = pci_iomap(priv->pdev, 1, 0);
1394     if (!membase) {
1395         pci_release_regions(priv->pdev);
1396         return -EBUSY;
1397     }
1398     priv->membase = port->membase = membase;
1399 
1400     return 0;
1401 }
1402 
1403 static void pch_uart_config_port(struct uart_port *port, int type)
1404 {
1405     struct eg20t_port *priv;
1406 
1407     priv = container_of(port, struct eg20t_port, port);
1408     if (type & UART_CONFIG_TYPE) {
1409         port->type = priv->port_type;
1410         pch_uart_request_port(port);
1411     }
1412 }
1413 
1414 static int pch_uart_verify_port(struct uart_port *port,
1415                 struct serial_struct *serinfo)
1416 {
1417     struct eg20t_port *priv;
1418 
1419     priv = container_of(port, struct eg20t_port, port);
1420     if (serinfo->flags & UPF_LOW_LATENCY) {
1421         dev_info(priv->port.dev,
1422             "PCH UART : Use PIO Mode (without DMA)\n");
1423         priv->use_dma = 0;
1424         serinfo->flags &= ~UPF_LOW_LATENCY;
1425     } else {
1426 #ifndef CONFIG_PCH_DMA
1427         dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1428             __func__);
1429         return -EOPNOTSUPP;
1430 #endif
1431         if (!priv->use_dma) {
1432             pch_request_dma(port);
1433             if (priv->chan_rx)
1434                 priv->use_dma = 1;
1435         }
1436         dev_info(priv->port.dev, "PCH UART: %s\n",
1437                 priv->use_dma ?
1438                 "Use DMA Mode" : "No DMA");
1439     }
1440 
1441     return 0;
1442 }
1443 
1444 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1445 /*
1446  *  Wait for transmitter & holding register to empty
1447  */
1448 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1449 {
1450     unsigned int status, tmout = 10000;
1451 
1452     /* Wait up to 10ms for the character(s) to be sent. */
1453     for (;;) {
1454         status = ioread8(up->membase + UART_LSR);
1455 
1456         if ((status & bits) == bits)
1457             break;
1458         if (--tmout == 0)
1459             break;
1460         udelay(1);
1461     }
1462 
1463     /* Wait up to 1s for flow control if necessary */
1464     if (up->port.flags & UPF_CONS_FLOW) {
1465         unsigned int tmout;
1466         for (tmout = 1000000; tmout; tmout--) {
1467             unsigned int msr = ioread8(up->membase + UART_MSR);
1468             if (msr & UART_MSR_CTS)
1469                 break;
1470             udelay(1);
1471             touch_nmi_watchdog();
1472         }
1473     }
1474 }
1475 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1476 
1477 #ifdef CONFIG_CONSOLE_POLL
1478 /*
1479  * Console polling routines for communicate via uart while
1480  * in an interrupt or debug context.
1481  */
1482 static int pch_uart_get_poll_char(struct uart_port *port)
1483 {
1484     struct eg20t_port *priv =
1485         container_of(port, struct eg20t_port, port);
1486     u8 lsr = ioread8(priv->membase + UART_LSR);
1487 
1488     if (!(lsr & UART_LSR_DR))
1489         return NO_POLL_CHAR;
1490 
1491     return ioread8(priv->membase + PCH_UART_RBR);
1492 }
1493 
1494 
1495 static void pch_uart_put_poll_char(struct uart_port *port,
1496              unsigned char c)
1497 {
1498     unsigned int ier;
1499     struct eg20t_port *priv =
1500         container_of(port, struct eg20t_port, port);
1501 
1502     /*
1503      * First save the IER then disable the interrupts
1504      */
1505     ier = ioread8(priv->membase + UART_IER);
1506     pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1507 
1508     wait_for_xmitr(priv, UART_LSR_THRE);
1509     /*
1510      * Send the character out.
1511      */
1512     iowrite8(c, priv->membase + PCH_UART_THR);
1513 
1514     /*
1515      * Finally, wait for transmitter to become empty
1516      * and restore the IER
1517      */
1518     wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1519     iowrite8(ier, priv->membase + UART_IER);
1520 }
1521 #endif /* CONFIG_CONSOLE_POLL */
1522 
1523 static const struct uart_ops pch_uart_ops = {
1524     .tx_empty = pch_uart_tx_empty,
1525     .set_mctrl = pch_uart_set_mctrl,
1526     .get_mctrl = pch_uart_get_mctrl,
1527     .stop_tx = pch_uart_stop_tx,
1528     .start_tx = pch_uart_start_tx,
1529     .stop_rx = pch_uart_stop_rx,
1530     .enable_ms = pch_uart_enable_ms,
1531     .break_ctl = pch_uart_break_ctl,
1532     .startup = pch_uart_startup,
1533     .shutdown = pch_uart_shutdown,
1534     .set_termios = pch_uart_set_termios,
1535 /*  .pm     = pch_uart_pm,      Not supported yet */
1536     .type = pch_uart_type,
1537     .release_port = pch_uart_release_port,
1538     .request_port = pch_uart_request_port,
1539     .config_port = pch_uart_config_port,
1540     .verify_port = pch_uart_verify_port,
1541 #ifdef CONFIG_CONSOLE_POLL
1542     .poll_get_char = pch_uart_get_poll_char,
1543     .poll_put_char = pch_uart_put_poll_char,
1544 #endif
1545 };
1546 
1547 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1548 
1549 static void pch_console_putchar(struct uart_port *port, unsigned char ch)
1550 {
1551     struct eg20t_port *priv =
1552         container_of(port, struct eg20t_port, port);
1553 
1554     wait_for_xmitr(priv, UART_LSR_THRE);
1555     iowrite8(ch, priv->membase + PCH_UART_THR);
1556 }
1557 
1558 /*
1559  *  Print a string to the serial port trying not to disturb
1560  *  any possible real use of the port...
1561  *
1562  *  The console_lock must be held when we get here.
1563  */
1564 static void
1565 pch_console_write(struct console *co, const char *s, unsigned int count)
1566 {
1567     struct eg20t_port *priv;
1568     unsigned long flags;
1569     int priv_locked = 1;
1570     int port_locked = 1;
1571     u8 ier;
1572 
1573     priv = pch_uart_ports[co->index];
1574 
1575     touch_nmi_watchdog();
1576 
1577     local_irq_save(flags);
1578     if (priv->port.sysrq) {
1579         /* call to uart_handle_sysrq_char already took the priv lock */
1580         priv_locked = 0;
1581         /* serial8250_handle_port() already took the port lock */
1582         port_locked = 0;
1583     } else if (oops_in_progress) {
1584         priv_locked = spin_trylock(&priv->lock);
1585         port_locked = spin_trylock(&priv->port.lock);
1586     } else {
1587         spin_lock(&priv->lock);
1588         spin_lock(&priv->port.lock);
1589     }
1590 
1591     /*
1592      *  First save the IER then disable the interrupts
1593      */
1594     ier = ioread8(priv->membase + UART_IER);
1595 
1596     pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1597 
1598     uart_console_write(&priv->port, s, count, pch_console_putchar);
1599 
1600     /*
1601      *  Finally, wait for transmitter to become empty
1602      *  and restore the IER
1603      */
1604     wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1605     iowrite8(ier, priv->membase + UART_IER);
1606 
1607     if (port_locked)
1608         spin_unlock(&priv->port.lock);
1609     if (priv_locked)
1610         spin_unlock(&priv->lock);
1611     local_irq_restore(flags);
1612 }
1613 
1614 static int __init pch_console_setup(struct console *co, char *options)
1615 {
1616     struct uart_port *port;
1617     int baud = default_baud;
1618     int bits = 8;
1619     int parity = 'n';
1620     int flow = 'n';
1621 
1622     /*
1623      * Check whether an invalid uart number has been specified, and
1624      * if so, search for the first available port that does have
1625      * console support.
1626      */
1627     if (co->index >= PCH_UART_NR)
1628         co->index = 0;
1629     port = &pch_uart_ports[co->index]->port;
1630 
1631     if (!port || (!port->iobase && !port->membase))
1632         return -ENODEV;
1633 
1634     port->uartclk = pch_uart_get_uartclk();
1635 
1636     if (options)
1637         uart_parse_options(options, &baud, &parity, &bits, &flow);
1638 
1639     return uart_set_options(port, co, baud, parity, bits, flow);
1640 }
1641 
1642 static struct uart_driver pch_uart_driver;
1643 
1644 static struct console pch_console = {
1645     .name       = PCH_UART_DRIVER_DEVICE,
1646     .write      = pch_console_write,
1647     .device     = uart_console_device,
1648     .setup      = pch_console_setup,
1649     .flags      = CON_PRINTBUFFER | CON_ANYTIME,
1650     .index      = -1,
1651     .data       = &pch_uart_driver,
1652 };
1653 
1654 #define PCH_CONSOLE (&pch_console)
1655 #else
1656 #define PCH_CONSOLE NULL
1657 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1658 
1659 static struct uart_driver pch_uart_driver = {
1660     .owner = THIS_MODULE,
1661     .driver_name = KBUILD_MODNAME,
1662     .dev_name = PCH_UART_DRIVER_DEVICE,
1663     .major = 0,
1664     .minor = 0,
1665     .nr = PCH_UART_NR,
1666     .cons = PCH_CONSOLE,
1667 };
1668 
1669 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1670                          const struct pci_device_id *id)
1671 {
1672     struct eg20t_port *priv;
1673     int ret;
1674     unsigned int iobase;
1675     unsigned int mapbase;
1676     unsigned char *rxbuf;
1677     int fifosize;
1678     int port_type;
1679     struct pch_uart_driver_data *board;
1680     char name[32];
1681 
1682     board = &drv_dat[id->driver_data];
1683     port_type = board->port_type;
1684 
1685     priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1686     if (priv == NULL)
1687         goto init_port_alloc_err;
1688 
1689     rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1690     if (!rxbuf)
1691         goto init_port_free_txbuf;
1692 
1693     switch (port_type) {
1694     case PORT_PCH_8LINE:
1695         fifosize = 256; /* EG20T/ML7213: UART0 */
1696         break;
1697     case PORT_PCH_2LINE:
1698         fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1699         break;
1700     default:
1701         dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1702         goto init_port_hal_free;
1703     }
1704 
1705     pci_enable_msi(pdev);
1706     pci_set_master(pdev);
1707 
1708     spin_lock_init(&priv->lock);
1709 
1710     iobase = pci_resource_start(pdev, 0);
1711     mapbase = pci_resource_start(pdev, 1);
1712     priv->mapbase = mapbase;
1713     priv->iobase = iobase;
1714     priv->pdev = pdev;
1715     priv->tx_empty = 1;
1716     priv->rxbuf.buf = rxbuf;
1717     priv->rxbuf.size = PAGE_SIZE;
1718 
1719     priv->fifo_size = fifosize;
1720     priv->uartclk = pch_uart_get_uartclk();
1721     priv->port_type = port_type;
1722     priv->port.dev = &pdev->dev;
1723     priv->port.iobase = iobase;
1724     priv->port.membase = NULL;
1725     priv->port.mapbase = mapbase;
1726     priv->port.irq = pdev->irq;
1727     priv->port.iotype = UPIO_PORT;
1728     priv->port.ops = &pch_uart_ops;
1729     priv->port.flags = UPF_BOOT_AUTOCONF;
1730     priv->port.fifosize = fifosize;
1731     priv->port.line = board->line_no;
1732     priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1733     priv->trigger = PCH_UART_HAL_TRIGGER_M;
1734 
1735     snprintf(priv->irq_name, IRQ_NAME_SIZE,
1736          KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1737          priv->port.line);
1738 
1739     spin_lock_init(&priv->port.lock);
1740 
1741     pci_set_drvdata(pdev, priv);
1742     priv->trigger_level = 1;
1743     priv->fcr = 0;
1744 
1745     if (pdev->dev.of_node)
1746         of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1747                      , &user_uartclk);
1748 
1749 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1750     pch_uart_ports[board->line_no] = priv;
1751 #endif
1752     ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1753     if (ret < 0)
1754         goto init_port_hal_free;
1755 
1756     snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1757     debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,
1758                 &port_regs_ops);
1759 
1760     return priv;
1761 
1762 init_port_hal_free:
1763 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1764     pch_uart_ports[board->line_no] = NULL;
1765 #endif
1766     free_page((unsigned long)rxbuf);
1767 init_port_free_txbuf:
1768     kfree(priv);
1769 init_port_alloc_err:
1770 
1771     return NULL;
1772 }
1773 
1774 static void pch_uart_exit_port(struct eg20t_port *priv)
1775 {
1776     char name[32];
1777 
1778     snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1779     debugfs_remove(debugfs_lookup(name, NULL));
1780     uart_remove_one_port(&pch_uart_driver, &priv->port);
1781     free_page((unsigned long)priv->rxbuf.buf);
1782 }
1783 
1784 static void pch_uart_pci_remove(struct pci_dev *pdev)
1785 {
1786     struct eg20t_port *priv = pci_get_drvdata(pdev);
1787 
1788     pci_disable_msi(pdev);
1789 
1790 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1791     pch_uart_ports[priv->port.line] = NULL;
1792 #endif
1793     pch_uart_exit_port(priv);
1794     pci_disable_device(pdev);
1795     kfree(priv);
1796     return;
1797 }
1798 
1799 static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1800 {
1801     struct eg20t_port *priv = dev_get_drvdata(dev);
1802 
1803     uart_suspend_port(&pch_uart_driver, &priv->port);
1804 
1805     return 0;
1806 }
1807 
1808 static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1809 {
1810     struct eg20t_port *priv = dev_get_drvdata(dev);
1811 
1812     uart_resume_port(&pch_uart_driver, &priv->port);
1813 
1814     return 0;
1815 }
1816 
1817 static const struct pci_device_id pch_uart_pci_id[] = {
1818     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1819      .driver_data = pch_et20t_uart0},
1820     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1821      .driver_data = pch_et20t_uart1},
1822     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1823      .driver_data = pch_et20t_uart2},
1824     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1825      .driver_data = pch_et20t_uart3},
1826     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1827      .driver_data = pch_ml7213_uart0},
1828     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1829      .driver_data = pch_ml7213_uart1},
1830     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1831      .driver_data = pch_ml7213_uart2},
1832     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1833      .driver_data = pch_ml7223_uart0},
1834     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1835      .driver_data = pch_ml7223_uart1},
1836     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1837      .driver_data = pch_ml7831_uart0},
1838     {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1839      .driver_data = pch_ml7831_uart1},
1840     {0,},
1841 };
1842 
1843 static int pch_uart_pci_probe(struct pci_dev *pdev,
1844                     const struct pci_device_id *id)
1845 {
1846     int ret;
1847     struct eg20t_port *priv;
1848 
1849     ret = pci_enable_device(pdev);
1850     if (ret < 0)
1851         goto probe_error;
1852 
1853     priv = pch_uart_init_port(pdev, id);
1854     if (!priv) {
1855         ret = -EBUSY;
1856         goto probe_disable_device;
1857     }
1858     pci_set_drvdata(pdev, priv);
1859 
1860     return ret;
1861 
1862 probe_disable_device:
1863     pci_disable_msi(pdev);
1864     pci_disable_device(pdev);
1865 probe_error:
1866     return ret;
1867 }
1868 
1869 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1870              pch_uart_pci_suspend,
1871              pch_uart_pci_resume);
1872 
1873 static struct pci_driver pch_uart_pci_driver = {
1874     .name = "pch_uart",
1875     .id_table = pch_uart_pci_id,
1876     .probe = pch_uart_pci_probe,
1877     .remove = pch_uart_pci_remove,
1878     .driver.pm = &pch_uart_pci_pm_ops,
1879 };
1880 
1881 static int __init pch_uart_module_init(void)
1882 {
1883     int ret;
1884 
1885     /* register as UART driver */
1886     ret = uart_register_driver(&pch_uart_driver);
1887     if (ret < 0)
1888         return ret;
1889 
1890     /* register as PCI driver */
1891     ret = pci_register_driver(&pch_uart_pci_driver);
1892     if (ret < 0)
1893         uart_unregister_driver(&pch_uart_driver);
1894 
1895     return ret;
1896 }
1897 module_init(pch_uart_module_init);
1898 
1899 static void __exit pch_uart_module_exit(void)
1900 {
1901     pci_unregister_driver(&pch_uart_pci_driver);
1902     uart_unregister_driver(&pch_uart_driver);
1903 }
1904 module_exit(pch_uart_module_exit);
1905 
1906 MODULE_LICENSE("GPL v2");
1907 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1908 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1909 
1910 module_param(default_baud, uint, S_IRUGO);
1911 MODULE_PARM_DESC(default_baud,
1912                  "Default BAUD for initial driver state and console (default 9600)");
1913 module_param(user_uartclk, uint, S_IRUGO);
1914 MODULE_PARM_DESC(user_uartclk,
1915                  "Override UART default or board specific UART clock");
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