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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Actions Semi Owl family serial console
0004  *
0005  * Copyright 2013 Actions Semi Inc.
0006  * Author: Actions Semi, Inc.
0007  *
0008  * Copyright (c) 2016-2017 Andreas Färber
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/console.h>
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/serial.h>
0020 #include <linux/serial_core.h>
0021 #include <linux/tty.h>
0022 #include <linux/tty_flip.h>
0023 
0024 #define OWL_UART_PORT_NUM 7
0025 #define OWL_UART_DEV_NAME "ttyOWL"
0026 
0027 #define OWL_UART_CTL    0x000
0028 #define OWL_UART_RXDAT  0x004
0029 #define OWL_UART_TXDAT  0x008
0030 #define OWL_UART_STAT   0x00c
0031 
0032 #define OWL_UART_CTL_DWLS_MASK      GENMASK(1, 0)
0033 #define OWL_UART_CTL_DWLS_5BITS     (0x0 << 0)
0034 #define OWL_UART_CTL_DWLS_6BITS     (0x1 << 0)
0035 #define OWL_UART_CTL_DWLS_7BITS     (0x2 << 0)
0036 #define OWL_UART_CTL_DWLS_8BITS     (0x3 << 0)
0037 #define OWL_UART_CTL_STPS_2BITS     BIT(2)
0038 #define OWL_UART_CTL_PRS_MASK       GENMASK(6, 4)
0039 #define OWL_UART_CTL_PRS_NONE       (0x0 << 4)
0040 #define OWL_UART_CTL_PRS_ODD        (0x4 << 4)
0041 #define OWL_UART_CTL_PRS_MARK       (0x5 << 4)
0042 #define OWL_UART_CTL_PRS_EVEN       (0x6 << 4)
0043 #define OWL_UART_CTL_PRS_SPACE      (0x7 << 4)
0044 #define OWL_UART_CTL_AFE        BIT(12)
0045 #define OWL_UART_CTL_TRFS_TX        BIT(14)
0046 #define OWL_UART_CTL_EN         BIT(15)
0047 #define OWL_UART_CTL_RXDE       BIT(16)
0048 #define OWL_UART_CTL_TXDE       BIT(17)
0049 #define OWL_UART_CTL_RXIE       BIT(18)
0050 #define OWL_UART_CTL_TXIE       BIT(19)
0051 #define OWL_UART_CTL_LBEN       BIT(20)
0052 
0053 #define OWL_UART_STAT_RIP       BIT(0)
0054 #define OWL_UART_STAT_TIP       BIT(1)
0055 #define OWL_UART_STAT_RXER      BIT(2)
0056 #define OWL_UART_STAT_TFER      BIT(3)
0057 #define OWL_UART_STAT_RXST      BIT(4)
0058 #define OWL_UART_STAT_RFEM      BIT(5)
0059 #define OWL_UART_STAT_TFFU      BIT(6)
0060 #define OWL_UART_STAT_CTSS      BIT(7)
0061 #define OWL_UART_STAT_RTSS      BIT(8)
0062 #define OWL_UART_STAT_TFES      BIT(10)
0063 #define OWL_UART_STAT_TRFL_MASK     GENMASK(16, 11)
0064 #define OWL_UART_STAT_UTBB      BIT(17)
0065 
0066 #define OWL_UART_POLL_USEC      5
0067 #define OWL_UART_TIMEOUT_USEC       10000
0068 
0069 static struct uart_driver owl_uart_driver;
0070 
0071 struct owl_uart_info {
0072     unsigned int tx_fifosize;
0073 };
0074 
0075 struct owl_uart_port {
0076     struct uart_port port;
0077     struct clk *clk;
0078 };
0079 
0080 #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
0081 
0082 static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
0083 
0084 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
0085 {
0086     writel(val, port->membase + off);
0087 }
0088 
0089 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
0090 {
0091     return readl(port->membase + off);
0092 }
0093 
0094 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0095 {
0096     u32 ctl;
0097 
0098     ctl = owl_uart_read(port, OWL_UART_CTL);
0099 
0100     if (mctrl & TIOCM_LOOP)
0101         ctl |= OWL_UART_CTL_LBEN;
0102     else
0103         ctl &= ~OWL_UART_CTL_LBEN;
0104 
0105     owl_uart_write(port, ctl, OWL_UART_CTL);
0106 }
0107 
0108 static unsigned int owl_uart_get_mctrl(struct uart_port *port)
0109 {
0110     unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
0111     u32 stat, ctl;
0112 
0113     ctl = owl_uart_read(port, OWL_UART_CTL);
0114     stat = owl_uart_read(port, OWL_UART_STAT);
0115     if (stat & OWL_UART_STAT_RTSS)
0116         mctrl |= TIOCM_RTS;
0117     if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
0118         mctrl |= TIOCM_CTS;
0119     return mctrl;
0120 }
0121 
0122 static unsigned int owl_uart_tx_empty(struct uart_port *port)
0123 {
0124     unsigned long flags;
0125     u32 val;
0126     unsigned int ret;
0127 
0128     spin_lock_irqsave(&port->lock, flags);
0129 
0130     val = owl_uart_read(port, OWL_UART_STAT);
0131     ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
0132 
0133     spin_unlock_irqrestore(&port->lock, flags);
0134 
0135     return ret;
0136 }
0137 
0138 static void owl_uart_stop_rx(struct uart_port *port)
0139 {
0140     u32 val;
0141 
0142     val = owl_uart_read(port, OWL_UART_CTL);
0143     val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
0144     owl_uart_write(port, val, OWL_UART_CTL);
0145 
0146     val = owl_uart_read(port, OWL_UART_STAT);
0147     val |= OWL_UART_STAT_RIP;
0148     owl_uart_write(port, val, OWL_UART_STAT);
0149 }
0150 
0151 static void owl_uart_stop_tx(struct uart_port *port)
0152 {
0153     u32 val;
0154 
0155     val = owl_uart_read(port, OWL_UART_CTL);
0156     val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
0157     owl_uart_write(port, val, OWL_UART_CTL);
0158 
0159     val = owl_uart_read(port, OWL_UART_STAT);
0160     val |= OWL_UART_STAT_TIP;
0161     owl_uart_write(port, val, OWL_UART_STAT);
0162 }
0163 
0164 static void owl_uart_start_tx(struct uart_port *port)
0165 {
0166     u32 val;
0167 
0168     if (uart_tx_stopped(port)) {
0169         owl_uart_stop_tx(port);
0170         return;
0171     }
0172 
0173     val = owl_uart_read(port, OWL_UART_STAT);
0174     val |= OWL_UART_STAT_TIP;
0175     owl_uart_write(port, val, OWL_UART_STAT);
0176 
0177     val = owl_uart_read(port, OWL_UART_CTL);
0178     val |= OWL_UART_CTL_TXIE;
0179     owl_uart_write(port, val, OWL_UART_CTL);
0180 }
0181 
0182 static void owl_uart_send_chars(struct uart_port *port)
0183 {
0184     struct circ_buf *xmit = &port->state->xmit;
0185     unsigned int ch;
0186 
0187     if (port->x_char) {
0188         while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
0189             cpu_relax();
0190         owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
0191         port->icount.tx++;
0192         port->x_char = 0;
0193     }
0194 
0195     if (uart_tx_stopped(port))
0196         return;
0197 
0198     while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
0199         if (uart_circ_empty(xmit))
0200             break;
0201 
0202         ch = xmit->buf[xmit->tail];
0203         owl_uart_write(port, ch, OWL_UART_TXDAT);
0204         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0205         port->icount.tx++;
0206     }
0207 
0208     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0209         uart_write_wakeup(port);
0210 
0211     if (uart_circ_empty(xmit))
0212         owl_uart_stop_tx(port);
0213 }
0214 
0215 static void owl_uart_receive_chars(struct uart_port *port)
0216 {
0217     u32 stat, val;
0218 
0219     val = owl_uart_read(port, OWL_UART_CTL);
0220     val &= ~OWL_UART_CTL_TRFS_TX;
0221     owl_uart_write(port, val, OWL_UART_CTL);
0222 
0223     stat = owl_uart_read(port, OWL_UART_STAT);
0224     while (!(stat & OWL_UART_STAT_RFEM)) {
0225         char flag = TTY_NORMAL;
0226 
0227         if (stat & OWL_UART_STAT_RXER)
0228             port->icount.overrun++;
0229 
0230         if (stat & OWL_UART_STAT_RXST) {
0231             /* We are not able to distinguish the error type. */
0232             port->icount.brk++;
0233             port->icount.frame++;
0234 
0235             stat &= port->read_status_mask;
0236             if (stat & OWL_UART_STAT_RXST)
0237                 flag = TTY_PARITY;
0238         } else
0239             port->icount.rx++;
0240 
0241         val = owl_uart_read(port, OWL_UART_RXDAT);
0242         val &= 0xff;
0243 
0244         if ((stat & port->ignore_status_mask) == 0)
0245             tty_insert_flip_char(&port->state->port, val, flag);
0246 
0247         stat = owl_uart_read(port, OWL_UART_STAT);
0248     }
0249 
0250     tty_flip_buffer_push(&port->state->port);
0251 }
0252 
0253 static irqreturn_t owl_uart_irq(int irq, void *dev_id)
0254 {
0255     struct uart_port *port = dev_id;
0256     unsigned long flags;
0257     u32 stat;
0258 
0259     spin_lock_irqsave(&port->lock, flags);
0260 
0261     stat = owl_uart_read(port, OWL_UART_STAT);
0262 
0263     if (stat & OWL_UART_STAT_RIP)
0264         owl_uart_receive_chars(port);
0265 
0266     if (stat & OWL_UART_STAT_TIP)
0267         owl_uart_send_chars(port);
0268 
0269     stat = owl_uart_read(port, OWL_UART_STAT);
0270     stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
0271     owl_uart_write(port, stat, OWL_UART_STAT);
0272 
0273     spin_unlock_irqrestore(&port->lock, flags);
0274 
0275     return IRQ_HANDLED;
0276 }
0277 
0278 static void owl_uart_shutdown(struct uart_port *port)
0279 {
0280     u32 val;
0281     unsigned long flags;
0282 
0283     spin_lock_irqsave(&port->lock, flags);
0284 
0285     val = owl_uart_read(port, OWL_UART_CTL);
0286     val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
0287         | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
0288     owl_uart_write(port, val, OWL_UART_CTL);
0289 
0290     spin_unlock_irqrestore(&port->lock, flags);
0291 
0292     free_irq(port->irq, port);
0293 }
0294 
0295 static int owl_uart_startup(struct uart_port *port)
0296 {
0297     u32 val;
0298     unsigned long flags;
0299     int ret;
0300 
0301     ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
0302             "owl-uart", port);
0303     if (ret)
0304         return ret;
0305 
0306     spin_lock_irqsave(&port->lock, flags);
0307 
0308     val = owl_uart_read(port, OWL_UART_STAT);
0309     val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
0310         | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
0311     owl_uart_write(port, val, OWL_UART_STAT);
0312 
0313     val = owl_uart_read(port, OWL_UART_CTL);
0314     val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
0315     val |= OWL_UART_CTL_EN;
0316     owl_uart_write(port, val, OWL_UART_CTL);
0317 
0318     spin_unlock_irqrestore(&port->lock, flags);
0319 
0320     return 0;
0321 }
0322 
0323 static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
0324                      unsigned long baud)
0325 {
0326     clk_set_rate(owl_port->clk, baud * 8);
0327 }
0328 
0329 static void owl_uart_set_termios(struct uart_port *port,
0330                  struct ktermios *termios,
0331                  struct ktermios *old)
0332 {
0333     struct owl_uart_port *owl_port = to_owl_uart_port(port);
0334     unsigned int baud;
0335     u32 ctl;
0336     unsigned long flags;
0337 
0338     spin_lock_irqsave(&port->lock, flags);
0339 
0340     ctl = owl_uart_read(port, OWL_UART_CTL);
0341 
0342     ctl &= ~OWL_UART_CTL_DWLS_MASK;
0343     switch (termios->c_cflag & CSIZE) {
0344     case CS5:
0345         ctl |= OWL_UART_CTL_DWLS_5BITS;
0346         break;
0347     case CS6:
0348         ctl |= OWL_UART_CTL_DWLS_6BITS;
0349         break;
0350     case CS7:
0351         ctl |= OWL_UART_CTL_DWLS_7BITS;
0352         break;
0353     case CS8:
0354     default:
0355         ctl |= OWL_UART_CTL_DWLS_8BITS;
0356         break;
0357     }
0358 
0359     if (termios->c_cflag & CSTOPB)
0360         ctl |= OWL_UART_CTL_STPS_2BITS;
0361     else
0362         ctl &= ~OWL_UART_CTL_STPS_2BITS;
0363 
0364     ctl &= ~OWL_UART_CTL_PRS_MASK;
0365     if (termios->c_cflag & PARENB) {
0366         if (termios->c_cflag & CMSPAR) {
0367             if (termios->c_cflag & PARODD)
0368                 ctl |= OWL_UART_CTL_PRS_MARK;
0369             else
0370                 ctl |= OWL_UART_CTL_PRS_SPACE;
0371         } else if (termios->c_cflag & PARODD)
0372             ctl |= OWL_UART_CTL_PRS_ODD;
0373         else
0374             ctl |= OWL_UART_CTL_PRS_EVEN;
0375     } else
0376         ctl |= OWL_UART_CTL_PRS_NONE;
0377 
0378     if (termios->c_cflag & CRTSCTS)
0379         ctl |= OWL_UART_CTL_AFE;
0380     else
0381         ctl &= ~OWL_UART_CTL_AFE;
0382 
0383     owl_uart_write(port, ctl, OWL_UART_CTL);
0384 
0385     baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
0386     owl_uart_change_baudrate(owl_port, baud);
0387 
0388     /* Don't rewrite B0 */
0389     if (tty_termios_baud_rate(termios))
0390         tty_termios_encode_baud_rate(termios, baud, baud);
0391 
0392     port->read_status_mask |= OWL_UART_STAT_RXER;
0393     if (termios->c_iflag & INPCK)
0394         port->read_status_mask |= OWL_UART_STAT_RXST;
0395 
0396     uart_update_timeout(port, termios->c_cflag, baud);
0397 
0398     spin_unlock_irqrestore(&port->lock, flags);
0399 }
0400 
0401 static void owl_uart_release_port(struct uart_port *port)
0402 {
0403     struct platform_device *pdev = to_platform_device(port->dev);
0404     struct resource *res;
0405 
0406     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0407     if (!res)
0408         return;
0409 
0410     if (port->flags & UPF_IOREMAP) {
0411         devm_release_mem_region(port->dev, port->mapbase,
0412             resource_size(res));
0413         devm_iounmap(port->dev, port->membase);
0414         port->membase = NULL;
0415     }
0416 }
0417 
0418 static int owl_uart_request_port(struct uart_port *port)
0419 {
0420     struct platform_device *pdev = to_platform_device(port->dev);
0421     struct resource *res;
0422 
0423     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0424     if (!res)
0425         return -ENXIO;
0426 
0427     if (!devm_request_mem_region(port->dev, port->mapbase,
0428             resource_size(res), dev_name(port->dev)))
0429         return -EBUSY;
0430 
0431     if (port->flags & UPF_IOREMAP) {
0432         port->membase = devm_ioremap(port->dev, port->mapbase,
0433                 resource_size(res));
0434         if (!port->membase)
0435             return -EBUSY;
0436     }
0437 
0438     return 0;
0439 }
0440 
0441 static const char *owl_uart_type(struct uart_port *port)
0442 {
0443     return (port->type == PORT_OWL) ? "owl-uart" : NULL;
0444 }
0445 
0446 static int owl_uart_verify_port(struct uart_port *port,
0447                 struct serial_struct *ser)
0448 {
0449     if (port->type != PORT_OWL)
0450         return -EINVAL;
0451 
0452     if (port->irq != ser->irq)
0453         return -EINVAL;
0454 
0455     return 0;
0456 }
0457 
0458 static void owl_uart_config_port(struct uart_port *port, int flags)
0459 {
0460     if (flags & UART_CONFIG_TYPE) {
0461         port->type = PORT_OWL;
0462         owl_uart_request_port(port);
0463     }
0464 }
0465 
0466 #ifdef CONFIG_CONSOLE_POLL
0467 
0468 static int owl_uart_poll_get_char(struct uart_port *port)
0469 {
0470     if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
0471         return NO_POLL_CHAR;
0472 
0473     return owl_uart_read(port, OWL_UART_RXDAT);
0474 }
0475 
0476 static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
0477 {
0478     u32 reg;
0479     int ret;
0480 
0481     /* Wait while FIFO is full or timeout */
0482     ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
0483                     !(reg & OWL_UART_STAT_TFFU),
0484                     OWL_UART_POLL_USEC,
0485                     OWL_UART_TIMEOUT_USEC);
0486     if (ret == -ETIMEDOUT) {
0487         dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
0488         return;
0489     }
0490 
0491     owl_uart_write(port, ch, OWL_UART_TXDAT);
0492 }
0493 
0494 #endif /* CONFIG_CONSOLE_POLL */
0495 
0496 static const struct uart_ops owl_uart_ops = {
0497     .set_mctrl = owl_uart_set_mctrl,
0498     .get_mctrl = owl_uart_get_mctrl,
0499     .tx_empty = owl_uart_tx_empty,
0500     .start_tx = owl_uart_start_tx,
0501     .stop_rx = owl_uart_stop_rx,
0502     .stop_tx = owl_uart_stop_tx,
0503     .startup = owl_uart_startup,
0504     .shutdown = owl_uart_shutdown,
0505     .set_termios = owl_uart_set_termios,
0506     .type = owl_uart_type,
0507     .config_port = owl_uart_config_port,
0508     .request_port = owl_uart_request_port,
0509     .release_port = owl_uart_release_port,
0510     .verify_port = owl_uart_verify_port,
0511 #ifdef CONFIG_CONSOLE_POLL
0512     .poll_get_char = owl_uart_poll_get_char,
0513     .poll_put_char = owl_uart_poll_put_char,
0514 #endif
0515 };
0516 
0517 #ifdef CONFIG_SERIAL_OWL_CONSOLE
0518 
0519 static void owl_console_putchar(struct uart_port *port, unsigned char ch)
0520 {
0521     if (!port->membase)
0522         return;
0523 
0524     while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
0525         cpu_relax();
0526 
0527     owl_uart_write(port, ch, OWL_UART_TXDAT);
0528 }
0529 
0530 static void owl_uart_port_write(struct uart_port *port, const char *s,
0531                 u_int count)
0532 {
0533     u32 old_ctl, val;
0534     unsigned long flags;
0535     int locked;
0536 
0537     local_irq_save(flags);
0538 
0539     if (port->sysrq)
0540         locked = 0;
0541     else if (oops_in_progress)
0542         locked = spin_trylock(&port->lock);
0543     else {
0544         spin_lock(&port->lock);
0545         locked = 1;
0546     }
0547 
0548     old_ctl = owl_uart_read(port, OWL_UART_CTL);
0549     val = old_ctl | OWL_UART_CTL_TRFS_TX;
0550     /* disable IRQ */
0551     val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
0552     owl_uart_write(port, val, OWL_UART_CTL);
0553 
0554     uart_console_write(port, s, count, owl_console_putchar);
0555 
0556     /* wait until all contents have been sent out */
0557     while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
0558         cpu_relax();
0559 
0560     /* clear IRQ pending */
0561     val = owl_uart_read(port, OWL_UART_STAT);
0562     val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
0563     owl_uart_write(port, val, OWL_UART_STAT);
0564 
0565     owl_uart_write(port, old_ctl, OWL_UART_CTL);
0566 
0567     if (locked)
0568         spin_unlock(&port->lock);
0569 
0570     local_irq_restore(flags);
0571 }
0572 
0573 static void owl_uart_console_write(struct console *co, const char *s,
0574                    u_int count)
0575 {
0576     struct owl_uart_port *owl_port;
0577 
0578     owl_port = owl_uart_ports[co->index];
0579     if (!owl_port)
0580         return;
0581 
0582     owl_uart_port_write(&owl_port->port, s, count);
0583 }
0584 
0585 static int owl_uart_console_setup(struct console *co, char *options)
0586 {
0587     struct owl_uart_port *owl_port;
0588     int baud = 115200;
0589     int bits = 8;
0590     int parity = 'n';
0591     int flow = 'n';
0592 
0593     if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
0594         return -EINVAL;
0595 
0596     owl_port = owl_uart_ports[co->index];
0597     if (!owl_port || !owl_port->port.membase)
0598         return -ENODEV;
0599 
0600     if (options)
0601         uart_parse_options(options, &baud, &parity, &bits, &flow);
0602 
0603     return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
0604 }
0605 
0606 static struct console owl_uart_console = {
0607     .name = OWL_UART_DEV_NAME,
0608     .write = owl_uart_console_write,
0609     .device = uart_console_device,
0610     .setup = owl_uart_console_setup,
0611     .flags = CON_PRINTBUFFER,
0612     .index = -1,
0613     .data = &owl_uart_driver,
0614 };
0615 
0616 static int __init owl_uart_console_init(void)
0617 {
0618     register_console(&owl_uart_console);
0619 
0620     return 0;
0621 }
0622 console_initcall(owl_uart_console_init);
0623 
0624 static void owl_uart_early_console_write(struct console *co,
0625                      const char *s,
0626                      u_int count)
0627 {
0628     struct earlycon_device *dev = co->data;
0629 
0630     owl_uart_port_write(&dev->port, s, count);
0631 }
0632 
0633 static int __init
0634 owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
0635 {
0636     if (!device->port.membase)
0637         return -ENODEV;
0638 
0639     device->con->write = owl_uart_early_console_write;
0640 
0641     return 0;
0642 }
0643 OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
0644             owl_uart_early_console_setup);
0645 
0646 #define OWL_UART_CONSOLE (&owl_uart_console)
0647 #else
0648 #define OWL_UART_CONSOLE NULL
0649 #endif
0650 
0651 static struct uart_driver owl_uart_driver = {
0652     .owner = THIS_MODULE,
0653     .driver_name = "owl-uart",
0654     .dev_name = OWL_UART_DEV_NAME,
0655     .nr = OWL_UART_PORT_NUM,
0656     .cons = OWL_UART_CONSOLE,
0657 };
0658 
0659 static const struct owl_uart_info owl_s500_info = {
0660     .tx_fifosize = 16,
0661 };
0662 
0663 static const struct owl_uart_info owl_s900_info = {
0664     .tx_fifosize = 32,
0665 };
0666 
0667 static const struct of_device_id owl_uart_dt_matches[] = {
0668     { .compatible = "actions,s500-uart", .data = &owl_s500_info },
0669     { .compatible = "actions,s900-uart", .data = &owl_s900_info },
0670     { }
0671 };
0672 MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
0673 
0674 static int owl_uart_probe(struct platform_device *pdev)
0675 {
0676     const struct of_device_id *match;
0677     const struct owl_uart_info *info = NULL;
0678     struct resource *res_mem;
0679     struct owl_uart_port *owl_port;
0680     int ret, irq;
0681 
0682     if (pdev->dev.of_node) {
0683         pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
0684         match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
0685         if (match)
0686             info = match->data;
0687     }
0688 
0689     if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
0690         dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
0691         return -EINVAL;
0692     }
0693 
0694     res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0695     if (!res_mem) {
0696         dev_err(&pdev->dev, "could not get mem\n");
0697         return -ENODEV;
0698     }
0699 
0700     irq = platform_get_irq(pdev, 0);
0701     if (irq < 0)
0702         return irq;
0703 
0704     if (owl_uart_ports[pdev->id]) {
0705         dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
0706         return -EBUSY;
0707     }
0708 
0709     owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
0710     if (!owl_port)
0711         return -ENOMEM;
0712 
0713     owl_port->clk = devm_clk_get(&pdev->dev, NULL);
0714     if (IS_ERR(owl_port->clk)) {
0715         dev_err(&pdev->dev, "could not get clk\n");
0716         return PTR_ERR(owl_port->clk);
0717     }
0718 
0719     ret = clk_prepare_enable(owl_port->clk);
0720     if (ret) {
0721         dev_err(&pdev->dev, "could not enable clk\n");
0722         return ret;
0723     }
0724 
0725     owl_port->port.dev = &pdev->dev;
0726     owl_port->port.line = pdev->id;
0727     owl_port->port.type = PORT_OWL;
0728     owl_port->port.iotype = UPIO_MEM;
0729     owl_port->port.mapbase = res_mem->start;
0730     owl_port->port.irq = irq;
0731     owl_port->port.uartclk = clk_get_rate(owl_port->clk);
0732     if (owl_port->port.uartclk == 0) {
0733         dev_err(&pdev->dev, "clock rate is zero\n");
0734         clk_disable_unprepare(owl_port->clk);
0735         return -EINVAL;
0736     }
0737     owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
0738     owl_port->port.x_char = 0;
0739     owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
0740     owl_port->port.ops = &owl_uart_ops;
0741 
0742     owl_uart_ports[pdev->id] = owl_port;
0743     platform_set_drvdata(pdev, owl_port);
0744 
0745     ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
0746     if (ret)
0747         owl_uart_ports[pdev->id] = NULL;
0748 
0749     return ret;
0750 }
0751 
0752 static int owl_uart_remove(struct platform_device *pdev)
0753 {
0754     struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
0755 
0756     uart_remove_one_port(&owl_uart_driver, &owl_port->port);
0757     owl_uart_ports[pdev->id] = NULL;
0758     clk_disable_unprepare(owl_port->clk);
0759 
0760     return 0;
0761 }
0762 
0763 static struct platform_driver owl_uart_platform_driver = {
0764     .probe = owl_uart_probe,
0765     .remove = owl_uart_remove,
0766     .driver = {
0767         .name = "owl-uart",
0768         .of_match_table = owl_uart_dt_matches,
0769     },
0770 };
0771 
0772 static int __init owl_uart_init(void)
0773 {
0774     int ret;
0775 
0776     ret = uart_register_driver(&owl_uart_driver);
0777     if (ret)
0778         return ret;
0779 
0780     ret = platform_driver_register(&owl_uart_platform_driver);
0781     if (ret)
0782         uart_unregister_driver(&owl_uart_driver);
0783 
0784     return ret;
0785 }
0786 
0787 static void __exit owl_uart_exit(void)
0788 {
0789     platform_driver_unregister(&owl_uart_platform_driver);
0790     uart_unregister_driver(&owl_uart_driver);
0791 }
0792 
0793 module_init(owl_uart_init);
0794 module_exit(owl_uart_exit);
0795 
0796 MODULE_LICENSE("GPL");
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