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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * ***************************************************************************
0004 * Marvell Armada-3700 Serial Driver
0005 * Author: Wilson Ding <dingwei@marvell.com>
0006 * Copyright (C) 2015 Marvell International Ltd.
0007 * ***************************************************************************
0008 */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/console.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/init.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/math64.h>
0019 #include <linux/of.h>
0020 #include <linux/of_address.h>
0021 #include <linux/of_device.h>
0022 #include <linux/of_irq.h>
0023 #include <linux/of_platform.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/serial.h>
0026 #include <linux/serial_core.h>
0027 #include <linux/slab.h>
0028 #include <linux/tty.h>
0029 #include <linux/tty_flip.h>
0030 
0031 /* Register Map */
0032 #define UART_STD_RBR        0x00
0033 #define UART_EXT_RBR        0x18
0034 
0035 #define UART_STD_TSH        0x04
0036 #define UART_EXT_TSH        0x1C
0037 
0038 #define UART_STD_CTRL1      0x08
0039 #define UART_EXT_CTRL1      0x04
0040 #define  CTRL_SOFT_RST      BIT(31)
0041 #define  CTRL_TXFIFO_RST    BIT(15)
0042 #define  CTRL_RXFIFO_RST    BIT(14)
0043 #define  CTRL_SND_BRK_SEQ   BIT(11)
0044 #define  CTRL_BRK_DET_INT   BIT(3)
0045 #define  CTRL_FRM_ERR_INT   BIT(2)
0046 #define  CTRL_PAR_ERR_INT   BIT(1)
0047 #define  CTRL_OVR_ERR_INT   BIT(0)
0048 #define  CTRL_BRK_INT       (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
0049                 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
0050 
0051 #define UART_STD_CTRL2      UART_STD_CTRL1
0052 #define UART_EXT_CTRL2      0x20
0053 #define  CTRL_STD_TX_RDY_INT    BIT(5)
0054 #define  CTRL_EXT_TX_RDY_INT    BIT(6)
0055 #define  CTRL_STD_RX_RDY_INT    BIT(4)
0056 #define  CTRL_EXT_RX_RDY_INT    BIT(5)
0057 
0058 #define UART_STAT       0x0C
0059 #define  STAT_TX_FIFO_EMP   BIT(13)
0060 #define  STAT_TX_FIFO_FUL   BIT(11)
0061 #define  STAT_TX_EMP        BIT(6)
0062 #define  STAT_STD_TX_RDY    BIT(5)
0063 #define  STAT_EXT_TX_RDY    BIT(15)
0064 #define  STAT_STD_RX_RDY    BIT(4)
0065 #define  STAT_EXT_RX_RDY    BIT(14)
0066 #define  STAT_BRK_DET       BIT(3)
0067 #define  STAT_FRM_ERR       BIT(2)
0068 #define  STAT_PAR_ERR       BIT(1)
0069 #define  STAT_OVR_ERR       BIT(0)
0070 #define  STAT_BRK_ERR       (STAT_BRK_DET | STAT_FRM_ERR \
0071                  | STAT_PAR_ERR | STAT_OVR_ERR)
0072 
0073 /*
0074  * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART
0075  * Clock Control register controls UART1 and bit 20 controls UART2. But in
0076  * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an
0077  * error in Marvell's documentation. Hence following CLK_DIS macros are swapped.
0078  */
0079 
0080 #define UART_BRDV       0x10
0081 /* These bits are located in UART1 address space and control UART2 */
0082 #define  UART2_CLK_DIS      BIT(21)
0083 /* These bits are located in UART1 address space and control UART1 */
0084 #define  UART1_CLK_DIS      BIT(20)
0085 /* These bits are located in UART1 address space and control both UARTs */
0086 #define  CLK_NO_XTAL        BIT(19)
0087 #define  CLK_TBG_DIV1_SHIFT 15
0088 #define  CLK_TBG_DIV1_MASK  0x7
0089 #define  CLK_TBG_DIV1_MAX   6
0090 #define  CLK_TBG_DIV2_SHIFT 12
0091 #define  CLK_TBG_DIV2_MASK  0x7
0092 #define  CLK_TBG_DIV2_MAX   6
0093 #define  CLK_TBG_SEL_SHIFT  10
0094 #define  CLK_TBG_SEL_MASK   0x3
0095 /* These bits are located in both UARTs address space */
0096 #define  BRDV_BAUD_MASK         0x3FF
0097 #define  BRDV_BAUD_MAX      BRDV_BAUD_MASK
0098 
0099 #define UART_OSAMP      0x14
0100 #define  OSAMP_DEFAULT_DIVISOR  16
0101 #define  OSAMP_DIVISORS_MASK    0x3F3F3F3F
0102 #define  OSAMP_MAX_DIVISOR  63
0103 
0104 #define MVEBU_NR_UARTS      2
0105 
0106 #define MVEBU_UART_TYPE     "mvebu-uart"
0107 #define DRIVER_NAME     "mvebu_serial"
0108 
0109 enum {
0110     /* Either there is only one summed IRQ... */
0111     UART_IRQ_SUM = 0,
0112     /* ...or there are two separate IRQ for RX and TX */
0113     UART_RX_IRQ = 0,
0114     UART_TX_IRQ,
0115     UART_IRQ_COUNT
0116 };
0117 
0118 /* Diverging register offsets */
0119 struct uart_regs_layout {
0120     unsigned int rbr;
0121     unsigned int tsh;
0122     unsigned int ctrl;
0123     unsigned int intr;
0124 };
0125 
0126 /* Diverging flags */
0127 struct uart_flags {
0128     unsigned int ctrl_tx_rdy_int;
0129     unsigned int ctrl_rx_rdy_int;
0130     unsigned int stat_tx_rdy;
0131     unsigned int stat_rx_rdy;
0132 };
0133 
0134 /* Driver data, a structure for each UART port */
0135 struct mvebu_uart_driver_data {
0136     bool is_ext;
0137     struct uart_regs_layout regs;
0138     struct uart_flags flags;
0139 };
0140 
0141 /* Saved registers during suspend */
0142 struct mvebu_uart_pm_regs {
0143     unsigned int rbr;
0144     unsigned int tsh;
0145     unsigned int ctrl;
0146     unsigned int intr;
0147     unsigned int stat;
0148     unsigned int brdv;
0149     unsigned int osamp;
0150 };
0151 
0152 /* MVEBU UART driver structure */
0153 struct mvebu_uart {
0154     struct uart_port *port;
0155     struct clk *clk;
0156     int irq[UART_IRQ_COUNT];
0157     struct mvebu_uart_driver_data *data;
0158 #if defined(CONFIG_PM)
0159     struct mvebu_uart_pm_regs pm_regs;
0160 #endif /* CONFIG_PM */
0161 };
0162 
0163 static struct mvebu_uart *to_mvuart(struct uart_port *port)
0164 {
0165     return (struct mvebu_uart *)port->private_data;
0166 }
0167 
0168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
0169 
0170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
0171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
0172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
0173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
0174 
0175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
0176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
0177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
0178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
0179 
0180 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
0181 
0182 static DEFINE_SPINLOCK(mvebu_uart_lock);
0183 
0184 /* Core UART Driver Operations */
0185 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
0186 {
0187     unsigned long flags;
0188     unsigned int st;
0189 
0190     spin_lock_irqsave(&port->lock, flags);
0191     st = readl(port->membase + UART_STAT);
0192     spin_unlock_irqrestore(&port->lock, flags);
0193 
0194     return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
0195 }
0196 
0197 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
0198 {
0199     return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
0200 }
0201 
0202 static void mvebu_uart_set_mctrl(struct uart_port *port,
0203                  unsigned int mctrl)
0204 {
0205 /*
0206  * Even if we do not support configuring the modem control lines, this
0207  * function must be proided to the serial core
0208  */
0209 }
0210 
0211 static void mvebu_uart_stop_tx(struct uart_port *port)
0212 {
0213     unsigned int ctl = readl(port->membase + UART_INTR(port));
0214 
0215     ctl &= ~CTRL_TX_RDY_INT(port);
0216     writel(ctl, port->membase + UART_INTR(port));
0217 }
0218 
0219 static void mvebu_uart_start_tx(struct uart_port *port)
0220 {
0221     unsigned int ctl;
0222     struct circ_buf *xmit = &port->state->xmit;
0223 
0224     if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
0225         writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
0226         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0227         port->icount.tx++;
0228     }
0229 
0230     ctl = readl(port->membase + UART_INTR(port));
0231     ctl |= CTRL_TX_RDY_INT(port);
0232     writel(ctl, port->membase + UART_INTR(port));
0233 }
0234 
0235 static void mvebu_uart_stop_rx(struct uart_port *port)
0236 {
0237     unsigned int ctl;
0238 
0239     ctl = readl(port->membase + UART_CTRL(port));
0240     ctl &= ~CTRL_BRK_INT;
0241     writel(ctl, port->membase + UART_CTRL(port));
0242 
0243     ctl = readl(port->membase + UART_INTR(port));
0244     ctl &= ~CTRL_RX_RDY_INT(port);
0245     writel(ctl, port->membase + UART_INTR(port));
0246 }
0247 
0248 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
0249 {
0250     unsigned int ctl;
0251     unsigned long flags;
0252 
0253     spin_lock_irqsave(&port->lock, flags);
0254     ctl = readl(port->membase + UART_CTRL(port));
0255     if (brk == -1)
0256         ctl |= CTRL_SND_BRK_SEQ;
0257     else
0258         ctl &= ~CTRL_SND_BRK_SEQ;
0259     writel(ctl, port->membase + UART_CTRL(port));
0260     spin_unlock_irqrestore(&port->lock, flags);
0261 }
0262 
0263 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
0264 {
0265     struct tty_port *tport = &port->state->port;
0266     unsigned char ch = 0;
0267     char flag = 0;
0268     int ret;
0269 
0270     do {
0271         if (status & STAT_RX_RDY(port)) {
0272             ch = readl(port->membase + UART_RBR(port));
0273             ch &= 0xff;
0274             flag = TTY_NORMAL;
0275             port->icount.rx++;
0276 
0277             if (status & STAT_PAR_ERR)
0278                 port->icount.parity++;
0279         }
0280 
0281         /*
0282          * For UART2, error bits are not cleared on buffer read.
0283          * This causes interrupt loop and system hang.
0284          */
0285         if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) {
0286             ret = readl(port->membase + UART_STAT);
0287             ret |= STAT_BRK_ERR;
0288             writel(ret, port->membase + UART_STAT);
0289         }
0290 
0291         if (status & STAT_BRK_DET) {
0292             port->icount.brk++;
0293             status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
0294             if (uart_handle_break(port))
0295                 goto ignore_char;
0296         }
0297 
0298         if (status & STAT_OVR_ERR)
0299             port->icount.overrun++;
0300 
0301         if (status & STAT_FRM_ERR)
0302             port->icount.frame++;
0303 
0304         if (uart_handle_sysrq_char(port, ch))
0305             goto ignore_char;
0306 
0307         if (status & port->ignore_status_mask & STAT_PAR_ERR)
0308             status &= ~STAT_RX_RDY(port);
0309 
0310         status &= port->read_status_mask;
0311 
0312         if (status & STAT_PAR_ERR)
0313             flag = TTY_PARITY;
0314 
0315         status &= ~port->ignore_status_mask;
0316 
0317         if (status & STAT_RX_RDY(port))
0318             tty_insert_flip_char(tport, ch, flag);
0319 
0320         if (status & STAT_BRK_DET)
0321             tty_insert_flip_char(tport, 0, TTY_BREAK);
0322 
0323         if (status & STAT_FRM_ERR)
0324             tty_insert_flip_char(tport, 0, TTY_FRAME);
0325 
0326         if (status & STAT_OVR_ERR)
0327             tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0328 
0329 ignore_char:
0330         status = readl(port->membase + UART_STAT);
0331     } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
0332 
0333     tty_flip_buffer_push(tport);
0334 }
0335 
0336 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
0337 {
0338     struct circ_buf *xmit = &port->state->xmit;
0339     unsigned int count;
0340     unsigned int st;
0341 
0342     if (port->x_char) {
0343         writel(port->x_char, port->membase + UART_TSH(port));
0344         port->icount.tx++;
0345         port->x_char = 0;
0346         return;
0347     }
0348 
0349     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0350         mvebu_uart_stop_tx(port);
0351         return;
0352     }
0353 
0354     for (count = 0; count < port->fifosize; count++) {
0355         writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
0356         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0357         port->icount.tx++;
0358 
0359         if (uart_circ_empty(xmit))
0360             break;
0361 
0362         st = readl(port->membase + UART_STAT);
0363         if (st & STAT_TX_FIFO_FUL)
0364             break;
0365     }
0366 
0367     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0368         uart_write_wakeup(port);
0369 
0370     if (uart_circ_empty(xmit))
0371         mvebu_uart_stop_tx(port);
0372 }
0373 
0374 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
0375 {
0376     struct uart_port *port = (struct uart_port *)dev_id;
0377     unsigned int st = readl(port->membase + UART_STAT);
0378 
0379     if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
0380           STAT_BRK_DET))
0381         mvebu_uart_rx_chars(port, st);
0382 
0383     if (st & STAT_TX_RDY(port))
0384         mvebu_uart_tx_chars(port, st);
0385 
0386     return IRQ_HANDLED;
0387 }
0388 
0389 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
0390 {
0391     struct uart_port *port = (struct uart_port *)dev_id;
0392     unsigned int st = readl(port->membase + UART_STAT);
0393 
0394     if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
0395             STAT_BRK_DET))
0396         mvebu_uart_rx_chars(port, st);
0397 
0398     return IRQ_HANDLED;
0399 }
0400 
0401 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
0402 {
0403     struct uart_port *port = (struct uart_port *)dev_id;
0404     unsigned int st = readl(port->membase + UART_STAT);
0405 
0406     if (st & STAT_TX_RDY(port))
0407         mvebu_uart_tx_chars(port, st);
0408 
0409     return IRQ_HANDLED;
0410 }
0411 
0412 static int mvebu_uart_startup(struct uart_port *port)
0413 {
0414     struct mvebu_uart *mvuart = to_mvuart(port);
0415     unsigned int ctl;
0416     int ret;
0417 
0418     writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
0419            port->membase + UART_CTRL(port));
0420     udelay(1);
0421 
0422     /* Clear the error bits of state register before IRQ request */
0423     ret = readl(port->membase + UART_STAT);
0424     ret |= STAT_BRK_ERR;
0425     writel(ret, port->membase + UART_STAT);
0426 
0427     writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
0428 
0429     ctl = readl(port->membase + UART_INTR(port));
0430     ctl |= CTRL_RX_RDY_INT(port);
0431     writel(ctl, port->membase + UART_INTR(port));
0432 
0433     if (!mvuart->irq[UART_TX_IRQ]) {
0434         /* Old bindings with just one interrupt (UART0 only) */
0435         ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
0436                        mvebu_uart_isr, port->irqflags,
0437                        dev_name(port->dev), port);
0438         if (ret) {
0439             dev_err(port->dev, "unable to request IRQ %d\n",
0440                 mvuart->irq[UART_IRQ_SUM]);
0441             return ret;
0442         }
0443     } else {
0444         /* New bindings with an IRQ for RX and TX (both UART) */
0445         ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
0446                        mvebu_uart_rx_isr, port->irqflags,
0447                        dev_name(port->dev), port);
0448         if (ret) {
0449             dev_err(port->dev, "unable to request IRQ %d\n",
0450                 mvuart->irq[UART_RX_IRQ]);
0451             return ret;
0452         }
0453 
0454         ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
0455                        mvebu_uart_tx_isr, port->irqflags,
0456                        dev_name(port->dev),
0457                        port);
0458         if (ret) {
0459             dev_err(port->dev, "unable to request IRQ %d\n",
0460                 mvuart->irq[UART_TX_IRQ]);
0461             devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
0462                       port);
0463             return ret;
0464         }
0465     }
0466 
0467     return 0;
0468 }
0469 
0470 static void mvebu_uart_shutdown(struct uart_port *port)
0471 {
0472     struct mvebu_uart *mvuart = to_mvuart(port);
0473 
0474     writel(0, port->membase + UART_INTR(port));
0475 
0476     if (!mvuart->irq[UART_TX_IRQ]) {
0477         devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
0478     } else {
0479         devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
0480         devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
0481     }
0482 }
0483 
0484 static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
0485 {
0486     unsigned int d_divisor, m_divisor;
0487     unsigned long flags;
0488     u32 brdv, osamp;
0489 
0490     if (!port->uartclk)
0491         return 0;
0492 
0493     /*
0494      * The baudrate is derived from the UART clock thanks to divisors:
0495      *   > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6
0496      *   > D ("baud generator"): can divide the clock from 1 to 1023
0497      *   > M ("fractional divisor"): allows a better accuracy (from 1 to 63)
0498      *
0499      * Exact formulas for calculating baudrate:
0500      *
0501      * with default x16 scheme:
0502      *   baudrate = xtal / (d * 16)
0503      *   baudrate = tbg / (d1 * d2 * d * 16)
0504      *
0505      * with fractional divisor:
0506      *   baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4)))
0507      *   baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4)))
0508      *
0509      * Oversampling value:
0510      *   osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24);
0511      *
0512      * Where m1 controls number of clock cycles per bit for bits 1,2,3;
0513      * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10.
0514      *
0515      * To simplify baudrate setup set all the M prescalers to the same
0516      * value. For baudrates 9600 Bd and higher, it is enough to use the
0517      * default (x16) divisor or fractional divisor with M = 63, so there
0518      * is no need to use real fractional support (where the M prescalers
0519      * are not equal).
0520      *
0521      * When all the M prescalers are zeroed then default (x16) divisor is
0522      * used. Default x16 scheme is more stable than M (fractional divisor),
0523      * so use M only when D divisor is not enough to derive baudrate.
0524      *
0525      * Member port->uartclk is either xtal clock rate or TBG clock rate
0526      * divided by (d1 * d2). So d1 and d2 are already set by the UART clock
0527      * driver (and UART driver itself cannot change them). Moreover they are
0528      * shared between both UARTs.
0529      */
0530 
0531     m_divisor = OSAMP_DEFAULT_DIVISOR;
0532     d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
0533 
0534     if (d_divisor > BRDV_BAUD_MAX) {
0535         /*
0536          * Experiments show that small M divisors are unstable.
0537          * Use maximal possible M = 63 and calculate D divisor.
0538          */
0539         m_divisor = OSAMP_MAX_DIVISOR;
0540         d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
0541     }
0542 
0543     if (d_divisor < 1)
0544         d_divisor = 1;
0545     else if (d_divisor > BRDV_BAUD_MAX)
0546         d_divisor = BRDV_BAUD_MAX;
0547 
0548     spin_lock_irqsave(&mvebu_uart_lock, flags);
0549     brdv = readl(port->membase + UART_BRDV);
0550     brdv &= ~BRDV_BAUD_MASK;
0551     brdv |= d_divisor;
0552     writel(brdv, port->membase + UART_BRDV);
0553     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
0554 
0555     osamp = readl(port->membase + UART_OSAMP);
0556     osamp &= ~OSAMP_DIVISORS_MASK;
0557     if (m_divisor != OSAMP_DEFAULT_DIVISOR)
0558         osamp |= (m_divisor << 0) | (m_divisor << 8) |
0559             (m_divisor << 16) | (m_divisor << 24);
0560     writel(osamp, port->membase + UART_OSAMP);
0561 
0562     return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor);
0563 }
0564 
0565 static void mvebu_uart_set_termios(struct uart_port *port,
0566                    struct ktermios *termios,
0567                    struct ktermios *old)
0568 {
0569     unsigned long flags;
0570     unsigned int baud, min_baud, max_baud;
0571 
0572     spin_lock_irqsave(&port->lock, flags);
0573 
0574     port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
0575         STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
0576 
0577     if (termios->c_iflag & INPCK)
0578         port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
0579 
0580     port->ignore_status_mask = 0;
0581     if (termios->c_iflag & IGNPAR)
0582         port->ignore_status_mask |=
0583             STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
0584 
0585     if ((termios->c_cflag & CREAD) == 0)
0586         port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
0587 
0588     /*
0589      * Maximal divisor is 1023 and maximal fractional divisor is 63. And
0590      * experiments show that baudrates above 1/80 of parent clock rate are
0591      * not stable. So disallow baudrates above 1/80 of the parent clock
0592      * rate. If port->uartclk is not available, then
0593      * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud
0594      * in this case do not matter.
0595      */
0596     min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX *
0597                 OSAMP_MAX_DIVISOR);
0598     max_baud = port->uartclk / 80;
0599 
0600     baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
0601     baud = mvebu_uart_baud_rate_set(port, baud);
0602 
0603     /* In case baudrate cannot be changed, report previous old value */
0604     if (baud == 0 && old)
0605         baud = tty_termios_baud_rate(old);
0606 
0607     /* Only the following flag changes are supported */
0608     if (old) {
0609         termios->c_iflag &= INPCK | IGNPAR;
0610         termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
0611         termios->c_cflag &= CREAD | CBAUD;
0612         termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
0613         termios->c_cflag |= CS8;
0614     }
0615 
0616     if (baud != 0) {
0617         tty_termios_encode_baud_rate(termios, baud, baud);
0618         uart_update_timeout(port, termios->c_cflag, baud);
0619     }
0620 
0621     spin_unlock_irqrestore(&port->lock, flags);
0622 }
0623 
0624 static const char *mvebu_uart_type(struct uart_port *port)
0625 {
0626     return MVEBU_UART_TYPE;
0627 }
0628 
0629 static void mvebu_uart_release_port(struct uart_port *port)
0630 {
0631     /* Nothing to do here */
0632 }
0633 
0634 static int mvebu_uart_request_port(struct uart_port *port)
0635 {
0636     return 0;
0637 }
0638 
0639 #ifdef CONFIG_CONSOLE_POLL
0640 static int mvebu_uart_get_poll_char(struct uart_port *port)
0641 {
0642     unsigned int st = readl(port->membase + UART_STAT);
0643 
0644     if (!(st & STAT_RX_RDY(port)))
0645         return NO_POLL_CHAR;
0646 
0647     return readl(port->membase + UART_RBR(port));
0648 }
0649 
0650 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
0651 {
0652     unsigned int st;
0653 
0654     for (;;) {
0655         st = readl(port->membase + UART_STAT);
0656 
0657         if (!(st & STAT_TX_FIFO_FUL))
0658             break;
0659 
0660         udelay(1);
0661     }
0662 
0663     writel(c, port->membase + UART_TSH(port));
0664 }
0665 #endif
0666 
0667 static const struct uart_ops mvebu_uart_ops = {
0668     .tx_empty   = mvebu_uart_tx_empty,
0669     .set_mctrl  = mvebu_uart_set_mctrl,
0670     .get_mctrl  = mvebu_uart_get_mctrl,
0671     .stop_tx    = mvebu_uart_stop_tx,
0672     .start_tx   = mvebu_uart_start_tx,
0673     .stop_rx    = mvebu_uart_stop_rx,
0674     .break_ctl  = mvebu_uart_break_ctl,
0675     .startup    = mvebu_uart_startup,
0676     .shutdown   = mvebu_uart_shutdown,
0677     .set_termios    = mvebu_uart_set_termios,
0678     .type       = mvebu_uart_type,
0679     .release_port   = mvebu_uart_release_port,
0680     .request_port   = mvebu_uart_request_port,
0681 #ifdef CONFIG_CONSOLE_POLL
0682     .poll_get_char  = mvebu_uart_get_poll_char,
0683     .poll_put_char  = mvebu_uart_put_poll_char,
0684 #endif
0685 };
0686 
0687 /* Console Driver Operations  */
0688 
0689 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
0690 /* Early Console */
0691 static void mvebu_uart_putc(struct uart_port *port, unsigned char c)
0692 {
0693     unsigned int st;
0694 
0695     for (;;) {
0696         st = readl(port->membase + UART_STAT);
0697         if (!(st & STAT_TX_FIFO_FUL))
0698             break;
0699     }
0700 
0701     /* At early stage, DT is not parsed yet, only use UART0 */
0702     writel(c, port->membase + UART_STD_TSH);
0703 
0704     for (;;) {
0705         st = readl(port->membase + UART_STAT);
0706         if (st & STAT_TX_FIFO_EMP)
0707             break;
0708     }
0709 }
0710 
0711 static void mvebu_uart_putc_early_write(struct console *con,
0712                     const char *s,
0713                     unsigned int n)
0714 {
0715     struct earlycon_device *dev = con->data;
0716 
0717     uart_console_write(&dev->port, s, n, mvebu_uart_putc);
0718 }
0719 
0720 static int __init
0721 mvebu_uart_early_console_setup(struct earlycon_device *device,
0722                    const char *opt)
0723 {
0724     if (!device->port.membase)
0725         return -ENODEV;
0726 
0727     device->con->write = mvebu_uart_putc_early_write;
0728 
0729     return 0;
0730 }
0731 
0732 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
0733 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
0734             mvebu_uart_early_console_setup);
0735 
0736 static void wait_for_xmitr(struct uart_port *port)
0737 {
0738     u32 val;
0739 
0740     readl_poll_timeout_atomic(port->membase + UART_STAT, val,
0741                   (val & STAT_TX_RDY(port)), 1, 10000);
0742 }
0743 
0744 static void wait_for_xmite(struct uart_port *port)
0745 {
0746     u32 val;
0747 
0748     readl_poll_timeout_atomic(port->membase + UART_STAT, val,
0749                   (val & STAT_TX_EMP), 1, 10000);
0750 }
0751 
0752 static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch)
0753 {
0754     wait_for_xmitr(port);
0755     writel(ch, port->membase + UART_TSH(port));
0756 }
0757 
0758 static void mvebu_uart_console_write(struct console *co, const char *s,
0759                      unsigned int count)
0760 {
0761     struct uart_port *port = &mvebu_uart_ports[co->index];
0762     unsigned long flags;
0763     unsigned int ier, intr, ctl;
0764     int locked = 1;
0765 
0766     if (oops_in_progress)
0767         locked = spin_trylock_irqsave(&port->lock, flags);
0768     else
0769         spin_lock_irqsave(&port->lock, flags);
0770 
0771     ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
0772     intr = readl(port->membase + UART_INTR(port)) &
0773         (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
0774     writel(0, port->membase + UART_CTRL(port));
0775     writel(0, port->membase + UART_INTR(port));
0776 
0777     uart_console_write(port, s, count, mvebu_uart_console_putchar);
0778 
0779     wait_for_xmite(port);
0780 
0781     if (ier)
0782         writel(ier, port->membase + UART_CTRL(port));
0783 
0784     if (intr) {
0785         ctl = intr | readl(port->membase + UART_INTR(port));
0786         writel(ctl, port->membase + UART_INTR(port));
0787     }
0788 
0789     if (locked)
0790         spin_unlock_irqrestore(&port->lock, flags);
0791 }
0792 
0793 static int mvebu_uart_console_setup(struct console *co, char *options)
0794 {
0795     struct uart_port *port;
0796     int baud = 9600;
0797     int bits = 8;
0798     int parity = 'n';
0799     int flow = 'n';
0800 
0801     if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
0802         return -EINVAL;
0803 
0804     port = &mvebu_uart_ports[co->index];
0805 
0806     if (!port->mapbase || !port->membase) {
0807         pr_debug("console on ttyMV%i not present\n", co->index);
0808         return -ENODEV;
0809     }
0810 
0811     if (options)
0812         uart_parse_options(options, &baud, &parity, &bits, &flow);
0813 
0814     return uart_set_options(port, co, baud, parity, bits, flow);
0815 }
0816 
0817 static struct uart_driver mvebu_uart_driver;
0818 
0819 static struct console mvebu_uart_console = {
0820     .name   = "ttyMV",
0821     .write  = mvebu_uart_console_write,
0822     .device = uart_console_device,
0823     .setup  = mvebu_uart_console_setup,
0824     .flags  = CON_PRINTBUFFER,
0825     .index  = -1,
0826     .data   = &mvebu_uart_driver,
0827 };
0828 
0829 static int __init mvebu_uart_console_init(void)
0830 {
0831     register_console(&mvebu_uart_console);
0832     return 0;
0833 }
0834 
0835 console_initcall(mvebu_uart_console_init);
0836 
0837 
0838 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
0839 
0840 static struct uart_driver mvebu_uart_driver = {
0841     .owner          = THIS_MODULE,
0842     .driver_name        = DRIVER_NAME,
0843     .dev_name       = "ttyMV",
0844     .nr         = MVEBU_NR_UARTS,
0845 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
0846     .cons           = &mvebu_uart_console,
0847 #endif
0848 };
0849 
0850 #if defined(CONFIG_PM)
0851 static int mvebu_uart_suspend(struct device *dev)
0852 {
0853     struct mvebu_uart *mvuart = dev_get_drvdata(dev);
0854     struct uart_port *port = mvuart->port;
0855     unsigned long flags;
0856 
0857     uart_suspend_port(&mvebu_uart_driver, port);
0858 
0859     mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
0860     mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
0861     mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
0862     mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
0863     mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
0864     spin_lock_irqsave(&mvebu_uart_lock, flags);
0865     mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
0866     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
0867     mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
0868 
0869     device_set_wakeup_enable(dev, true);
0870 
0871     return 0;
0872 }
0873 
0874 static int mvebu_uart_resume(struct device *dev)
0875 {
0876     struct mvebu_uart *mvuart = dev_get_drvdata(dev);
0877     struct uart_port *port = mvuart->port;
0878     unsigned long flags;
0879 
0880     writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
0881     writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
0882     writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
0883     writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
0884     writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
0885     spin_lock_irqsave(&mvebu_uart_lock, flags);
0886     writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
0887     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
0888     writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
0889 
0890     uart_resume_port(&mvebu_uart_driver, port);
0891 
0892     return 0;
0893 }
0894 
0895 static const struct dev_pm_ops mvebu_uart_pm_ops = {
0896     .suspend        = mvebu_uart_suspend,
0897     .resume         = mvebu_uart_resume,
0898 };
0899 #endif /* CONFIG_PM */
0900 
0901 static const struct of_device_id mvebu_uart_of_match[];
0902 
0903 /* Counter to keep track of each UART port id when not using CONFIG_OF */
0904 static int uart_num_counter;
0905 
0906 static int mvebu_uart_probe(struct platform_device *pdev)
0907 {
0908     struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0909     const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
0910                                &pdev->dev);
0911     struct uart_port *port;
0912     struct mvebu_uart *mvuart;
0913     int id, irq;
0914 
0915     if (!reg) {
0916         dev_err(&pdev->dev, "no registers defined\n");
0917         return -EINVAL;
0918     }
0919 
0920     /* Assume that all UART ports have a DT alias or none has */
0921     id = of_alias_get_id(pdev->dev.of_node, "serial");
0922     if (!pdev->dev.of_node || id < 0)
0923         pdev->id = uart_num_counter++;
0924     else
0925         pdev->id = id;
0926 
0927     if (pdev->id >= MVEBU_NR_UARTS) {
0928         dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
0929             MVEBU_NR_UARTS);
0930         return -EINVAL;
0931     }
0932 
0933     port = &mvebu_uart_ports[pdev->id];
0934 
0935     spin_lock_init(&port->lock);
0936 
0937     port->dev        = &pdev->dev;
0938     port->type       = PORT_MVEBU;
0939     port->ops        = &mvebu_uart_ops;
0940     port->regshift   = 0;
0941 
0942     port->fifosize   = 32;
0943     port->iotype     = UPIO_MEM32;
0944     port->flags      = UPF_FIXED_PORT;
0945     port->line       = pdev->id;
0946 
0947     /*
0948      * IRQ number is not stored in this structure because we may have two of
0949      * them per port (RX and TX). Instead, use the driver UART structure
0950      * array so called ->irq[].
0951      */
0952     port->irq        = 0;
0953     port->irqflags   = 0;
0954     port->mapbase    = reg->start;
0955 
0956     port->membase = devm_ioremap_resource(&pdev->dev, reg);
0957     if (IS_ERR(port->membase))
0958         return PTR_ERR(port->membase);
0959 
0960     mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
0961                   GFP_KERNEL);
0962     if (!mvuart)
0963         return -ENOMEM;
0964 
0965     /* Get controller data depending on the compatible string */
0966     mvuart->data = (struct mvebu_uart_driver_data *)match->data;
0967     mvuart->port = port;
0968 
0969     port->private_data = mvuart;
0970     platform_set_drvdata(pdev, mvuart);
0971 
0972     /* Get fixed clock frequency */
0973     mvuart->clk = devm_clk_get(&pdev->dev, NULL);
0974     if (IS_ERR(mvuart->clk)) {
0975         if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
0976             return PTR_ERR(mvuart->clk);
0977 
0978         if (IS_EXTENDED(port)) {
0979             dev_err(&pdev->dev, "unable to get UART clock\n");
0980             return PTR_ERR(mvuart->clk);
0981         }
0982     } else {
0983         if (!clk_prepare_enable(mvuart->clk))
0984             port->uartclk = clk_get_rate(mvuart->clk);
0985     }
0986 
0987     /* Manage interrupts */
0988     if (platform_irq_count(pdev) == 1) {
0989         /* Old bindings: no name on the single unamed UART0 IRQ */
0990         irq = platform_get_irq(pdev, 0);
0991         if (irq < 0)
0992             return irq;
0993 
0994         mvuart->irq[UART_IRQ_SUM] = irq;
0995     } else {
0996         /*
0997          * New bindings: named interrupts (RX, TX) for both UARTS,
0998          * only make use of uart-rx and uart-tx interrupts, do not use
0999          * uart-sum of UART0 port.
1000          */
1001         irq = platform_get_irq_byname(pdev, "uart-rx");
1002         if (irq < 0)
1003             return irq;
1004 
1005         mvuart->irq[UART_RX_IRQ] = irq;
1006 
1007         irq = platform_get_irq_byname(pdev, "uart-tx");
1008         if (irq < 0)
1009             return irq;
1010 
1011         mvuart->irq[UART_TX_IRQ] = irq;
1012     }
1013 
1014     /* UART Soft Reset*/
1015     writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
1016     udelay(1);
1017     writel(0, port->membase + UART_CTRL(port));
1018 
1019     return uart_add_one_port(&mvebu_uart_driver, port);
1020 }
1021 
1022 static struct mvebu_uart_driver_data uart_std_driver_data = {
1023     .is_ext = false,
1024     .regs.rbr = UART_STD_RBR,
1025     .regs.tsh = UART_STD_TSH,
1026     .regs.ctrl = UART_STD_CTRL1,
1027     .regs.intr = UART_STD_CTRL2,
1028     .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
1029     .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
1030     .flags.stat_tx_rdy = STAT_STD_TX_RDY,
1031     .flags.stat_rx_rdy = STAT_STD_RX_RDY,
1032 };
1033 
1034 static struct mvebu_uart_driver_data uart_ext_driver_data = {
1035     .is_ext = true,
1036     .regs.rbr = UART_EXT_RBR,
1037     .regs.tsh = UART_EXT_TSH,
1038     .regs.ctrl = UART_EXT_CTRL1,
1039     .regs.intr = UART_EXT_CTRL2,
1040     .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
1041     .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
1042     .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
1043     .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
1044 };
1045 
1046 /* Match table for of_platform binding */
1047 static const struct of_device_id mvebu_uart_of_match[] = {
1048     {
1049         .compatible = "marvell,armada-3700-uart",
1050         .data = (void *)&uart_std_driver_data,
1051     },
1052     {
1053         .compatible = "marvell,armada-3700-uart-ext",
1054         .data = (void *)&uart_ext_driver_data,
1055     },
1056     {}
1057 };
1058 
1059 static struct platform_driver mvebu_uart_platform_driver = {
1060     .probe  = mvebu_uart_probe,
1061     .driver = {
1062         .name  = "mvebu-uart",
1063         .of_match_table = of_match_ptr(mvebu_uart_of_match),
1064         .suppress_bind_attrs = true,
1065 #if defined(CONFIG_PM)
1066         .pm = &mvebu_uart_pm_ops,
1067 #endif /* CONFIG_PM */
1068     },
1069 };
1070 
1071 /* This code is based on clk-fixed-factor.c driver and modified. */
1072 
1073 struct mvebu_uart_clock {
1074     struct clk_hw clk_hw;
1075     int clock_idx;
1076     u32 pm_context_reg1;
1077     u32 pm_context_reg2;
1078 };
1079 
1080 struct mvebu_uart_clock_base {
1081     struct mvebu_uart_clock clocks[2];
1082     unsigned int parent_rates[5];
1083     int parent_idx;
1084     unsigned int div;
1085     void __iomem *reg1;
1086     void __iomem *reg2;
1087     bool configured;
1088 };
1089 
1090 #define PARENT_CLOCK_XTAL 4
1091 
1092 #define to_uart_clock(hw) container_of(hw, struct mvebu_uart_clock, clk_hw)
1093 #define to_uart_clock_base(uart_clock) container_of(uart_clock, \
1094     struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx])
1095 
1096 static int mvebu_uart_clock_prepare(struct clk_hw *hw)
1097 {
1098     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1099     struct mvebu_uart_clock_base *uart_clock_base =
1100                         to_uart_clock_base(uart_clock);
1101     unsigned int prev_clock_idx, prev_clock_rate, prev_d1d2;
1102     unsigned int parent_clock_idx, parent_clock_rate;
1103     unsigned long flags;
1104     unsigned int d1, d2;
1105     u64 divisor;
1106     u32 val;
1107 
1108     /*
1109      * This function just reconfigures UART Clock Control register (located
1110      * in UART1 address space which controls both UART1 and UART2) to
1111      * selected UART base clock and recalculates current UART1/UART2
1112      * divisors in their address spaces, so that final baudrate will not be
1113      * changed by switching UART parent clock. This is required for
1114      * otherwise kernel's boot log stops working - we need to ensure that
1115      * UART baudrate does not change during this setup. It is a one time
1116      * operation, it will execute only once and set `configured` to true,
1117      * and be skipped on subsequent calls. Because this UART Clock Control
1118      * register (UART_BRDV) is shared between UART1 baudrate function,
1119      * UART1 clock selector and UART2 clock selector, every access to
1120      * UART_BRDV (reg1) needs to be protected by a lock.
1121      */
1122 
1123     spin_lock_irqsave(&mvebu_uart_lock, flags);
1124 
1125     if (uart_clock_base->configured) {
1126         spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1127         return 0;
1128     }
1129 
1130     parent_clock_idx = uart_clock_base->parent_idx;
1131     parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx];
1132 
1133     val = readl(uart_clock_base->reg1);
1134 
1135     if (uart_clock_base->div > CLK_TBG_DIV1_MAX) {
1136         d1 = CLK_TBG_DIV1_MAX;
1137         d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX;
1138     } else {
1139         d1 = uart_clock_base->div;
1140         d2 = 1;
1141     }
1142 
1143     if (val & CLK_NO_XTAL) {
1144         prev_clock_idx = (val >> CLK_TBG_SEL_SHIFT) & CLK_TBG_SEL_MASK;
1145         prev_d1d2 = ((val >> CLK_TBG_DIV1_SHIFT) & CLK_TBG_DIV1_MASK) *
1146                 ((val >> CLK_TBG_DIV2_SHIFT) & CLK_TBG_DIV2_MASK);
1147     } else {
1148         prev_clock_idx = PARENT_CLOCK_XTAL;
1149         prev_d1d2 = 1;
1150     }
1151 
1152     /* Note that uart_clock_base->parent_rates[i] may not be available */
1153     prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx];
1154 
1155     /* Recalculate UART1 divisor so UART1 baudrate does not change */
1156     if (prev_clock_rate) {
1157         divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) *
1158                         parent_clock_rate * prev_d1d2,
1159                         prev_clock_rate * d1 * d2);
1160         if (divisor < 1)
1161             divisor = 1;
1162         else if (divisor > BRDV_BAUD_MAX)
1163             divisor = BRDV_BAUD_MAX;
1164         val = (val & ~BRDV_BAUD_MASK) | divisor;
1165     }
1166 
1167     if (parent_clock_idx != PARENT_CLOCK_XTAL) {
1168         /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */
1169         val |= CLK_NO_XTAL;
1170         val &= ~(CLK_TBG_DIV1_MASK << CLK_TBG_DIV1_SHIFT);
1171         val |= d1 << CLK_TBG_DIV1_SHIFT;
1172         val &= ~(CLK_TBG_DIV2_MASK << CLK_TBG_DIV2_SHIFT);
1173         val |= d2 << CLK_TBG_DIV2_SHIFT;
1174         val &= ~(CLK_TBG_SEL_MASK << CLK_TBG_SEL_SHIFT);
1175         val |= parent_clock_idx << CLK_TBG_SEL_SHIFT;
1176     } else {
1177         /* Use XTAL, TBG bits are then ignored */
1178         val &= ~CLK_NO_XTAL;
1179     }
1180 
1181     writel(val, uart_clock_base->reg1);
1182 
1183     /* Recalculate UART2 divisor so UART2 baudrate does not change */
1184     if (prev_clock_rate) {
1185         val = readl(uart_clock_base->reg2);
1186         divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) *
1187                         parent_clock_rate * prev_d1d2,
1188                         prev_clock_rate * d1 * d2);
1189         if (divisor < 1)
1190             divisor = 1;
1191         else if (divisor > BRDV_BAUD_MAX)
1192             divisor = BRDV_BAUD_MAX;
1193         val = (val & ~BRDV_BAUD_MASK) | divisor;
1194         writel(val, uart_clock_base->reg2);
1195     }
1196 
1197     uart_clock_base->configured = true;
1198 
1199     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1200 
1201     return 0;
1202 }
1203 
1204 static int mvebu_uart_clock_enable(struct clk_hw *hw)
1205 {
1206     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1207     struct mvebu_uart_clock_base *uart_clock_base =
1208                         to_uart_clock_base(uart_clock);
1209     unsigned long flags;
1210     u32 val;
1211 
1212     spin_lock_irqsave(&mvebu_uart_lock, flags);
1213 
1214     val = readl(uart_clock_base->reg1);
1215 
1216     if (uart_clock->clock_idx == 0)
1217         val &= ~UART1_CLK_DIS;
1218     else
1219         val &= ~UART2_CLK_DIS;
1220 
1221     writel(val, uart_clock_base->reg1);
1222 
1223     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1224 
1225     return 0;
1226 }
1227 
1228 static void mvebu_uart_clock_disable(struct clk_hw *hw)
1229 {
1230     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1231     struct mvebu_uart_clock_base *uart_clock_base =
1232                         to_uart_clock_base(uart_clock);
1233     unsigned long flags;
1234     u32 val;
1235 
1236     spin_lock_irqsave(&mvebu_uart_lock, flags);
1237 
1238     val = readl(uart_clock_base->reg1);
1239 
1240     if (uart_clock->clock_idx == 0)
1241         val |= UART1_CLK_DIS;
1242     else
1243         val |= UART2_CLK_DIS;
1244 
1245     writel(val, uart_clock_base->reg1);
1246 
1247     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1248 }
1249 
1250 static int mvebu_uart_clock_is_enabled(struct clk_hw *hw)
1251 {
1252     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1253     struct mvebu_uart_clock_base *uart_clock_base =
1254                         to_uart_clock_base(uart_clock);
1255     u32 val;
1256 
1257     val = readl(uart_clock_base->reg1);
1258 
1259     if (uart_clock->clock_idx == 0)
1260         return !(val & UART1_CLK_DIS);
1261     else
1262         return !(val & UART2_CLK_DIS);
1263 }
1264 
1265 static int mvebu_uart_clock_save_context(struct clk_hw *hw)
1266 {
1267     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1268     struct mvebu_uart_clock_base *uart_clock_base =
1269                         to_uart_clock_base(uart_clock);
1270     unsigned long flags;
1271 
1272     spin_lock_irqsave(&mvebu_uart_lock, flags);
1273     uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1);
1274     uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2);
1275     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1276 
1277     return 0;
1278 }
1279 
1280 static void mvebu_uart_clock_restore_context(struct clk_hw *hw)
1281 {
1282     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1283     struct mvebu_uart_clock_base *uart_clock_base =
1284                         to_uart_clock_base(uart_clock);
1285     unsigned long flags;
1286 
1287     spin_lock_irqsave(&mvebu_uart_lock, flags);
1288     writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);
1289     writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);
1290     spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1291 }
1292 
1293 static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw,
1294                           unsigned long parent_rate)
1295 {
1296     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1297     struct mvebu_uart_clock_base *uart_clock_base =
1298                         to_uart_clock_base(uart_clock);
1299 
1300     return parent_rate / uart_clock_base->div;
1301 }
1302 
1303 static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate,
1304                     unsigned long *parent_rate)
1305 {
1306     struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1307     struct mvebu_uart_clock_base *uart_clock_base =
1308                         to_uart_clock_base(uart_clock);
1309 
1310     return *parent_rate / uart_clock_base->div;
1311 }
1312 
1313 static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate,
1314                      unsigned long parent_rate)
1315 {
1316     /*
1317      * We must report success but we can do so unconditionally because
1318      * mvebu_uart_clock_round_rate returns values that ensure this call is a
1319      * nop.
1320      */
1321 
1322     return 0;
1323 }
1324 
1325 static const struct clk_ops mvebu_uart_clock_ops = {
1326     .prepare = mvebu_uart_clock_prepare,
1327     .enable = mvebu_uart_clock_enable,
1328     .disable = mvebu_uart_clock_disable,
1329     .is_enabled = mvebu_uart_clock_is_enabled,
1330     .save_context = mvebu_uart_clock_save_context,
1331     .restore_context = mvebu_uart_clock_restore_context,
1332     .round_rate = mvebu_uart_clock_round_rate,
1333     .set_rate = mvebu_uart_clock_set_rate,
1334     .recalc_rate = mvebu_uart_clock_recalc_rate,
1335 };
1336 
1337 static int mvebu_uart_clock_register(struct device *dev,
1338                      struct mvebu_uart_clock *uart_clock,
1339                      const char *name,
1340                      const char *parent_name)
1341 {
1342     struct clk_init_data init = { };
1343 
1344     uart_clock->clk_hw.init = &init;
1345 
1346     init.name = name;
1347     init.ops = &mvebu_uart_clock_ops;
1348     init.flags = 0;
1349     init.num_parents = 1;
1350     init.parent_names = &parent_name;
1351 
1352     return devm_clk_hw_register(dev, &uart_clock->clk_hw);
1353 }
1354 
1355 static int mvebu_uart_clock_probe(struct platform_device *pdev)
1356 {
1357     static const char *const uart_clk_names[] = { "uart_1", "uart_2" };
1358     static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P",
1359                             "TBG-A-S", "TBG-B-S",
1360                             "xtal" };
1361     struct clk *parent_clks[ARRAY_SIZE(parent_clk_names)];
1362     struct mvebu_uart_clock_base *uart_clock_base;
1363     struct clk_hw_onecell_data *hw_clk_data;
1364     struct device *dev = &pdev->dev;
1365     int i, parent_clk_idx, ret;
1366     unsigned long div, rate;
1367     struct resource *res;
1368     unsigned int d1, d2;
1369 
1370     BUILD_BUG_ON(ARRAY_SIZE(uart_clk_names) !=
1371              ARRAY_SIZE(uart_clock_base->clocks));
1372     BUILD_BUG_ON(ARRAY_SIZE(parent_clk_names) !=
1373              ARRAY_SIZE(uart_clock_base->parent_rates));
1374 
1375     uart_clock_base = devm_kzalloc(dev,
1376                        sizeof(*uart_clock_base),
1377                        GFP_KERNEL);
1378     if (!uart_clock_base)
1379         return -ENOMEM;
1380 
1381     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382     if (!res) {
1383         dev_err(dev, "Couldn't get first register\n");
1384         return -ENOENT;
1385     }
1386 
1387     /*
1388      * UART Clock Control register (reg1 / UART_BRDV) is in the address
1389      * space of UART1 (standard UART variant), controls parent clock and
1390      * dividers for both UART1 and UART2 and is supplied via DT as the first
1391      * resource. Therefore use ioremap() rather than ioremap_resource() to
1392      * avoid conflicts with UART1 driver. Access to UART_BRDV is protected
1393      * by a lock shared between clock and UART driver.
1394      */
1395     uart_clock_base->reg1 = devm_ioremap(dev, res->start,
1396                          resource_size(res));
1397     if (!uart_clock_base->reg1)
1398         return -ENOMEM;
1399 
1400     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1401     if (!res) {
1402         dev_err(dev, "Couldn't get second register\n");
1403         return -ENOENT;
1404     }
1405 
1406     /*
1407      * UART 2 Baud Rate Divisor register (reg2 / UART_BRDV) is in address
1408      * space of UART2 (extended UART variant), controls only one UART2
1409      * specific divider and is supplied via DT as second resource.
1410      * Therefore use ioremap() rather than ioremap_resource() to avoid
1411      * conflicts with UART2 driver. Access to UART_BRDV is protected by a
1412      * by lock shared between clock and UART driver.
1413      */
1414     uart_clock_base->reg2 = devm_ioremap(dev, res->start,
1415                          resource_size(res));
1416     if (!uart_clock_base->reg2)
1417         return -ENOMEM;
1418 
1419     hw_clk_data = devm_kzalloc(dev,
1420                    struct_size(hw_clk_data, hws,
1421                            ARRAY_SIZE(uart_clk_names)),
1422                    GFP_KERNEL);
1423     if (!hw_clk_data)
1424         return -ENOMEM;
1425 
1426     hw_clk_data->num = ARRAY_SIZE(uart_clk_names);
1427     for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) {
1428         hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw;
1429         uart_clock_base->clocks[i].clock_idx = i;
1430     }
1431 
1432     parent_clk_idx = -1;
1433 
1434     for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) {
1435         parent_clks[i] = devm_clk_get(dev, parent_clk_names[i]);
1436         if (IS_ERR(parent_clks[i])) {
1437             if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER)
1438                 return -EPROBE_DEFER;
1439             dev_warn(dev, "Couldn't get the parent clock %s: %ld\n",
1440                  parent_clk_names[i], PTR_ERR(parent_clks[i]));
1441             continue;
1442         }
1443 
1444         ret = clk_prepare_enable(parent_clks[i]);
1445         if (ret) {
1446             dev_warn(dev, "Couldn't enable parent clock %s: %d\n",
1447                  parent_clk_names[i], ret);
1448             continue;
1449         }
1450         rate = clk_get_rate(parent_clks[i]);
1451         uart_clock_base->parent_rates[i] = rate;
1452 
1453         if (i != PARENT_CLOCK_XTAL) {
1454             /*
1455              * Calculate the smallest TBG d1 and d2 divisors that
1456              * still can provide 9600 baudrate.
1457              */
1458             d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1459                       BRDV_BAUD_MAX);
1460             if (d1 < 1)
1461                 d1 = 1;
1462             else if (d1 > CLK_TBG_DIV1_MAX)
1463                 d1 = CLK_TBG_DIV1_MAX;
1464 
1465             d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1466                       BRDV_BAUD_MAX * d1);
1467             if (d2 < 1)
1468                 d2 = 1;
1469             else if (d2 > CLK_TBG_DIV2_MAX)
1470                 d2 = CLK_TBG_DIV2_MAX;
1471         } else {
1472             /*
1473              * When UART clock uses XTAL clock as a source then it
1474              * is not possible to use d1 and d2 divisors.
1475              */
1476             d1 = d2 = 1;
1477         }
1478 
1479         /* Skip clock source which cannot provide 9600 baudrate */
1480         if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2)
1481             continue;
1482 
1483         /*
1484          * Choose TBG clock source with the smallest divisors. Use XTAL
1485          * clock source only in case TBG is not available as XTAL cannot
1486          * be used for baudrates higher than 230400.
1487          */
1488         if (parent_clk_idx == -1 ||
1489             (i != PARENT_CLOCK_XTAL && div > d1 * d2)) {
1490             parent_clk_idx = i;
1491             div = d1 * d2;
1492         }
1493     }
1494 
1495     for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) {
1496         if (i == parent_clk_idx || IS_ERR(parent_clks[i]))
1497             continue;
1498         clk_disable_unprepare(parent_clks[i]);
1499         devm_clk_put(dev, parent_clks[i]);
1500     }
1501 
1502     if (parent_clk_idx == -1) {
1503         dev_err(dev, "No usable parent clock\n");
1504         return -ENOENT;
1505     }
1506 
1507     uart_clock_base->parent_idx = parent_clk_idx;
1508     uart_clock_base->div = div;
1509 
1510     dev_notice(dev, "Using parent clock %s as base UART clock\n",
1511            __clk_get_name(parent_clks[parent_clk_idx]));
1512 
1513     for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) {
1514         ret = mvebu_uart_clock_register(dev,
1515                 &uart_clock_base->clocks[i],
1516                 uart_clk_names[i],
1517                 __clk_get_name(parent_clks[parent_clk_idx]));
1518         if (ret) {
1519             dev_err(dev, "Can't register UART clock %d: %d\n",
1520                 i, ret);
1521             return ret;
1522         }
1523     }
1524 
1525     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1526                        hw_clk_data);
1527 }
1528 
1529 static const struct of_device_id mvebu_uart_clock_of_match[] = {
1530     { .compatible = "marvell,armada-3700-uart-clock", },
1531     { }
1532 };
1533 
1534 static struct platform_driver mvebu_uart_clock_platform_driver = {
1535     .probe = mvebu_uart_clock_probe,
1536     .driver     = {
1537         .name   = "mvebu-uart-clock",
1538         .of_match_table = mvebu_uart_clock_of_match,
1539     },
1540 };
1541 
1542 static int __init mvebu_uart_init(void)
1543 {
1544     int ret;
1545 
1546     ret = uart_register_driver(&mvebu_uart_driver);
1547     if (ret)
1548         return ret;
1549 
1550     ret = platform_driver_register(&mvebu_uart_clock_platform_driver);
1551     if (ret) {
1552         uart_unregister_driver(&mvebu_uart_driver);
1553         return ret;
1554     }
1555 
1556     ret = platform_driver_register(&mvebu_uart_platform_driver);
1557     if (ret) {
1558         platform_driver_unregister(&mvebu_uart_clock_platform_driver);
1559         uart_unregister_driver(&mvebu_uart_driver);
1560         return ret;
1561     }
1562 
1563     return 0;
1564 }
1565 arch_initcall(mvebu_uart_init);
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