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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for msm7k serial device and console
0004  *
0005  * Copyright (C) 2007 Google, Inc.
0006  * Author: Robert Love <rlove@google.com>
0007  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/atomic.h>
0012 #include <linux/dma/qcom_adm.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/dmaengine.h>
0015 #include <linux/module.h>
0016 #include <linux/io.h>
0017 #include <linux/ioport.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/init.h>
0020 #include <linux/console.h>
0021 #include <linux/tty.h>
0022 #include <linux/tty_flip.h>
0023 #include <linux/serial_core.h>
0024 #include <linux/slab.h>
0025 #include <linux/clk.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/delay.h>
0028 #include <linux/of.h>
0029 #include <linux/of_device.h>
0030 #include <linux/wait.h>
0031 
0032 #define MSM_UART_MR1            0x0000
0033 
0034 #define MSM_UART_MR1_AUTO_RFR_LEVEL0    0x3F
0035 #define MSM_UART_MR1_AUTO_RFR_LEVEL1    0x3FF00
0036 #define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
0037 #define MSM_UART_MR1_RX_RDY_CTL     BIT(7)
0038 #define MSM_UART_MR1_CTS_CTL        BIT(6)
0039 
0040 #define MSM_UART_MR2            0x0004
0041 #define MSM_UART_MR2_ERROR_MODE     BIT(6)
0042 #define MSM_UART_MR2_BITS_PER_CHAR  0x30
0043 #define MSM_UART_MR2_BITS_PER_CHAR_5    (0x0 << 4)
0044 #define MSM_UART_MR2_BITS_PER_CHAR_6    (0x1 << 4)
0045 #define MSM_UART_MR2_BITS_PER_CHAR_7    (0x2 << 4)
0046 #define MSM_UART_MR2_BITS_PER_CHAR_8    (0x3 << 4)
0047 #define MSM_UART_MR2_STOP_BIT_LEN_ONE   (0x1 << 2)
0048 #define MSM_UART_MR2_STOP_BIT_LEN_TWO   (0x3 << 2)
0049 #define MSM_UART_MR2_PARITY_MODE_NONE   0x0
0050 #define MSM_UART_MR2_PARITY_MODE_ODD    0x1
0051 #define MSM_UART_MR2_PARITY_MODE_EVEN   0x2
0052 #define MSM_UART_MR2_PARITY_MODE_SPACE  0x3
0053 #define MSM_UART_MR2_PARITY_MODE    0x3
0054 
0055 #define MSM_UART_CSR            0x0008
0056 
0057 #define MSM_UART_TF         0x000C
0058 #define UARTDM_TF           0x0070
0059 
0060 #define MSM_UART_CR             0x0010
0061 #define MSM_UART_CR_CMD_NULL            (0 << 4)
0062 #define MSM_UART_CR_CMD_RESET_RX        (1 << 4)
0063 #define MSM_UART_CR_CMD_RESET_TX        (2 << 4)
0064 #define MSM_UART_CR_CMD_RESET_ERR       (3 << 4)
0065 #define MSM_UART_CR_CMD_RESET_BREAK_INT     (4 << 4)
0066 #define MSM_UART_CR_CMD_START_BREAK     (5 << 4)
0067 #define MSM_UART_CR_CMD_STOP_BREAK      (6 << 4)
0068 #define MSM_UART_CR_CMD_RESET_CTS       (7 << 4)
0069 #define MSM_UART_CR_CMD_RESET_STALE_INT     (8 << 4)
0070 #define MSM_UART_CR_CMD_PACKET_MODE     (9 << 4)
0071 #define MSM_UART_CR_CMD_MODE_RESET      (12 << 4)
0072 #define MSM_UART_CR_CMD_SET_RFR         (13 << 4)
0073 #define MSM_UART_CR_CMD_RESET_RFR       (14 << 4)
0074 #define MSM_UART_CR_CMD_PROTECTION_EN       (16 << 4)
0075 #define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
0076 #define MSM_UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
0077 #define MSM_UART_CR_CMD_FORCE_STALE     (4 << 8)
0078 #define MSM_UART_CR_CMD_RESET_TX_READY      (3 << 8)
0079 #define MSM_UART_CR_TX_DISABLE          BIT(3)
0080 #define MSM_UART_CR_TX_ENABLE           BIT(2)
0081 #define MSM_UART_CR_RX_DISABLE          BIT(1)
0082 #define MSM_UART_CR_RX_ENABLE           BIT(0)
0083 #define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
0084 
0085 #define MSM_UART_IMR            0x0014
0086 #define MSM_UART_IMR_TXLEV      BIT(0)
0087 #define MSM_UART_IMR_RXSTALE        BIT(3)
0088 #define MSM_UART_IMR_RXLEV      BIT(4)
0089 #define MSM_UART_IMR_DELTA_CTS      BIT(5)
0090 #define MSM_UART_IMR_CURRENT_CTS    BIT(6)
0091 #define MSM_UART_IMR_RXBREAK_START  BIT(10)
0092 
0093 #define MSM_UART_IPR_RXSTALE_LAST       0x20
0094 #define MSM_UART_IPR_STALE_LSB          0x1F
0095 #define MSM_UART_IPR_STALE_TIMEOUT_MSB      0x3FF80
0096 #define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB   0xFFFFFF80
0097 
0098 #define MSM_UART_IPR            0x0018
0099 #define MSM_UART_TFWR           0x001C
0100 #define MSM_UART_RFWR           0x0020
0101 #define MSM_UART_HCR            0x0024
0102 
0103 #define MSM_UART_MREG           0x0028
0104 #define MSM_UART_NREG           0x002C
0105 #define MSM_UART_DREG           0x0030
0106 #define MSM_UART_MNDREG         0x0034
0107 #define MSM_UART_IRDA           0x0038
0108 #define MSM_UART_MISR_MODE      0x0040
0109 #define MSM_UART_MISR_RESET     0x0044
0110 #define MSM_UART_MISR_EXPORT        0x0048
0111 #define MSM_UART_MISR_VAL       0x004C
0112 #define MSM_UART_TEST_CTRL      0x0050
0113 
0114 #define MSM_UART_SR         0x0008
0115 #define MSM_UART_SR_HUNT_CHAR       BIT(7)
0116 #define MSM_UART_SR_RX_BREAK        BIT(6)
0117 #define MSM_UART_SR_PAR_FRAME_ERR   BIT(5)
0118 #define MSM_UART_SR_OVERRUN     BIT(4)
0119 #define MSM_UART_SR_TX_EMPTY        BIT(3)
0120 #define MSM_UART_SR_TX_READY        BIT(2)
0121 #define MSM_UART_SR_RX_FULL     BIT(1)
0122 #define MSM_UART_SR_RX_READY        BIT(0)
0123 
0124 #define MSM_UART_RF         0x000C
0125 #define UARTDM_RF           0x0070
0126 #define MSM_UART_MISR           0x0010
0127 #define MSM_UART_ISR            0x0014
0128 #define MSM_UART_ISR_TX_READY       BIT(7)
0129 
0130 #define UARTDM_RXFS         0x50
0131 #define UARTDM_RXFS_BUF_SHIFT       0x7
0132 #define UARTDM_RXFS_BUF_MASK        0x7
0133 
0134 #define UARTDM_DMEN         0x3C
0135 #define UARTDM_DMEN_RX_SC_ENABLE    BIT(5)
0136 #define UARTDM_DMEN_TX_SC_ENABLE    BIT(4)
0137 
0138 #define UARTDM_DMEN_TX_BAM_ENABLE   BIT(2)  /* UARTDM_1P4 */
0139 #define UARTDM_DMEN_TX_DM_ENABLE    BIT(0)  /* < UARTDM_1P4 */
0140 
0141 #define UARTDM_DMEN_RX_BAM_ENABLE   BIT(3)  /* UARTDM_1P4 */
0142 #define UARTDM_DMEN_RX_DM_ENABLE    BIT(1)  /* < UARTDM_1P4 */
0143 
0144 #define UARTDM_DMRX         0x34
0145 #define UARTDM_NCF_TX           0x40
0146 #define UARTDM_RX_TOTAL_SNAP        0x38
0147 
0148 #define UARTDM_BURST_SIZE       16   /* in bytes */
0149 #define UARTDM_TX_AIGN(x)       ((x) & ~0x3) /* valid for > 1p3 */
0150 #define UARTDM_TX_MAX           256   /* in bytes, valid for <= 1p3 */
0151 #define UARTDM_RX_SIZE          (UART_XMIT_SIZE / 4)
0152 
0153 enum {
0154     UARTDM_1P1 = 1,
0155     UARTDM_1P2,
0156     UARTDM_1P3,
0157     UARTDM_1P4,
0158 };
0159 
0160 struct msm_dma {
0161     struct dma_chan     *chan;
0162     enum dma_data_direction dir;
0163     dma_addr_t      phys;
0164     unsigned char       *virt;
0165     dma_cookie_t        cookie;
0166     u32         enable_bit;
0167     unsigned int        count;
0168     struct dma_async_tx_descriptor  *desc;
0169 };
0170 
0171 struct msm_port {
0172     struct uart_port    uart;
0173     char            name[16];
0174     struct clk      *clk;
0175     struct clk      *pclk;
0176     unsigned int        imr;
0177     int         is_uartdm;
0178     unsigned int        old_snap_state;
0179     bool            break_detected;
0180     struct msm_dma      tx_dma;
0181     struct msm_dma      rx_dma;
0182 };
0183 
0184 static inline struct msm_port *to_msm_port(struct uart_port *up)
0185 {
0186     return container_of(up, struct msm_port, uart);
0187 }
0188 
0189 static
0190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
0191 {
0192     writel_relaxed(val, port->membase + off);
0193 }
0194 
0195 static
0196 unsigned int msm_read(struct uart_port *port, unsigned int off)
0197 {
0198     return readl_relaxed(port->membase + off);
0199 }
0200 
0201 /*
0202  * Setup the MND registers to use the TCXO clock.
0203  */
0204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
0205 {
0206     msm_write(port, 0x06, MSM_UART_MREG);
0207     msm_write(port, 0xF1, MSM_UART_NREG);
0208     msm_write(port, 0x0F, MSM_UART_DREG);
0209     msm_write(port, 0x1A, MSM_UART_MNDREG);
0210     port->uartclk = 1843200;
0211 }
0212 
0213 /*
0214  * Setup the MND registers to use the TCXO clock divided by 4.
0215  */
0216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
0217 {
0218     msm_write(port, 0x18, MSM_UART_MREG);
0219     msm_write(port, 0xF6, MSM_UART_NREG);
0220     msm_write(port, 0x0F, MSM_UART_DREG);
0221     msm_write(port, 0x0A, MSM_UART_MNDREG);
0222     port->uartclk = 1843200;
0223 }
0224 
0225 static void msm_serial_set_mnd_regs(struct uart_port *port)
0226 {
0227     struct msm_port *msm_port = to_msm_port(port);
0228 
0229     /*
0230      * These registers don't exist so we change the clk input rate
0231      * on uartdm hardware instead
0232      */
0233     if (msm_port->is_uartdm)
0234         return;
0235 
0236     if (port->uartclk == 19200000)
0237         msm_serial_set_mnd_regs_tcxo(port);
0238     else if (port->uartclk == 4800000)
0239         msm_serial_set_mnd_regs_tcxoby4(port);
0240 }
0241 
0242 static void msm_handle_tx(struct uart_port *port);
0243 static void msm_start_rx_dma(struct msm_port *msm_port);
0244 
0245 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
0246 {
0247     struct device *dev = port->dev;
0248     unsigned int mapped;
0249     u32 val;
0250 
0251     mapped = dma->count;
0252     dma->count = 0;
0253 
0254     dmaengine_terminate_all(dma->chan);
0255 
0256     /*
0257      * DMA Stall happens if enqueue and flush command happens concurrently.
0258      * For example before changing the baud rate/protocol configuration and
0259      * sending flush command to ADM, disable the channel of UARTDM.
0260      * Note: should not reset the receiver here immediately as it is not
0261      * suggested to do disable/reset or reset/disable at the same time.
0262      */
0263     val = msm_read(port, UARTDM_DMEN);
0264     val &= ~dma->enable_bit;
0265     msm_write(port, val, UARTDM_DMEN);
0266 
0267     if (mapped)
0268         dma_unmap_single(dev, dma->phys, mapped, dma->dir);
0269 }
0270 
0271 static void msm_release_dma(struct msm_port *msm_port)
0272 {
0273     struct msm_dma *dma;
0274 
0275     dma = &msm_port->tx_dma;
0276     if (dma->chan) {
0277         msm_stop_dma(&msm_port->uart, dma);
0278         dma_release_channel(dma->chan);
0279     }
0280 
0281     memset(dma, 0, sizeof(*dma));
0282 
0283     dma = &msm_port->rx_dma;
0284     if (dma->chan) {
0285         msm_stop_dma(&msm_port->uart, dma);
0286         dma_release_channel(dma->chan);
0287         kfree(dma->virt);
0288     }
0289 
0290     memset(dma, 0, sizeof(*dma));
0291 }
0292 
0293 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
0294 {
0295     struct device *dev = msm_port->uart.dev;
0296     struct dma_slave_config conf;
0297     struct qcom_adm_peripheral_config periph_conf = {};
0298     struct msm_dma *dma;
0299     u32 crci = 0;
0300     int ret;
0301 
0302     dma = &msm_port->tx_dma;
0303 
0304     /* allocate DMA resources, if available */
0305     dma->chan = dma_request_chan(dev, "tx");
0306     if (IS_ERR(dma->chan))
0307         goto no_tx;
0308 
0309     of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
0310 
0311     memset(&conf, 0, sizeof(conf));
0312     conf.direction = DMA_MEM_TO_DEV;
0313     conf.device_fc = true;
0314     conf.dst_addr = base + UARTDM_TF;
0315     conf.dst_maxburst = UARTDM_BURST_SIZE;
0316     if (crci) {
0317         conf.peripheral_config = &periph_conf;
0318         conf.peripheral_size = sizeof(periph_conf);
0319         periph_conf.crci = crci;
0320     }
0321 
0322     ret = dmaengine_slave_config(dma->chan, &conf);
0323     if (ret)
0324         goto rel_tx;
0325 
0326     dma->dir = DMA_TO_DEVICE;
0327 
0328     if (msm_port->is_uartdm < UARTDM_1P4)
0329         dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
0330     else
0331         dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
0332 
0333     return;
0334 
0335 rel_tx:
0336     dma_release_channel(dma->chan);
0337 no_tx:
0338     memset(dma, 0, sizeof(*dma));
0339 }
0340 
0341 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
0342 {
0343     struct device *dev = msm_port->uart.dev;
0344     struct dma_slave_config conf;
0345     struct qcom_adm_peripheral_config periph_conf = {};
0346     struct msm_dma *dma;
0347     u32 crci = 0;
0348     int ret;
0349 
0350     dma = &msm_port->rx_dma;
0351 
0352     /* allocate DMA resources, if available */
0353     dma->chan = dma_request_chan(dev, "rx");
0354     if (IS_ERR(dma->chan))
0355         goto no_rx;
0356 
0357     of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
0358 
0359     dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
0360     if (!dma->virt)
0361         goto rel_rx;
0362 
0363     memset(&conf, 0, sizeof(conf));
0364     conf.direction = DMA_DEV_TO_MEM;
0365     conf.device_fc = true;
0366     conf.src_addr = base + UARTDM_RF;
0367     conf.src_maxburst = UARTDM_BURST_SIZE;
0368     if (crci) {
0369         conf.peripheral_config = &periph_conf;
0370         conf.peripheral_size = sizeof(periph_conf);
0371         periph_conf.crci = crci;
0372     }
0373 
0374     ret = dmaengine_slave_config(dma->chan, &conf);
0375     if (ret)
0376         goto err;
0377 
0378     dma->dir = DMA_FROM_DEVICE;
0379 
0380     if (msm_port->is_uartdm < UARTDM_1P4)
0381         dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
0382     else
0383         dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
0384 
0385     return;
0386 err:
0387     kfree(dma->virt);
0388 rel_rx:
0389     dma_release_channel(dma->chan);
0390 no_rx:
0391     memset(dma, 0, sizeof(*dma));
0392 }
0393 
0394 static inline void msm_wait_for_xmitr(struct uart_port *port)
0395 {
0396     unsigned int timeout = 500000;
0397 
0398     while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) {
0399         if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY)
0400             break;
0401         udelay(1);
0402         if (!timeout--)
0403             break;
0404     }
0405     msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
0406 }
0407 
0408 static void msm_stop_tx(struct uart_port *port)
0409 {
0410     struct msm_port *msm_port = to_msm_port(port);
0411 
0412     msm_port->imr &= ~MSM_UART_IMR_TXLEV;
0413     msm_write(port, msm_port->imr, MSM_UART_IMR);
0414 }
0415 
0416 static void msm_start_tx(struct uart_port *port)
0417 {
0418     struct msm_port *msm_port = to_msm_port(port);
0419     struct msm_dma *dma = &msm_port->tx_dma;
0420 
0421     /* Already started in DMA mode */
0422     if (dma->count)
0423         return;
0424 
0425     msm_port->imr |= MSM_UART_IMR_TXLEV;
0426     msm_write(port, msm_port->imr, MSM_UART_IMR);
0427 }
0428 
0429 static void msm_reset_dm_count(struct uart_port *port, int count)
0430 {
0431     msm_wait_for_xmitr(port);
0432     msm_write(port, count, UARTDM_NCF_TX);
0433     msm_read(port, UARTDM_NCF_TX);
0434 }
0435 
0436 static void msm_complete_tx_dma(void *args)
0437 {
0438     struct msm_port *msm_port = args;
0439     struct uart_port *port = &msm_port->uart;
0440     struct circ_buf *xmit = &port->state->xmit;
0441     struct msm_dma *dma = &msm_port->tx_dma;
0442     struct dma_tx_state state;
0443     unsigned long flags;
0444     unsigned int count;
0445     u32 val;
0446 
0447     spin_lock_irqsave(&port->lock, flags);
0448 
0449     /* Already stopped */
0450     if (!dma->count)
0451         goto done;
0452 
0453     dmaengine_tx_status(dma->chan, dma->cookie, &state);
0454 
0455     dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
0456 
0457     val = msm_read(port, UARTDM_DMEN);
0458     val &= ~dma->enable_bit;
0459     msm_write(port, val, UARTDM_DMEN);
0460 
0461     if (msm_port->is_uartdm > UARTDM_1P3) {
0462         msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
0463         msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
0464     }
0465 
0466     count = dma->count - state.residue;
0467     port->icount.tx += count;
0468     dma->count = 0;
0469 
0470     xmit->tail += count;
0471     xmit->tail &= UART_XMIT_SIZE - 1;
0472 
0473     /* Restore "Tx FIFO below watermark" interrupt */
0474     msm_port->imr |= MSM_UART_IMR_TXLEV;
0475     msm_write(port, msm_port->imr, MSM_UART_IMR);
0476 
0477     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0478         uart_write_wakeup(port);
0479 
0480     msm_handle_tx(port);
0481 done:
0482     spin_unlock_irqrestore(&port->lock, flags);
0483 }
0484 
0485 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
0486 {
0487     struct circ_buf *xmit = &msm_port->uart.state->xmit;
0488     struct uart_port *port = &msm_port->uart;
0489     struct msm_dma *dma = &msm_port->tx_dma;
0490     void *cpu_addr;
0491     int ret;
0492     u32 val;
0493 
0494     cpu_addr = &xmit->buf[xmit->tail];
0495 
0496     dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
0497     ret = dma_mapping_error(port->dev, dma->phys);
0498     if (ret)
0499         return ret;
0500 
0501     dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
0502                         count, DMA_MEM_TO_DEV,
0503                         DMA_PREP_INTERRUPT |
0504                         DMA_PREP_FENCE);
0505     if (!dma->desc) {
0506         ret = -EIO;
0507         goto unmap;
0508     }
0509 
0510     dma->desc->callback = msm_complete_tx_dma;
0511     dma->desc->callback_param = msm_port;
0512 
0513     dma->cookie = dmaengine_submit(dma->desc);
0514     ret = dma_submit_error(dma->cookie);
0515     if (ret)
0516         goto unmap;
0517 
0518     /*
0519      * Using DMA complete for Tx FIFO reload, no need for
0520      * "Tx FIFO below watermark" one, disable it
0521      */
0522     msm_port->imr &= ~MSM_UART_IMR_TXLEV;
0523     msm_write(port, msm_port->imr, MSM_UART_IMR);
0524 
0525     dma->count = count;
0526 
0527     val = msm_read(port, UARTDM_DMEN);
0528     val |= dma->enable_bit;
0529 
0530     if (msm_port->is_uartdm < UARTDM_1P4)
0531         msm_write(port, val, UARTDM_DMEN);
0532 
0533     msm_reset_dm_count(port, count);
0534 
0535     if (msm_port->is_uartdm > UARTDM_1P3)
0536         msm_write(port, val, UARTDM_DMEN);
0537 
0538     dma_async_issue_pending(dma->chan);
0539     return 0;
0540 unmap:
0541     dma_unmap_single(port->dev, dma->phys, count, dma->dir);
0542     return ret;
0543 }
0544 
0545 static void msm_complete_rx_dma(void *args)
0546 {
0547     struct msm_port *msm_port = args;
0548     struct uart_port *port = &msm_port->uart;
0549     struct tty_port *tport = &port->state->port;
0550     struct msm_dma *dma = &msm_port->rx_dma;
0551     int count = 0, i, sysrq;
0552     unsigned long flags;
0553     u32 val;
0554 
0555     spin_lock_irqsave(&port->lock, flags);
0556 
0557     /* Already stopped */
0558     if (!dma->count)
0559         goto done;
0560 
0561     val = msm_read(port, UARTDM_DMEN);
0562     val &= ~dma->enable_bit;
0563     msm_write(port, val, UARTDM_DMEN);
0564 
0565     if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) {
0566         port->icount.overrun++;
0567         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0568         msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
0569     }
0570 
0571     count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
0572 
0573     port->icount.rx += count;
0574 
0575     dma->count = 0;
0576 
0577     dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
0578 
0579     for (i = 0; i < count; i++) {
0580         char flag = TTY_NORMAL;
0581 
0582         if (msm_port->break_detected && dma->virt[i] == 0) {
0583             port->icount.brk++;
0584             flag = TTY_BREAK;
0585             msm_port->break_detected = false;
0586             if (uart_handle_break(port))
0587                 continue;
0588         }
0589 
0590         if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
0591             flag = TTY_NORMAL;
0592 
0593         spin_unlock_irqrestore(&port->lock, flags);
0594         sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
0595         spin_lock_irqsave(&port->lock, flags);
0596         if (!sysrq)
0597             tty_insert_flip_char(tport, dma->virt[i], flag);
0598     }
0599 
0600     msm_start_rx_dma(msm_port);
0601 done:
0602     spin_unlock_irqrestore(&port->lock, flags);
0603 
0604     if (count)
0605         tty_flip_buffer_push(tport);
0606 }
0607 
0608 static void msm_start_rx_dma(struct msm_port *msm_port)
0609 {
0610     struct msm_dma *dma = &msm_port->rx_dma;
0611     struct uart_port *uart = &msm_port->uart;
0612     u32 val;
0613     int ret;
0614 
0615     if (IS_ENABLED(CONFIG_CONSOLE_POLL))
0616         return;
0617 
0618     if (!dma->chan)
0619         return;
0620 
0621     dma->phys = dma_map_single(uart->dev, dma->virt,
0622                    UARTDM_RX_SIZE, dma->dir);
0623     ret = dma_mapping_error(uart->dev, dma->phys);
0624     if (ret)
0625         goto sw_mode;
0626 
0627     dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
0628                         UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
0629                         DMA_PREP_INTERRUPT);
0630     if (!dma->desc)
0631         goto unmap;
0632 
0633     dma->desc->callback = msm_complete_rx_dma;
0634     dma->desc->callback_param = msm_port;
0635 
0636     dma->cookie = dmaengine_submit(dma->desc);
0637     ret = dma_submit_error(dma->cookie);
0638     if (ret)
0639         goto unmap;
0640     /*
0641      * Using DMA for FIFO off-load, no need for "Rx FIFO over
0642      * watermark" or "stale" interrupts, disable them
0643      */
0644     msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
0645 
0646     /*
0647      * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
0648      * we need RXSTALE to flush input DMA fifo to memory
0649      */
0650     if (msm_port->is_uartdm < UARTDM_1P4)
0651         msm_port->imr |= MSM_UART_IMR_RXSTALE;
0652 
0653     msm_write(uart, msm_port->imr, MSM_UART_IMR);
0654 
0655     dma->count = UARTDM_RX_SIZE;
0656 
0657     dma_async_issue_pending(dma->chan);
0658 
0659     msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
0660     msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
0661 
0662     val = msm_read(uart, UARTDM_DMEN);
0663     val |= dma->enable_bit;
0664 
0665     if (msm_port->is_uartdm < UARTDM_1P4)
0666         msm_write(uart, val, UARTDM_DMEN);
0667 
0668     msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
0669 
0670     if (msm_port->is_uartdm > UARTDM_1P3)
0671         msm_write(uart, val, UARTDM_DMEN);
0672 
0673     return;
0674 unmap:
0675     dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
0676 
0677 sw_mode:
0678     /*
0679      * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
0680      * receiver must be reset.
0681      */
0682     msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
0683     msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
0684 
0685     msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
0686     msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
0687     msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
0688 
0689     /* Re-enable RX interrupts */
0690     msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE;
0691     msm_write(uart, msm_port->imr, MSM_UART_IMR);
0692 }
0693 
0694 static void msm_stop_rx(struct uart_port *port)
0695 {
0696     struct msm_port *msm_port = to_msm_port(port);
0697     struct msm_dma *dma = &msm_port->rx_dma;
0698 
0699     msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
0700     msm_write(port, msm_port->imr, MSM_UART_IMR);
0701 
0702     if (dma->chan)
0703         msm_stop_dma(port, dma);
0704 }
0705 
0706 static void msm_enable_ms(struct uart_port *port)
0707 {
0708     struct msm_port *msm_port = to_msm_port(port);
0709 
0710     msm_port->imr |= MSM_UART_IMR_DELTA_CTS;
0711     msm_write(port, msm_port->imr, MSM_UART_IMR);
0712 }
0713 
0714 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
0715     __must_hold(&port->lock)
0716 {
0717     struct tty_port *tport = &port->state->port;
0718     unsigned int sr;
0719     int count = 0;
0720     struct msm_port *msm_port = to_msm_port(port);
0721 
0722     if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
0723         port->icount.overrun++;
0724         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0725         msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
0726     }
0727 
0728     if (misr & MSM_UART_IMR_RXSTALE) {
0729         count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
0730             msm_port->old_snap_state;
0731         msm_port->old_snap_state = 0;
0732     } else {
0733         count = 4 * (msm_read(port, MSM_UART_RFWR));
0734         msm_port->old_snap_state += count;
0735     }
0736 
0737     /* TODO: Precise error reporting */
0738 
0739     port->icount.rx += count;
0740 
0741     while (count > 0) {
0742         unsigned char buf[4];
0743         int sysrq, r_count, i;
0744 
0745         sr = msm_read(port, MSM_UART_SR);
0746         if ((sr & MSM_UART_SR_RX_READY) == 0) {
0747             msm_port->old_snap_state -= count;
0748             break;
0749         }
0750 
0751         ioread32_rep(port->membase + UARTDM_RF, buf, 1);
0752         r_count = min_t(int, count, sizeof(buf));
0753 
0754         for (i = 0; i < r_count; i++) {
0755             char flag = TTY_NORMAL;
0756 
0757             if (msm_port->break_detected && buf[i] == 0) {
0758                 port->icount.brk++;
0759                 flag = TTY_BREAK;
0760                 msm_port->break_detected = false;
0761                 if (uart_handle_break(port))
0762                     continue;
0763             }
0764 
0765             if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
0766                 flag = TTY_NORMAL;
0767 
0768             spin_unlock(&port->lock);
0769             sysrq = uart_handle_sysrq_char(port, buf[i]);
0770             spin_lock(&port->lock);
0771             if (!sysrq)
0772                 tty_insert_flip_char(tport, buf[i], flag);
0773         }
0774         count -= r_count;
0775     }
0776 
0777     tty_flip_buffer_push(tport);
0778 
0779     if (misr & (MSM_UART_IMR_RXSTALE))
0780         msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
0781     msm_write(port, 0xFFFFFF, UARTDM_DMRX);
0782     msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
0783 
0784     /* Try to use DMA */
0785     msm_start_rx_dma(msm_port);
0786 }
0787 
0788 static void msm_handle_rx(struct uart_port *port)
0789     __must_hold(&port->lock)
0790 {
0791     struct tty_port *tport = &port->state->port;
0792     unsigned int sr;
0793 
0794     /*
0795      * Handle overrun. My understanding of the hardware is that overrun
0796      * is not tied to the RX buffer, so we handle the case out of band.
0797      */
0798     if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
0799         port->icount.overrun++;
0800         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0801         msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
0802     }
0803 
0804     /* and now the main RX loop */
0805     while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) {
0806         unsigned int c;
0807         char flag = TTY_NORMAL;
0808         int sysrq;
0809 
0810         c = msm_read(port, MSM_UART_RF);
0811 
0812         if (sr & MSM_UART_SR_RX_BREAK) {
0813             port->icount.brk++;
0814             if (uart_handle_break(port))
0815                 continue;
0816         } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) {
0817             port->icount.frame++;
0818         } else {
0819             port->icount.rx++;
0820         }
0821 
0822         /* Mask conditions we're ignorning. */
0823         sr &= port->read_status_mask;
0824 
0825         if (sr & MSM_UART_SR_RX_BREAK)
0826             flag = TTY_BREAK;
0827         else if (sr & MSM_UART_SR_PAR_FRAME_ERR)
0828             flag = TTY_FRAME;
0829 
0830         spin_unlock(&port->lock);
0831         sysrq = uart_handle_sysrq_char(port, c);
0832         spin_lock(&port->lock);
0833         if (!sysrq)
0834             tty_insert_flip_char(tport, c, flag);
0835     }
0836 
0837     tty_flip_buffer_push(tport);
0838 }
0839 
0840 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
0841 {
0842     struct circ_buf *xmit = &port->state->xmit;
0843     struct msm_port *msm_port = to_msm_port(port);
0844     unsigned int num_chars;
0845     unsigned int tf_pointer = 0;
0846     void __iomem *tf;
0847 
0848     if (msm_port->is_uartdm)
0849         tf = port->membase + UARTDM_TF;
0850     else
0851         tf = port->membase + MSM_UART_TF;
0852 
0853     if (tx_count && msm_port->is_uartdm)
0854         msm_reset_dm_count(port, tx_count);
0855 
0856     while (tf_pointer < tx_count) {
0857         int i;
0858         char buf[4] = { 0 };
0859 
0860         if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
0861             break;
0862 
0863         if (msm_port->is_uartdm)
0864             num_chars = min(tx_count - tf_pointer,
0865                     (unsigned int)sizeof(buf));
0866         else
0867             num_chars = 1;
0868 
0869         for (i = 0; i < num_chars; i++) {
0870             buf[i] = xmit->buf[xmit->tail + i];
0871             port->icount.tx++;
0872         }
0873 
0874         iowrite32_rep(tf, buf, 1);
0875         xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
0876         tf_pointer += num_chars;
0877     }
0878 
0879     /* disable tx interrupts if nothing more to send */
0880     if (uart_circ_empty(xmit))
0881         msm_stop_tx(port);
0882 
0883     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0884         uart_write_wakeup(port);
0885 }
0886 
0887 static void msm_handle_tx(struct uart_port *port)
0888 {
0889     struct msm_port *msm_port = to_msm_port(port);
0890     struct circ_buf *xmit = &msm_port->uart.state->xmit;
0891     struct msm_dma *dma = &msm_port->tx_dma;
0892     unsigned int pio_count, dma_count, dma_min;
0893     char buf[4] = { 0 };
0894     void __iomem *tf;
0895     int err = 0;
0896 
0897     if (port->x_char) {
0898         if (msm_port->is_uartdm)
0899             tf = port->membase + UARTDM_TF;
0900         else
0901             tf = port->membase + MSM_UART_TF;
0902 
0903         buf[0] = port->x_char;
0904 
0905         if (msm_port->is_uartdm)
0906             msm_reset_dm_count(port, 1);
0907 
0908         iowrite32_rep(tf, buf, 1);
0909         port->icount.tx++;
0910         port->x_char = 0;
0911         return;
0912     }
0913 
0914     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0915         msm_stop_tx(port);
0916         return;
0917     }
0918 
0919     pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
0920     dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
0921 
0922     dma_min = 1;    /* Always DMA */
0923     if (msm_port->is_uartdm > UARTDM_1P3) {
0924         dma_count = UARTDM_TX_AIGN(dma_count);
0925         dma_min = UARTDM_BURST_SIZE;
0926     } else {
0927         if (dma_count > UARTDM_TX_MAX)
0928             dma_count = UARTDM_TX_MAX;
0929     }
0930 
0931     if (pio_count > port->fifosize)
0932         pio_count = port->fifosize;
0933 
0934     if (!dma->chan || dma_count < dma_min)
0935         msm_handle_tx_pio(port, pio_count);
0936     else
0937         err = msm_handle_tx_dma(msm_port, dma_count);
0938 
0939     if (err)    /* fall back to PIO mode */
0940         msm_handle_tx_pio(port, pio_count);
0941 }
0942 
0943 static void msm_handle_delta_cts(struct uart_port *port)
0944 {
0945     msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
0946     port->icount.cts++;
0947     wake_up_interruptible(&port->state->port.delta_msr_wait);
0948 }
0949 
0950 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
0951 {
0952     struct uart_port *port = dev_id;
0953     struct msm_port *msm_port = to_msm_port(port);
0954     struct msm_dma *dma = &msm_port->rx_dma;
0955     unsigned long flags;
0956     unsigned int misr;
0957     u32 val;
0958 
0959     spin_lock_irqsave(&port->lock, flags);
0960     misr = msm_read(port, MSM_UART_MISR);
0961     msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
0962 
0963     if (misr & MSM_UART_IMR_RXBREAK_START) {
0964         msm_port->break_detected = true;
0965         msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
0966     }
0967 
0968     if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
0969         if (dma->count) {
0970             val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE;
0971             msm_write(port, val, MSM_UART_CR);
0972             val = MSM_UART_CR_CMD_RESET_STALE_INT;
0973             msm_write(port, val, MSM_UART_CR);
0974             /*
0975              * Flush DMA input fifo to memory, this will also
0976              * trigger DMA RX completion
0977              */
0978             dmaengine_terminate_all(dma->chan);
0979         } else if (msm_port->is_uartdm) {
0980             msm_handle_rx_dm(port, misr);
0981         } else {
0982             msm_handle_rx(port);
0983         }
0984     }
0985     if (misr & MSM_UART_IMR_TXLEV)
0986         msm_handle_tx(port);
0987     if (misr & MSM_UART_IMR_DELTA_CTS)
0988         msm_handle_delta_cts(port);
0989 
0990     msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
0991     spin_unlock_irqrestore(&port->lock, flags);
0992 
0993     return IRQ_HANDLED;
0994 }
0995 
0996 static unsigned int msm_tx_empty(struct uart_port *port)
0997 {
0998     return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
0999 }
1000 
1001 static unsigned int msm_get_mctrl(struct uart_port *port)
1002 {
1003     return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
1004 }
1005 
1006 static void msm_reset(struct uart_port *port)
1007 {
1008     struct msm_port *msm_port = to_msm_port(port);
1009     unsigned int mr;
1010 
1011     /* reset everything */
1012     msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
1013     msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
1014     msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
1015     msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
1016     msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
1017     msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1018     mr = msm_read(port, MSM_UART_MR1);
1019     mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1020     msm_write(port, mr, MSM_UART_MR1);
1021 
1022     /* Disable DM modes */
1023     if (msm_port->is_uartdm)
1024         msm_write(port, 0, UARTDM_DMEN);
1025 }
1026 
1027 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1028 {
1029     unsigned int mr;
1030 
1031     mr = msm_read(port, MSM_UART_MR1);
1032 
1033     if (!(mctrl & TIOCM_RTS)) {
1034         mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1035         msm_write(port, mr, MSM_UART_MR1);
1036         msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1037     } else {
1038         mr |= MSM_UART_MR1_RX_RDY_CTL;
1039         msm_write(port, mr, MSM_UART_MR1);
1040     }
1041 }
1042 
1043 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1044 {
1045     if (break_ctl)
1046         msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
1047     else
1048         msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
1049 }
1050 
1051 struct msm_baud_map {
1052     u16 divisor;
1053     u8  code;
1054     u8  rxstale;
1055 };
1056 
1057 static const struct msm_baud_map *
1058 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1059            unsigned long *rate)
1060 {
1061     struct msm_port *msm_port = to_msm_port(port);
1062     unsigned int divisor, result;
1063     unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1064     const struct msm_baud_map *entry, *end, *best;
1065     static const struct msm_baud_map table[] = {
1066         {    1, 0xff, 31 },
1067         {    2, 0xee, 16 },
1068         {    3, 0xdd,  8 },
1069         {    4, 0xcc,  6 },
1070         {    6, 0xbb,  6 },
1071         {    8, 0xaa,  6 },
1072         {   12, 0x99,  6 },
1073         {   16, 0x88,  1 },
1074         {   24, 0x77,  1 },
1075         {   32, 0x66,  1 },
1076         {   48, 0x55,  1 },
1077         {   96, 0x44,  1 },
1078         {  192, 0x33,  1 },
1079         {  384, 0x22,  1 },
1080         {  768, 0x11,  1 },
1081         { 1536, 0x00,  1 },
1082     };
1083 
1084     best = table; /* Default to smallest divider */
1085     target = clk_round_rate(msm_port->clk, 16 * baud);
1086     divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1087 
1088     end = table + ARRAY_SIZE(table);
1089     entry = table;
1090     while (entry < end) {
1091         if (entry->divisor <= divisor) {
1092             result = target / entry->divisor / 16;
1093             diff = abs(result - baud);
1094 
1095             /* Keep track of best entry */
1096             if (diff < best_diff) {
1097                 best_diff = diff;
1098                 best = entry;
1099                 best_rate = target;
1100             }
1101 
1102             if (result == baud)
1103                 break;
1104         } else if (entry->divisor > divisor) {
1105             old = target;
1106             target = clk_round_rate(msm_port->clk, old + 1);
1107             /*
1108              * The rate didn't get any faster so we can't do
1109              * better at dividing it down
1110              */
1111             if (target == old)
1112                 break;
1113 
1114             /* Start the divisor search over at this new rate */
1115             entry = table;
1116             divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1117             continue;
1118         }
1119         entry++;
1120     }
1121 
1122     *rate = best_rate;
1123     return best;
1124 }
1125 
1126 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1127                  unsigned long *saved_flags)
1128 {
1129     unsigned int rxstale, watermark, mask;
1130     struct msm_port *msm_port = to_msm_port(port);
1131     const struct msm_baud_map *entry;
1132     unsigned long flags, rate;
1133 
1134     flags = *saved_flags;
1135     spin_unlock_irqrestore(&port->lock, flags);
1136 
1137     entry = msm_find_best_baud(port, baud, &rate);
1138     clk_set_rate(msm_port->clk, rate);
1139     baud = rate / 16 / entry->divisor;
1140 
1141     spin_lock_irqsave(&port->lock, flags);
1142     *saved_flags = flags;
1143     port->uartclk = rate;
1144 
1145     msm_write(port, entry->code, MSM_UART_CSR);
1146 
1147     /* RX stale watermark */
1148     rxstale = entry->rxstale;
1149     watermark = MSM_UART_IPR_STALE_LSB & rxstale;
1150     if (msm_port->is_uartdm) {
1151         mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB;
1152     } else {
1153         watermark |= MSM_UART_IPR_RXSTALE_LAST;
1154         mask = MSM_UART_IPR_STALE_TIMEOUT_MSB;
1155     }
1156 
1157     watermark |= mask & (rxstale << 2);
1158 
1159     msm_write(port, watermark, MSM_UART_IPR);
1160 
1161     /* set RX watermark */
1162     watermark = (port->fifosize * 3) / 4;
1163     msm_write(port, watermark, MSM_UART_RFWR);
1164 
1165     /* set TX watermark */
1166     msm_write(port, 10, MSM_UART_TFWR);
1167 
1168     msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
1169     msm_reset(port);
1170 
1171     /* Enable RX and TX */
1172     msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
1173 
1174     /* turn on RX and CTS interrupts */
1175     msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE |
1176             MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START;
1177 
1178     msm_write(port, msm_port->imr, MSM_UART_IMR);
1179 
1180     if (msm_port->is_uartdm) {
1181         msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1182         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1183         msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1184     }
1185 
1186     return baud;
1187 }
1188 
1189 static void msm_init_clock(struct uart_port *port)
1190 {
1191     struct msm_port *msm_port = to_msm_port(port);
1192 
1193     clk_prepare_enable(msm_port->clk);
1194     clk_prepare_enable(msm_port->pclk);
1195     msm_serial_set_mnd_regs(port);
1196 }
1197 
1198 static int msm_startup(struct uart_port *port)
1199 {
1200     struct msm_port *msm_port = to_msm_port(port);
1201     unsigned int data, rfr_level, mask;
1202     int ret;
1203 
1204     snprintf(msm_port->name, sizeof(msm_port->name),
1205          "msm_serial%d", port->line);
1206 
1207     msm_init_clock(port);
1208 
1209     if (likely(port->fifosize > 12))
1210         rfr_level = port->fifosize - 12;
1211     else
1212         rfr_level = port->fifosize;
1213 
1214     /* set automatic RFR level */
1215     data = msm_read(port, MSM_UART_MR1);
1216 
1217     if (msm_port->is_uartdm)
1218         mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1;
1219     else
1220         mask = MSM_UART_MR1_AUTO_RFR_LEVEL1;
1221 
1222     data &= ~mask;
1223     data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0;
1224     data |= mask & (rfr_level << 2);
1225     data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1226     msm_write(port, data, MSM_UART_MR1);
1227 
1228     if (msm_port->is_uartdm) {
1229         msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1230         msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1231     }
1232 
1233     ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1234               msm_port->name, port);
1235     if (unlikely(ret))
1236         goto err_irq;
1237 
1238     return 0;
1239 
1240 err_irq:
1241     if (msm_port->is_uartdm)
1242         msm_release_dma(msm_port);
1243 
1244     clk_disable_unprepare(msm_port->pclk);
1245     clk_disable_unprepare(msm_port->clk);
1246 
1247     return ret;
1248 }
1249 
1250 static void msm_shutdown(struct uart_port *port)
1251 {
1252     struct msm_port *msm_port = to_msm_port(port);
1253 
1254     msm_port->imr = 0;
1255     msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
1256 
1257     if (msm_port->is_uartdm)
1258         msm_release_dma(msm_port);
1259 
1260     clk_disable_unprepare(msm_port->clk);
1261 
1262     free_irq(port->irq, port);
1263 }
1264 
1265 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1266                 struct ktermios *old)
1267 {
1268     struct msm_port *msm_port = to_msm_port(port);
1269     struct msm_dma *dma = &msm_port->rx_dma;
1270     unsigned long flags;
1271     unsigned int baud, mr;
1272 
1273     spin_lock_irqsave(&port->lock, flags);
1274 
1275     if (dma->chan) /* Terminate if any */
1276         msm_stop_dma(port, dma);
1277 
1278     /* calculate and set baud rate */
1279     baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1280     baud = msm_set_baud_rate(port, baud, &flags);
1281     if (tty_termios_baud_rate(termios))
1282         tty_termios_encode_baud_rate(termios, baud, baud);
1283 
1284     /* calculate parity */
1285     mr = msm_read(port, MSM_UART_MR2);
1286     mr &= ~MSM_UART_MR2_PARITY_MODE;
1287     if (termios->c_cflag & PARENB) {
1288         if (termios->c_cflag & PARODD)
1289             mr |= MSM_UART_MR2_PARITY_MODE_ODD;
1290         else if (termios->c_cflag & CMSPAR)
1291             mr |= MSM_UART_MR2_PARITY_MODE_SPACE;
1292         else
1293             mr |= MSM_UART_MR2_PARITY_MODE_EVEN;
1294     }
1295 
1296     /* calculate bits per char */
1297     mr &= ~MSM_UART_MR2_BITS_PER_CHAR;
1298     switch (termios->c_cflag & CSIZE) {
1299     case CS5:
1300         mr |= MSM_UART_MR2_BITS_PER_CHAR_5;
1301         break;
1302     case CS6:
1303         mr |= MSM_UART_MR2_BITS_PER_CHAR_6;
1304         break;
1305     case CS7:
1306         mr |= MSM_UART_MR2_BITS_PER_CHAR_7;
1307         break;
1308     case CS8:
1309     default:
1310         mr |= MSM_UART_MR2_BITS_PER_CHAR_8;
1311         break;
1312     }
1313 
1314     /* calculate stop bits */
1315     mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO);
1316     if (termios->c_cflag & CSTOPB)
1317         mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO;
1318     else
1319         mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE;
1320 
1321     /* set parity, bits per char, and stop bit */
1322     msm_write(port, mr, MSM_UART_MR2);
1323 
1324     /* calculate and set hardware flow control */
1325     mr = msm_read(port, MSM_UART_MR1);
1326     mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL);
1327     if (termios->c_cflag & CRTSCTS) {
1328         mr |= MSM_UART_MR1_CTS_CTL;
1329         mr |= MSM_UART_MR1_RX_RDY_CTL;
1330     }
1331     msm_write(port, mr, MSM_UART_MR1);
1332 
1333     /* Configure status bits to ignore based on termio flags. */
1334     port->read_status_mask = 0;
1335     if (termios->c_iflag & INPCK)
1336         port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR;
1337     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1338         port->read_status_mask |= MSM_UART_SR_RX_BREAK;
1339 
1340     uart_update_timeout(port, termios->c_cflag, baud);
1341 
1342     /* Try to use DMA */
1343     msm_start_rx_dma(msm_port);
1344 
1345     spin_unlock_irqrestore(&port->lock, flags);
1346 }
1347 
1348 static const char *msm_type(struct uart_port *port)
1349 {
1350     return "MSM";
1351 }
1352 
1353 static void msm_release_port(struct uart_port *port)
1354 {
1355     struct platform_device *pdev = to_platform_device(port->dev);
1356     struct resource *uart_resource;
1357     resource_size_t size;
1358 
1359     uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1360     if (unlikely(!uart_resource))
1361         return;
1362     size = resource_size(uart_resource);
1363 
1364     release_mem_region(port->mapbase, size);
1365     iounmap(port->membase);
1366     port->membase = NULL;
1367 }
1368 
1369 static int msm_request_port(struct uart_port *port)
1370 {
1371     struct platform_device *pdev = to_platform_device(port->dev);
1372     struct resource *uart_resource;
1373     resource_size_t size;
1374     int ret;
1375 
1376     uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1377     if (unlikely(!uart_resource))
1378         return -ENXIO;
1379 
1380     size = resource_size(uart_resource);
1381 
1382     if (!request_mem_region(port->mapbase, size, "msm_serial"))
1383         return -EBUSY;
1384 
1385     port->membase = ioremap(port->mapbase, size);
1386     if (!port->membase) {
1387         ret = -EBUSY;
1388         goto fail_release_port;
1389     }
1390 
1391     return 0;
1392 
1393 fail_release_port:
1394     release_mem_region(port->mapbase, size);
1395     return ret;
1396 }
1397 
1398 static void msm_config_port(struct uart_port *port, int flags)
1399 {
1400     int ret;
1401 
1402     if (flags & UART_CONFIG_TYPE) {
1403         port->type = PORT_MSM;
1404         ret = msm_request_port(port);
1405         if (ret)
1406             return;
1407     }
1408 }
1409 
1410 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1411 {
1412     if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1413         return -EINVAL;
1414     if (unlikely(port->irq != ser->irq))
1415         return -EINVAL;
1416     return 0;
1417 }
1418 
1419 static void msm_power(struct uart_port *port, unsigned int state,
1420               unsigned int oldstate)
1421 {
1422     struct msm_port *msm_port = to_msm_port(port);
1423 
1424     switch (state) {
1425     case 0:
1426         clk_prepare_enable(msm_port->clk);
1427         clk_prepare_enable(msm_port->pclk);
1428         break;
1429     case 3:
1430         clk_disable_unprepare(msm_port->clk);
1431         clk_disable_unprepare(msm_port->pclk);
1432         break;
1433     default:
1434         pr_err("msm_serial: Unknown PM state %d\n", state);
1435     }
1436 }
1437 
1438 #ifdef CONFIG_CONSOLE_POLL
1439 static int msm_poll_get_char_single(struct uart_port *port)
1440 {
1441     struct msm_port *msm_port = to_msm_port(port);
1442     unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF;
1443 
1444     if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY))
1445         return NO_POLL_CHAR;
1446 
1447     return msm_read(port, rf_reg) & 0xff;
1448 }
1449 
1450 static int msm_poll_get_char_dm(struct uart_port *port)
1451 {
1452     int c;
1453     static u32 slop;
1454     static int count;
1455     unsigned char *sp = (unsigned char *)&slop;
1456 
1457     /* Check if a previous read had more than one char */
1458     if (count) {
1459         c = sp[sizeof(slop) - count];
1460         count--;
1461     /* Or if FIFO is empty */
1462     } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) {
1463         /*
1464          * If RX packing buffer has less than a word, force stale to
1465          * push contents into RX FIFO
1466          */
1467         count = msm_read(port, UARTDM_RXFS);
1468         count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1469         if (count) {
1470             msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
1471             slop = msm_read(port, UARTDM_RF);
1472             c = sp[0];
1473             count--;
1474             msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1475             msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1476             msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1477         } else {
1478             c = NO_POLL_CHAR;
1479         }
1480     /* FIFO has a word */
1481     } else {
1482         slop = msm_read(port, UARTDM_RF);
1483         c = sp[0];
1484         count = sizeof(slop) - 1;
1485     }
1486 
1487     return c;
1488 }
1489 
1490 static int msm_poll_get_char(struct uart_port *port)
1491 {
1492     u32 imr;
1493     int c;
1494     struct msm_port *msm_port = to_msm_port(port);
1495 
1496     /* Disable all interrupts */
1497     imr = msm_read(port, MSM_UART_IMR);
1498     msm_write(port, 0, MSM_UART_IMR);
1499 
1500     if (msm_port->is_uartdm)
1501         c = msm_poll_get_char_dm(port);
1502     else
1503         c = msm_poll_get_char_single(port);
1504 
1505     /* Enable interrupts */
1506     msm_write(port, imr, MSM_UART_IMR);
1507 
1508     return c;
1509 }
1510 
1511 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1512 {
1513     u32 imr;
1514     struct msm_port *msm_port = to_msm_port(port);
1515 
1516     /* Disable all interrupts */
1517     imr = msm_read(port, MSM_UART_IMR);
1518     msm_write(port, 0, MSM_UART_IMR);
1519 
1520     if (msm_port->is_uartdm)
1521         msm_reset_dm_count(port, 1);
1522 
1523     /* Wait until FIFO is empty */
1524     while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1525         cpu_relax();
1526 
1527     /* Write a character */
1528     msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
1529 
1530     /* Wait until FIFO is empty */
1531     while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1532         cpu_relax();
1533 
1534     /* Enable interrupts */
1535     msm_write(port, imr, MSM_UART_IMR);
1536 }
1537 #endif
1538 
1539 static const struct uart_ops msm_uart_pops = {
1540     .tx_empty = msm_tx_empty,
1541     .set_mctrl = msm_set_mctrl,
1542     .get_mctrl = msm_get_mctrl,
1543     .stop_tx = msm_stop_tx,
1544     .start_tx = msm_start_tx,
1545     .stop_rx = msm_stop_rx,
1546     .enable_ms = msm_enable_ms,
1547     .break_ctl = msm_break_ctl,
1548     .startup = msm_startup,
1549     .shutdown = msm_shutdown,
1550     .set_termios = msm_set_termios,
1551     .type = msm_type,
1552     .release_port = msm_release_port,
1553     .request_port = msm_request_port,
1554     .config_port = msm_config_port,
1555     .verify_port = msm_verify_port,
1556     .pm = msm_power,
1557 #ifdef CONFIG_CONSOLE_POLL
1558     .poll_get_char  = msm_poll_get_char,
1559     .poll_put_char  = msm_poll_put_char,
1560 #endif
1561 };
1562 
1563 static struct msm_port msm_uart_ports[] = {
1564     {
1565         .uart = {
1566             .iotype = UPIO_MEM,
1567             .ops = &msm_uart_pops,
1568             .flags = UPF_BOOT_AUTOCONF,
1569             .fifosize = 64,
1570             .line = 0,
1571         },
1572     },
1573     {
1574         .uart = {
1575             .iotype = UPIO_MEM,
1576             .ops = &msm_uart_pops,
1577             .flags = UPF_BOOT_AUTOCONF,
1578             .fifosize = 64,
1579             .line = 1,
1580         },
1581     },
1582     {
1583         .uart = {
1584             .iotype = UPIO_MEM,
1585             .ops = &msm_uart_pops,
1586             .flags = UPF_BOOT_AUTOCONF,
1587             .fifosize = 64,
1588             .line = 2,
1589         },
1590     },
1591 };
1592 
1593 #define MSM_UART_NR ARRAY_SIZE(msm_uart_ports)
1594 
1595 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1596 {
1597     return &msm_uart_ports[line].uart;
1598 }
1599 
1600 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1601 static void __msm_console_write(struct uart_port *port, const char *s,
1602                 unsigned int count, bool is_uartdm)
1603 {
1604     unsigned long flags;
1605     int i;
1606     int num_newlines = 0;
1607     bool replaced = false;
1608     void __iomem *tf;
1609     int locked = 1;
1610 
1611     if (is_uartdm)
1612         tf = port->membase + UARTDM_TF;
1613     else
1614         tf = port->membase + MSM_UART_TF;
1615 
1616     /* Account for newlines that will get a carriage return added */
1617     for (i = 0; i < count; i++)
1618         if (s[i] == '\n')
1619             num_newlines++;
1620     count += num_newlines;
1621 
1622     local_irq_save(flags);
1623 
1624     if (port->sysrq)
1625         locked = 0;
1626     else if (oops_in_progress)
1627         locked = spin_trylock(&port->lock);
1628     else
1629         spin_lock(&port->lock);
1630 
1631     if (is_uartdm)
1632         msm_reset_dm_count(port, count);
1633 
1634     i = 0;
1635     while (i < count) {
1636         int j;
1637         unsigned int num_chars;
1638         char buf[4] = { 0 };
1639 
1640         if (is_uartdm)
1641             num_chars = min(count - i, (unsigned int)sizeof(buf));
1642         else
1643             num_chars = 1;
1644 
1645         for (j = 0; j < num_chars; j++) {
1646             char c = *s;
1647 
1648             if (c == '\n' && !replaced) {
1649                 buf[j] = '\r';
1650                 j++;
1651                 replaced = true;
1652             }
1653             if (j < num_chars) {
1654                 buf[j] = c;
1655                 s++;
1656                 replaced = false;
1657             }
1658         }
1659 
1660         while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1661             cpu_relax();
1662 
1663         iowrite32_rep(tf, buf, 1);
1664         i += num_chars;
1665     }
1666 
1667     if (locked)
1668         spin_unlock(&port->lock);
1669 
1670     local_irq_restore(flags);
1671 }
1672 
1673 static void msm_console_write(struct console *co, const char *s,
1674                   unsigned int count)
1675 {
1676     struct uart_port *port;
1677     struct msm_port *msm_port;
1678 
1679     BUG_ON(co->index < 0 || co->index >= MSM_UART_NR);
1680 
1681     port = msm_get_port_from_line(co->index);
1682     msm_port = to_msm_port(port);
1683 
1684     __msm_console_write(port, s, count, msm_port->is_uartdm);
1685 }
1686 
1687 static int msm_console_setup(struct console *co, char *options)
1688 {
1689     struct uart_port *port;
1690     int baud = 115200;
1691     int bits = 8;
1692     int parity = 'n';
1693     int flow = 'n';
1694 
1695     if (unlikely(co->index >= MSM_UART_NR || co->index < 0))
1696         return -ENXIO;
1697 
1698     port = msm_get_port_from_line(co->index);
1699 
1700     if (unlikely(!port->membase))
1701         return -ENXIO;
1702 
1703     msm_init_clock(port);
1704 
1705     if (options)
1706         uart_parse_options(options, &baud, &parity, &bits, &flow);
1707 
1708     pr_info("msm_serial: console setup on port #%d\n", port->line);
1709 
1710     return uart_set_options(port, co, baud, parity, bits, flow);
1711 }
1712 
1713 static void
1714 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1715 {
1716     struct earlycon_device *dev = con->data;
1717 
1718     __msm_console_write(&dev->port, s, n, false);
1719 }
1720 
1721 static int __init
1722 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1723 {
1724     if (!device->port.membase)
1725         return -ENODEV;
1726 
1727     device->con->write = msm_serial_early_write;
1728     return 0;
1729 }
1730 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1731             msm_serial_early_console_setup);
1732 
1733 static void
1734 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1735 {
1736     struct earlycon_device *dev = con->data;
1737 
1738     __msm_console_write(&dev->port, s, n, true);
1739 }
1740 
1741 static int __init
1742 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1743                   const char *opt)
1744 {
1745     if (!device->port.membase)
1746         return -ENODEV;
1747 
1748     device->con->write = msm_serial_early_write_dm;
1749     return 0;
1750 }
1751 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1752             msm_serial_early_console_setup_dm);
1753 
1754 static struct uart_driver msm_uart_driver;
1755 
1756 static struct console msm_console = {
1757     .name = "ttyMSM",
1758     .write = msm_console_write,
1759     .device = uart_console_device,
1760     .setup = msm_console_setup,
1761     .flags = CON_PRINTBUFFER,
1762     .index = -1,
1763     .data = &msm_uart_driver,
1764 };
1765 
1766 #define MSM_CONSOLE (&msm_console)
1767 
1768 #else
1769 #define MSM_CONSOLE NULL
1770 #endif
1771 
1772 static struct uart_driver msm_uart_driver = {
1773     .owner = THIS_MODULE,
1774     .driver_name = "msm_serial",
1775     .dev_name = "ttyMSM",
1776     .nr = MSM_UART_NR,
1777     .cons = MSM_CONSOLE,
1778 };
1779 
1780 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1781 
1782 static const struct of_device_id msm_uartdm_table[] = {
1783     { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1784     { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1785     { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1786     { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1787     { }
1788 };
1789 
1790 static int msm_serial_probe(struct platform_device *pdev)
1791 {
1792     struct msm_port *msm_port;
1793     struct resource *resource;
1794     struct uart_port *port;
1795     const struct of_device_id *id;
1796     int irq, line;
1797 
1798     if (pdev->dev.of_node)
1799         line = of_alias_get_id(pdev->dev.of_node, "serial");
1800     else
1801         line = pdev->id;
1802 
1803     if (line < 0)
1804         line = atomic_inc_return(&msm_uart_next_id) - 1;
1805 
1806     if (unlikely(line < 0 || line >= MSM_UART_NR))
1807         return -ENXIO;
1808 
1809     dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1810 
1811     port = msm_get_port_from_line(line);
1812     port->dev = &pdev->dev;
1813     msm_port = to_msm_port(port);
1814 
1815     id = of_match_device(msm_uartdm_table, &pdev->dev);
1816     if (id)
1817         msm_port->is_uartdm = (unsigned long)id->data;
1818     else
1819         msm_port->is_uartdm = 0;
1820 
1821     msm_port->clk = devm_clk_get(&pdev->dev, "core");
1822     if (IS_ERR(msm_port->clk))
1823         return PTR_ERR(msm_port->clk);
1824 
1825     if (msm_port->is_uartdm) {
1826         msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1827         if (IS_ERR(msm_port->pclk))
1828             return PTR_ERR(msm_port->pclk);
1829     }
1830 
1831     port->uartclk = clk_get_rate(msm_port->clk);
1832     dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1833 
1834     resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1835     if (unlikely(!resource))
1836         return -ENXIO;
1837     port->mapbase = resource->start;
1838 
1839     irq = platform_get_irq(pdev, 0);
1840     if (unlikely(irq < 0))
1841         return -ENXIO;
1842     port->irq = irq;
1843     port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1844 
1845     platform_set_drvdata(pdev, port);
1846 
1847     return uart_add_one_port(&msm_uart_driver, port);
1848 }
1849 
1850 static int msm_serial_remove(struct platform_device *pdev)
1851 {
1852     struct uart_port *port = platform_get_drvdata(pdev);
1853 
1854     uart_remove_one_port(&msm_uart_driver, port);
1855 
1856     return 0;
1857 }
1858 
1859 static const struct of_device_id msm_match_table[] = {
1860     { .compatible = "qcom,msm-uart" },
1861     { .compatible = "qcom,msm-uartdm" },
1862     {}
1863 };
1864 MODULE_DEVICE_TABLE(of, msm_match_table);
1865 
1866 static int __maybe_unused msm_serial_suspend(struct device *dev)
1867 {
1868     struct msm_port *port = dev_get_drvdata(dev);
1869 
1870     uart_suspend_port(&msm_uart_driver, &port->uart);
1871 
1872     return 0;
1873 }
1874 
1875 static int __maybe_unused msm_serial_resume(struct device *dev)
1876 {
1877     struct msm_port *port = dev_get_drvdata(dev);
1878 
1879     uart_resume_port(&msm_uart_driver, &port->uart);
1880 
1881     return 0;
1882 }
1883 
1884 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1885     SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1886 };
1887 
1888 static struct platform_driver msm_platform_driver = {
1889     .remove = msm_serial_remove,
1890     .probe = msm_serial_probe,
1891     .driver = {
1892         .name = "msm_serial",
1893         .pm = &msm_serial_dev_pm_ops,
1894         .of_match_table = msm_match_table,
1895     },
1896 };
1897 
1898 static int __init msm_serial_init(void)
1899 {
1900     int ret;
1901 
1902     ret = uart_register_driver(&msm_uart_driver);
1903     if (unlikely(ret))
1904         return ret;
1905 
1906     ret = platform_driver_register(&msm_platform_driver);
1907     if (unlikely(ret))
1908         uart_unregister_driver(&msm_uart_driver);
1909 
1910     pr_info("msm_serial: driver initialized\n");
1911 
1912     return ret;
1913 }
1914 
1915 static void __exit msm_serial_exit(void)
1916 {
1917     platform_driver_unregister(&msm_platform_driver);
1918     uart_unregister_driver(&msm_uart_driver);
1919 }
1920 
1921 module_init(msm_serial_init);
1922 module_exit(msm_serial_exit);
1923 
1924 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1925 MODULE_DESCRIPTION("Driver for msm7x serial device");
1926 MODULE_LICENSE("GPL");
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