tty/serial/mps2-uart.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MPS2 UART driver
0004  *
0005  * Copyright (C) 2015 ARM Limited
0006  *
0007  * Author: Vladimir Murzin <vladimir.murzin@arm.com>
0008  *
0009  * TODO: support for SysRq
0010  */
0011
0012 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0013
0014 #include <linux/bitops.h>
0015 #include <linux/clk.h>
0016 #include <linux/console.h>
0017 #include <linux/io.h>
0018 #include <linux/kernel.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/serial_core.h>
0023 #include <linux/tty_flip.h>
0024 #include <linux/types.h>
0025 #include <linux/idr.h>
0026
0027 #define SERIAL_NAME "ttyMPS"
0028 #define DRIVER_NAME "mps2-uart"
0029 #define MAKE_NAME(x)    (DRIVER_NAME # x)
0030
0031 #define UARTn_DATA              0x00
0032
0033 #define UARTn_STATE             0x04
0034 #define UARTn_STATE_TX_FULL         BIT(0)
0035 #define UARTn_STATE_RX_FULL         BIT(1)
0036 #define UARTn_STATE_TX_OVERRUN          BIT(2)
0037 #define UARTn_STATE_RX_OVERRUN          BIT(3)
0038
0039 #define UARTn_CTRL              0x08
0040 #define UARTn_CTRL_TX_ENABLE            BIT(0)
0041 #define UARTn_CTRL_RX_ENABLE            BIT(1)
0042 #define UARTn_CTRL_TX_INT_ENABLE        BIT(2)
0043 #define UARTn_CTRL_RX_INT_ENABLE        BIT(3)
0044 #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE    BIT(4)
0045 #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE    BIT(5)
0046
0047 #define UARTn_INT               0x0c
0048 #define UARTn_INT_TX                BIT(0)
0049 #define UARTn_INT_RX                BIT(1)
0050 #define UARTn_INT_TX_OVERRUN            BIT(2)
0051 #define UARTn_INT_RX_OVERRUN            BIT(3)
0052
0053 #define UARTn_BAUDDIV               0x10
0054 #define UARTn_BAUDDIV_MASK          GENMASK(20, 0)
0055
0056 /*
0057  * Helpers to make typical enable/disable operations more readable.
0058  */
0059 #define UARTn_CTRL_TX_GRP   (UARTn_CTRL_TX_ENABLE        |\
0060                  UARTn_CTRL_TX_INT_ENABLE    |\
0061                  UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
0062
0063 #define UARTn_CTRL_RX_GRP   (UARTn_CTRL_RX_ENABLE        |\
0064                  UARTn_CTRL_RX_INT_ENABLE    |\
0065                  UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
0066
0067 #define MPS2_MAX_PORTS      3
0068
0069 #define UART_PORT_COMBINED_IRQ  BIT(0)
0070
0071 struct mps2_uart_port {
0072     struct uart_port port;
0073     struct clk *clk;
0074     unsigned int tx_irq;
0075     unsigned int rx_irq;
0076     unsigned int flags;
0077 };
0078
0079 static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
0080 {
0081     return container_of(port, struct mps2_uart_port, port);
0082 }
0083
0084 static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
0085 {
0086     struct mps2_uart_port *mps_port = to_mps2_port(port);
0087
0088     writeb(val, mps_port->port.membase + off);
0089 }
0090
0091 static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
0092 {
0093     struct mps2_uart_port *mps_port = to_mps2_port(port);
0094
0095     return readb(mps_port->port.membase + off);
0096 }
0097
0098 static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
0099 {
0100     struct mps2_uart_port *mps_port = to_mps2_port(port);
0101
0102     writel_relaxed(val, mps_port->port.membase + off);
0103 }
0104
0105 static unsigned int mps2_uart_tx_empty(struct uart_port *port)
0106 {
0107     u8 status = mps2_uart_read8(port, UARTn_STATE);
0108
0109     return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
0110 }
0111
0112 static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0113 {
0114 }
0115
0116 static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
0117 {
0118     return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
0119 }
0120
0121 static void mps2_uart_stop_tx(struct uart_port *port)
0122 {
0123     u8 control = mps2_uart_read8(port, UARTn_CTRL);
0124
0125     control &= ~UARTn_CTRL_TX_INT_ENABLE;
0126
0127     mps2_uart_write8(port, control, UARTn_CTRL);
0128 }
0129
0130 static void mps2_uart_tx_chars(struct uart_port *port)
0131 {
0132     struct circ_buf *xmit = &port->state->xmit;
0133
0134     while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
0135         if (port->x_char) {
0136             mps2_uart_write8(port, port->x_char, UARTn_DATA);
0137             port->x_char = 0;
0138             port->icount.tx++;
0139             continue;
0140         }
0141
0142         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
0143             break;
0144
0145         mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
0146         xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
0147         port->icount.tx++;
0148     }
0149
0150     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0151         uart_write_wakeup(port);
0152
0153     if (uart_circ_empty(xmit))
0154         mps2_uart_stop_tx(port);
0155 }
0156
0157 static void mps2_uart_start_tx(struct uart_port *port)
0158 {
0159     u8 control = mps2_uart_read8(port, UARTn_CTRL);
0160
0161     control |= UARTn_CTRL_TX_INT_ENABLE;
0162
0163     mps2_uart_write8(port, control, UARTn_CTRL);
0164
0165     /*
0166      * We've just unmasked the TX IRQ and now slow-starting via
0167      * polling; if there is enough data to fill up the internal
0168      * write buffer in one go, the TX IRQ should assert, at which
0169      * point we switch to fully interrupt-driven TX.
0170      */
0171
0172     mps2_uart_tx_chars(port);
0173 }
0174
0175 static void mps2_uart_stop_rx(struct uart_port *port)
0176 {
0177     u8 control = mps2_uart_read8(port, UARTn_CTRL);
0178
0179     control &= ~UARTn_CTRL_RX_GRP;
0180
0181     mps2_uart_write8(port, control, UARTn_CTRL);
0182 }
0183
0184 static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
0185 {
0186 }
0187
0188 static void mps2_uart_rx_chars(struct uart_port *port)
0189 {
0190     struct tty_port *tport = &port->state->port;
0191
0192     while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
0193         u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
0194
0195         port->icount.rx++;
0196         tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
0197     }
0198
0199     tty_flip_buffer_push(tport);
0200 }
0201
0202 static irqreturn_t mps2_uart_rxirq(int irq, void *data)
0203 {
0204     struct uart_port *port = data;
0205     u8 irqflag = mps2_uart_read8(port, UARTn_INT);
0206
0207     if (unlikely(!(irqflag & UARTn_INT_RX)))
0208         return IRQ_NONE;
0209
0210     spin_lock(&port->lock);
0211
0212     mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
0213     mps2_uart_rx_chars(port);
0214
0215     spin_unlock(&port->lock);
0216
0217     return IRQ_HANDLED;
0218 }
0219
0220 static irqreturn_t mps2_uart_txirq(int irq, void *data)
0221 {
0222     struct uart_port *port = data;
0223     u8 irqflag = mps2_uart_read8(port, UARTn_INT);
0224
0225     if (unlikely(!(irqflag & UARTn_INT_TX)))
0226         return IRQ_NONE;
0227
0228     spin_lock(&port->lock);
0229
0230     mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
0231     mps2_uart_tx_chars(port);
0232
0233     spin_unlock(&port->lock);
0234
0235     return IRQ_HANDLED;
0236 }
0237
0238 static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
0239 {
0240     irqreturn_t handled = IRQ_NONE;
0241     struct uart_port *port = data;
0242     u8 irqflag = mps2_uart_read8(port, UARTn_INT);
0243
0244     spin_lock(&port->lock);
0245
0246     if (irqflag & UARTn_INT_RX_OVERRUN) {
0247         struct tty_port *tport = &port->state->port;
0248
0249         mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
0250         port->icount.overrun++;
0251         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0252         tty_flip_buffer_push(tport);
0253         handled = IRQ_HANDLED;
0254     }
0255
0256     /*
0257      * It's never been seen in practice and it never *should* happen since
0258      * we check if there is enough room in TX buffer before sending data.
0259      * So we keep this check in case something suspicious has happened.
0260      */
0261     if (irqflag & UARTn_INT_TX_OVERRUN) {
0262         mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
0263         handled = IRQ_HANDLED;
0264     }
0265
0266     spin_unlock(&port->lock);
0267
0268     return handled;
0269 }
0270
0271 static irqreturn_t mps2_uart_combinedirq(int irq, void *data)
0272 {
0273     if (mps2_uart_rxirq(irq, data) == IRQ_HANDLED)
0274         return IRQ_HANDLED;
0275
0276     if (mps2_uart_txirq(irq, data) == IRQ_HANDLED)
0277         return IRQ_HANDLED;
0278
0279     if (mps2_uart_oerrirq(irq, data) == IRQ_HANDLED)
0280         return IRQ_HANDLED;
0281
0282     return IRQ_NONE;
0283 }
0284
0285 static int mps2_uart_startup(struct uart_port *port)
0286 {
0287     struct mps2_uart_port *mps_port = to_mps2_port(port);
0288     u8 control = mps2_uart_read8(port, UARTn_CTRL);
0289     int ret;
0290
0291     control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
0292
0293     mps2_uart_write8(port, control, UARTn_CTRL);
0294
0295     if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
0296         ret = request_irq(port->irq, mps2_uart_combinedirq, 0,
0297                   MAKE_NAME(-combined), mps_port);
0298
0299         if (ret) {
0300             dev_err(port->dev, "failed to register combinedirq (%d)\n", ret);
0301             return ret;
0302         }
0303     } else {
0304         ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
0305                   MAKE_NAME(-overrun), mps_port);
0306
0307         if (ret) {
0308             dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
0309             return ret;
0310         }
0311
0312         ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
0313                   MAKE_NAME(-rx), mps_port);
0314         if (ret) {
0315             dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
0316             goto err_free_oerrirq;
0317         }
0318
0319         ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
0320                   MAKE_NAME(-tx), mps_port);
0321         if (ret) {
0322             dev_err(port->dev, "failed to register txirq (%d)\n", ret);
0323             goto err_free_rxirq;
0324         }
0325
0326     }
0327
0328     control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
0329
0330     mps2_uart_write8(port, control, UARTn_CTRL);
0331
0332     return 0;
0333
0334 err_free_rxirq:
0335     free_irq(mps_port->rx_irq, mps_port);
0336 err_free_oerrirq:
0337     free_irq(port->irq, mps_port);
0338
0339     return ret;
0340 }
0341
0342 static void mps2_uart_shutdown(struct uart_port *port)
0343 {
0344     struct mps2_uart_port *mps_port = to_mps2_port(port);
0345     u8 control = mps2_uart_read8(port, UARTn_CTRL);
0346
0347     control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
0348
0349     mps2_uart_write8(port, control, UARTn_CTRL);
0350
0351     if (!(mps_port->flags & UART_PORT_COMBINED_IRQ)) {
0352         free_irq(mps_port->rx_irq, mps_port);
0353         free_irq(mps_port->tx_irq, mps_port);
0354     }
0355
0356     free_irq(port->irq, mps_port);
0357 }
0358
0359 static void
0360 mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
0361               struct ktermios *old)
0362 {
0363     unsigned long flags;
0364     unsigned int baud, bauddiv;
0365
0366     termios->c_cflag &= ~(CRTSCTS | CMSPAR);
0367     termios->c_cflag &= ~CSIZE;
0368     termios->c_cflag |= CS8;
0369     termios->c_cflag &= ~PARENB;
0370     termios->c_cflag &= ~CSTOPB;
0371
0372     baud = uart_get_baud_rate(port, termios, old,
0373             DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
0374             DIV_ROUND_CLOSEST(port->uartclk, 16));
0375
0376     bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
0377
0378     spin_lock_irqsave(&port->lock, flags);
0379
0380     uart_update_timeout(port, termios->c_cflag, baud);
0381     mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
0382
0383     spin_unlock_irqrestore(&port->lock, flags);
0384
0385     if (tty_termios_baud_rate(termios))
0386         tty_termios_encode_baud_rate(termios, baud, baud);
0387 }
0388
0389 static const char *mps2_uart_type(struct uart_port *port)
0390 {
0391     return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
0392 }
0393
0394 static void mps2_uart_release_port(struct uart_port *port)
0395 {
0396 }
0397
0398 static int mps2_uart_request_port(struct uart_port *port)
0399 {
0400     return 0;
0401 }
0402
0403 static void mps2_uart_config_port(struct uart_port *port, int type)
0404 {
0405     if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
0406         port->type = PORT_MPS2UART;
0407 }
0408
0409 static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
0410 {
0411     return -EINVAL;
0412 }
0413
0414 static const struct uart_ops mps2_uart_pops = {
0415     .tx_empty = mps2_uart_tx_empty,
0416     .set_mctrl = mps2_uart_set_mctrl,
0417     .get_mctrl = mps2_uart_get_mctrl,
0418     .stop_tx = mps2_uart_stop_tx,
0419     .start_tx = mps2_uart_start_tx,
0420     .stop_rx = mps2_uart_stop_rx,
0421     .break_ctl = mps2_uart_break_ctl,
0422     .startup = mps2_uart_startup,
0423     .shutdown = mps2_uart_shutdown,
0424     .set_termios = mps2_uart_set_termios,
0425     .type = mps2_uart_type,
0426     .release_port = mps2_uart_release_port,
0427     .request_port = mps2_uart_request_port,
0428     .config_port = mps2_uart_config_port,
0429     .verify_port = mps2_uart_verify_port,
0430 };
0431
0432 static DEFINE_IDR(ports_idr);
0433
0434 #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
0435 static void mps2_uart_console_putchar(struct uart_port *port, unsigned char ch)
0436 {
0437     while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
0438         cpu_relax();
0439
0440     mps2_uart_write8(port, ch, UARTn_DATA);
0441 }
0442
0443 static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
0444 {
0445     struct mps2_uart_port *mps_port = idr_find(&ports_idr, co->index);
0446     struct uart_port *port = &mps_port->port;
0447
0448     uart_console_write(port, s, cnt, mps2_uart_console_putchar);
0449 }
0450
0451 static int mps2_uart_console_setup(struct console *co, char *options)
0452 {
0453     struct mps2_uart_port *mps_port;
0454     int baud = 9600;
0455     int bits = 8;
0456     int parity = 'n';
0457     int flow = 'n';
0458
0459     if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
0460         return -ENODEV;
0461
0462     mps_port = idr_find(&ports_idr, co->index);
0463
0464     if (!mps_port)
0465         return -ENODEV;
0466
0467     if (options)
0468         uart_parse_options(options, &baud, &parity, &bits, &flow);
0469
0470     return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
0471 }
0472
0473 static struct uart_driver mps2_uart_driver;
0474
0475 static struct console mps2_uart_console = {
0476     .name = SERIAL_NAME,
0477     .device = uart_console_device,
0478     .write = mps2_uart_console_write,
0479     .setup = mps2_uart_console_setup,
0480     .flags = CON_PRINTBUFFER,
0481     .index = -1,
0482     .data = &mps2_uart_driver,
0483 };
0484
0485 #define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
0486
0487 static void mps2_early_putchar(struct uart_port *port, unsigned char ch)
0488 {
0489     while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
0490         cpu_relax();
0491
0492     writeb((unsigned char)ch, port->membase + UARTn_DATA);
0493 }
0494
0495 static void mps2_early_write(struct console *con, const char *s, unsigned int n)
0496 {
0497     struct earlycon_device *dev = con->data;
0498
0499     uart_console_write(&dev->port, s, n, mps2_early_putchar);
0500 }
0501
0502 static int __init mps2_early_console_setup(struct earlycon_device *device,
0503                        const char *opt)
0504 {
0505     if (!device->port.membase)
0506         return -ENODEV;
0507
0508     device->con->write = mps2_early_write;
0509
0510     return 0;
0511 }
0512
0513 OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
0514
0515 #else
0516 #define MPS2_SERIAL_CONSOLE NULL
0517 #endif
0518
0519 static struct uart_driver mps2_uart_driver = {
0520     .driver_name = DRIVER_NAME,
0521     .dev_name = SERIAL_NAME,
0522     .nr = MPS2_MAX_PORTS,
0523     .cons = MPS2_SERIAL_CONSOLE,
0524 };
0525
0526 static int mps2_of_get_port(struct platform_device *pdev,
0527                 struct mps2_uart_port *mps_port)
0528 {
0529     struct device_node *np = pdev->dev.of_node;
0530     int id;
0531
0532     if (!np)
0533         return -ENODEV;
0534
0535     id = of_alias_get_id(np, "serial");
0536
0537     if (id < 0)
0538         id = idr_alloc_cyclic(&ports_idr, (void *)mps_port, 0, MPS2_MAX_PORTS, GFP_KERNEL);
0539     else
0540         id = idr_alloc(&ports_idr, (void *)mps_port, id, MPS2_MAX_PORTS, GFP_KERNEL);
0541
0542     if (id < 0)
0543         return id;
0544
0545     /* Only combined irq is presesnt */
0546     if (platform_irq_count(pdev) == 1)
0547         mps_port->flags |= UART_PORT_COMBINED_IRQ;
0548
0549     mps_port->port.line = id;
0550
0551     return 0;
0552 }
0553
0554 static int mps2_init_port(struct platform_device *pdev,
0555               struct mps2_uart_port *mps_port)
0556 {
0557     struct resource *res;
0558     int ret;
0559
0560     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0561     mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
0562     if (IS_ERR(mps_port->port.membase))
0563         return PTR_ERR(mps_port->port.membase);
0564
0565     mps_port->port.mapbase = res->start;
0566     mps_port->port.mapsize = resource_size(res);
0567     mps_port->port.iotype = UPIO_MEM;
0568     mps_port->port.flags = UPF_BOOT_AUTOCONF;
0569     mps_port->port.fifosize = 1;
0570     mps_port->port.ops = &mps2_uart_pops;
0571     mps_port->port.dev = &pdev->dev;
0572
0573     mps_port->clk = devm_clk_get(&pdev->dev, NULL);
0574     if (IS_ERR(mps_port->clk))
0575         return PTR_ERR(mps_port->clk);
0576
0577     ret = clk_prepare_enable(mps_port->clk);
0578     if (ret)
0579         return ret;
0580
0581     mps_port->port.uartclk = clk_get_rate(mps_port->clk);
0582
0583     clk_disable_unprepare(mps_port->clk);
0584
0585
0586     if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
0587         mps_port->port.irq = platform_get_irq(pdev, 0);
0588     } else {
0589         mps_port->rx_irq = platform_get_irq(pdev, 0);
0590         mps_port->tx_irq = platform_get_irq(pdev, 1);
0591         mps_port->port.irq = platform_get_irq(pdev, 2);
0592     }
0593
0594     return ret;
0595 }
0596
0597 static int mps2_serial_probe(struct platform_device *pdev)
0598 {
0599     struct mps2_uart_port *mps_port;
0600     int ret;
0601
0602     mps_port = devm_kzalloc(&pdev->dev, sizeof(struct mps2_uart_port), GFP_KERNEL);
0603
0604         if (!mps_port)
0605                 return -ENOMEM;
0606
0607     ret = mps2_of_get_port(pdev, mps_port);
0608     if (ret)
0609         return ret;
0610
0611     ret = mps2_init_port(pdev, mps_port);
0612     if (ret)
0613         return ret;
0614
0615     ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
0616     if (ret)
0617         return ret;
0618
0619     platform_set_drvdata(pdev, mps_port);
0620
0621     return 0;
0622 }
0623
0624 #ifdef CONFIG_OF
0625 static const struct of_device_id mps2_match[] = {
0626     { .compatible = "arm,mps2-uart", },
0627     {},
0628 };
0629 #endif
0630
0631 static struct platform_driver mps2_serial_driver = {
0632     .probe = mps2_serial_probe,
0633
0634     .driver = {
0635         .name = DRIVER_NAME,
0636         .of_match_table = of_match_ptr(mps2_match),
0637         .suppress_bind_attrs = true,
0638     },
0639 };
0640
0641 static int __init mps2_uart_init(void)
0642 {
0643     int ret;
0644
0645     ret = uart_register_driver(&mps2_uart_driver);
0646     if (ret)
0647         return ret;
0648
0649     ret = platform_driver_register(&mps2_serial_driver);
0650     if (ret)
0651         uart_unregister_driver(&mps2_uart_driver);
0652
0653     return ret;
0654 }
0655 arch_initcall(mps2_uart_init);