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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
0004  *
0005  * FIXME According to the usermanual the status bits in the status register
0006  * are only updated when the peripherals access the FIFO and not when the
0007  * CPU access them. So since we use this bits to know when we stop writing
0008  * and reading, they may not be updated in-time and a race condition may
0009  * exists. But I haven't be able to prove this and I don't care. But if
0010  * any problem arises, it might worth checking. The TX/RX FIFO Stats
0011  * registers should be used in addition.
0012  * Update: Actually, they seem updated ... At least the bits we use.
0013  *
0014  *
0015  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
0016  *
0017  * Some of the code has been inspired/copied from the 2.4 code written
0018  * by Dale Farnsworth <dfarnsworth@mvista.com>.
0019  *
0020  * Copyright (C) 2008 Freescale Semiconductor Inc.
0021  *                    John Rigby <jrigby@gmail.com>
0022  * Added support for MPC5121
0023  * Copyright (C) 2006 Secret Lab Technologies Ltd.
0024  *                    Grant Likely <grant.likely@secretlab.ca>
0025  * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
0026  * Copyright (C) 2003 MontaVista, Software, Inc.
0027  */
0028 
0029 #undef DEBUG
0030 
0031 #include <linux/device.h>
0032 #include <linux/module.h>
0033 #include <linux/tty.h>
0034 #include <linux/tty_flip.h>
0035 #include <linux/serial.h>
0036 #include <linux/sysrq.h>
0037 #include <linux/console.h>
0038 #include <linux/delay.h>
0039 #include <linux/io.h>
0040 #include <linux/of.h>
0041 #include <linux/of_address.h>
0042 #include <linux/of_irq.h>
0043 #include <linux/of_platform.h>
0044 #include <linux/clk.h>
0045 
0046 #include <asm/mpc52xx.h>
0047 #include <asm/mpc52xx_psc.h>
0048 
0049 #include <linux/serial_core.h>
0050 
0051 
0052 /* We've been assigned a range on the "Low-density serial ports" major */
0053 #define SERIAL_PSC_MAJOR    204
0054 #define SERIAL_PSC_MINOR    148
0055 
0056 
0057 #define ISR_PASS_LIMIT 256  /* Max number of iteration in the interrupt */
0058 
0059 
0060 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
0061     /* Rem: - We use the read_status_mask as a shadow of
0062      *        psc->mpc52xx_psc_imr
0063      *      - It's important that is array is all zero on start as we
0064      *        use it to know if it's initialized or not ! If it's not sure
0065      *        it's cleared, then a memset(...,0,...) should be added to
0066      *        the console_init
0067      */
0068 
0069 /* lookup table for matching device nodes to index numbers */
0070 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
0071 
0072 static void mpc52xx_uart_of_enumerate(void);
0073 
0074 
0075 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
0076 
0077 
0078 /* Forward declaration of the interruption handling routine */
0079 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
0080 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
0081 
0082 /* ======================================================================== */
0083 /* PSC fifo operations for isolating differences between 52xx and 512x      */
0084 /* ======================================================================== */
0085 
0086 struct psc_ops {
0087     void        (*fifo_init)(struct uart_port *port);
0088     unsigned int    (*raw_rx_rdy)(struct uart_port *port);
0089     unsigned int    (*raw_tx_rdy)(struct uart_port *port);
0090     unsigned int    (*rx_rdy)(struct uart_port *port);
0091     unsigned int    (*tx_rdy)(struct uart_port *port);
0092     unsigned int    (*tx_empty)(struct uart_port *port);
0093     void        (*stop_rx)(struct uart_port *port);
0094     void        (*start_tx)(struct uart_port *port);
0095     void        (*stop_tx)(struct uart_port *port);
0096     void        (*rx_clr_irq)(struct uart_port *port);
0097     void        (*tx_clr_irq)(struct uart_port *port);
0098     void        (*write_char)(struct uart_port *port, unsigned char c);
0099     unsigned char   (*read_char)(struct uart_port *port);
0100     void        (*cw_disable_ints)(struct uart_port *port);
0101     void        (*cw_restore_ints)(struct uart_port *port);
0102     unsigned int    (*set_baudrate)(struct uart_port *port,
0103                     struct ktermios *new,
0104                     struct ktermios *old);
0105     int     (*clock_alloc)(struct uart_port *port);
0106     void        (*clock_relse)(struct uart_port *port);
0107     int     (*clock)(struct uart_port *port, int enable);
0108     int     (*fifoc_init)(void);
0109     void        (*fifoc_uninit)(void);
0110     void        (*get_irq)(struct uart_port *, struct device_node *);
0111     irqreturn_t (*handle_irq)(struct uart_port *port);
0112     u16     (*get_status)(struct uart_port *port);
0113     u8      (*get_ipcr)(struct uart_port *port);
0114     void        (*command)(struct uart_port *port, u8 cmd);
0115     void        (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
0116     void        (*set_rts)(struct uart_port *port, int state);
0117     void        (*enable_ms)(struct uart_port *port);
0118     void        (*set_sicr)(struct uart_port *port, u32 val);
0119     void        (*set_imr)(struct uart_port *port, u16 val);
0120     u8      (*get_mr1)(struct uart_port *port);
0121 };
0122 
0123 /* setting the prescaler and divisor reg is common for all chips */
0124 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
0125                        u16 prescaler, unsigned int divisor)
0126 {
0127     /* select prescaler */
0128     out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
0129     out_8(&psc->ctur, divisor >> 8);
0130     out_8(&psc->ctlr, divisor & 0xff);
0131 }
0132 
0133 static u16 mpc52xx_psc_get_status(struct uart_port *port)
0134 {
0135     return in_be16(&PSC(port)->mpc52xx_psc_status);
0136 }
0137 
0138 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
0139 {
0140     return in_8(&PSC(port)->mpc52xx_psc_ipcr);
0141 }
0142 
0143 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
0144 {
0145     out_8(&PSC(port)->command, cmd);
0146 }
0147 
0148 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
0149 {
0150     out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
0151     out_8(&PSC(port)->mode, mr1);
0152     out_8(&PSC(port)->mode, mr2);
0153 }
0154 
0155 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
0156 {
0157     if (state)
0158         out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
0159     else
0160         out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
0161 }
0162 
0163 static void mpc52xx_psc_enable_ms(struct uart_port *port)
0164 {
0165     struct mpc52xx_psc __iomem *psc = PSC(port);
0166 
0167     /* clear D_*-bits by reading them */
0168     in_8(&psc->mpc52xx_psc_ipcr);
0169     /* enable CTS and DCD as IPC interrupts */
0170     out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
0171 
0172     port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
0173     out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
0174 }
0175 
0176 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
0177 {
0178     out_be32(&PSC(port)->sicr, val);
0179 }
0180 
0181 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
0182 {
0183     out_be16(&PSC(port)->mpc52xx_psc_imr, val);
0184 }
0185 
0186 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
0187 {
0188     out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
0189     return in_8(&PSC(port)->mode);
0190 }
0191 
0192 #ifdef CONFIG_PPC_MPC52xx
0193 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
0194 static void mpc52xx_psc_fifo_init(struct uart_port *port)
0195 {
0196     struct mpc52xx_psc __iomem *psc = PSC(port);
0197     struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
0198 
0199     out_8(&fifo->rfcntl, 0x00);
0200     out_be16(&fifo->rfalarm, 0x1ff);
0201     out_8(&fifo->tfcntl, 0x07);
0202     out_be16(&fifo->tfalarm, 0x80);
0203 
0204     port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
0205     out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
0206 }
0207 
0208 static unsigned int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
0209 {
0210     return in_be16(&PSC(port)->mpc52xx_psc_status)
0211         & MPC52xx_PSC_SR_RXRDY;
0212 }
0213 
0214 static unsigned int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
0215 {
0216     return in_be16(&PSC(port)->mpc52xx_psc_status)
0217         & MPC52xx_PSC_SR_TXRDY;
0218 }
0219 
0220 
0221 static unsigned int mpc52xx_psc_rx_rdy(struct uart_port *port)
0222 {
0223     return in_be16(&PSC(port)->mpc52xx_psc_isr)
0224         & port->read_status_mask
0225         & MPC52xx_PSC_IMR_RXRDY;
0226 }
0227 
0228 static unsigned int mpc52xx_psc_tx_rdy(struct uart_port *port)
0229 {
0230     return in_be16(&PSC(port)->mpc52xx_psc_isr)
0231         & port->read_status_mask
0232         & MPC52xx_PSC_IMR_TXRDY;
0233 }
0234 
0235 static unsigned int mpc52xx_psc_tx_empty(struct uart_port *port)
0236 {
0237     u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
0238 
0239     return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
0240 }
0241 
0242 static void mpc52xx_psc_start_tx(struct uart_port *port)
0243 {
0244     port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
0245     out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
0246 }
0247 
0248 static void mpc52xx_psc_stop_tx(struct uart_port *port)
0249 {
0250     port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
0251     out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
0252 }
0253 
0254 static void mpc52xx_psc_stop_rx(struct uart_port *port)
0255 {
0256     port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
0257     out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
0258 }
0259 
0260 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
0261 {
0262 }
0263 
0264 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
0265 {
0266 }
0267 
0268 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
0269 {
0270     out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
0271 }
0272 
0273 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
0274 {
0275     return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
0276 }
0277 
0278 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
0279 {
0280     out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
0281 }
0282 
0283 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
0284 {
0285     out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
0286 }
0287 
0288 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
0289                          struct ktermios *new,
0290                          struct ktermios *old)
0291 {
0292     unsigned int baud;
0293     unsigned int divisor;
0294 
0295     /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
0296     baud = uart_get_baud_rate(port, new, old,
0297                   port->uartclk / (32 * 0xffff) + 1,
0298                   port->uartclk / 32);
0299     divisor = (port->uartclk + 16 * baud) / (32 * baud);
0300 
0301     /* enable the /32 prescaler and set the divisor */
0302     mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
0303     return baud;
0304 }
0305 
0306 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
0307                           struct ktermios *new,
0308                           struct ktermios *old)
0309 {
0310     unsigned int baud;
0311     unsigned int divisor;
0312     u16 prescaler;
0313 
0314     /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
0315      * ipb freq */
0316     baud = uart_get_baud_rate(port, new, old,
0317                   port->uartclk / (32 * 0xffff) + 1,
0318                   port->uartclk / 4);
0319     divisor = (port->uartclk + 2 * baud) / (4 * baud);
0320 
0321     /* select the proper prescaler and set the divisor
0322      * prefer high prescaler for more tolerance on low baudrates */
0323     if (divisor > 0xffff || baud <= 115200) {
0324         divisor = (divisor + 4) / 8;
0325         prescaler = 0xdd00; /* /32 */
0326     } else
0327         prescaler = 0xff00; /* /4 */
0328     mpc52xx_set_divisor(PSC(port), prescaler, divisor);
0329     return baud;
0330 }
0331 
0332 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
0333 {
0334     port->irqflags = 0;
0335     port->irq = irq_of_parse_and_map(np, 0);
0336 }
0337 
0338 /* 52xx specific interrupt handler. The caller holds the port lock */
0339 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
0340 {
0341     return mpc5xxx_uart_process_int(port);
0342 }
0343 
0344 static const struct psc_ops mpc52xx_psc_ops = {
0345     .fifo_init = mpc52xx_psc_fifo_init,
0346     .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
0347     .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
0348     .rx_rdy = mpc52xx_psc_rx_rdy,
0349     .tx_rdy = mpc52xx_psc_tx_rdy,
0350     .tx_empty = mpc52xx_psc_tx_empty,
0351     .stop_rx = mpc52xx_psc_stop_rx,
0352     .start_tx = mpc52xx_psc_start_tx,
0353     .stop_tx = mpc52xx_psc_stop_tx,
0354     .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
0355     .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
0356     .write_char = mpc52xx_psc_write_char,
0357     .read_char = mpc52xx_psc_read_char,
0358     .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
0359     .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
0360     .set_baudrate = mpc5200_psc_set_baudrate,
0361     .get_irq = mpc52xx_psc_get_irq,
0362     .handle_irq = mpc52xx_psc_handle_irq,
0363     .get_status = mpc52xx_psc_get_status,
0364     .get_ipcr = mpc52xx_psc_get_ipcr,
0365     .command = mpc52xx_psc_command,
0366     .set_mode = mpc52xx_psc_set_mode,
0367     .set_rts = mpc52xx_psc_set_rts,
0368     .enable_ms = mpc52xx_psc_enable_ms,
0369     .set_sicr = mpc52xx_psc_set_sicr,
0370     .set_imr = mpc52xx_psc_set_imr,
0371     .get_mr1 = mpc52xx_psc_get_mr1,
0372 };
0373 
0374 static const struct psc_ops mpc5200b_psc_ops = {
0375     .fifo_init = mpc52xx_psc_fifo_init,
0376     .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
0377     .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
0378     .rx_rdy = mpc52xx_psc_rx_rdy,
0379     .tx_rdy = mpc52xx_psc_tx_rdy,
0380     .tx_empty = mpc52xx_psc_tx_empty,
0381     .stop_rx = mpc52xx_psc_stop_rx,
0382     .start_tx = mpc52xx_psc_start_tx,
0383     .stop_tx = mpc52xx_psc_stop_tx,
0384     .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
0385     .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
0386     .write_char = mpc52xx_psc_write_char,
0387     .read_char = mpc52xx_psc_read_char,
0388     .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
0389     .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
0390     .set_baudrate = mpc5200b_psc_set_baudrate,
0391     .get_irq = mpc52xx_psc_get_irq,
0392     .handle_irq = mpc52xx_psc_handle_irq,
0393     .get_status = mpc52xx_psc_get_status,
0394     .get_ipcr = mpc52xx_psc_get_ipcr,
0395     .command = mpc52xx_psc_command,
0396     .set_mode = mpc52xx_psc_set_mode,
0397     .set_rts = mpc52xx_psc_set_rts,
0398     .enable_ms = mpc52xx_psc_enable_ms,
0399     .set_sicr = mpc52xx_psc_set_sicr,
0400     .set_imr = mpc52xx_psc_set_imr,
0401     .get_mr1 = mpc52xx_psc_get_mr1,
0402 };
0403 
0404 #endif /* CONFIG_PPC_MPC52xx */
0405 
0406 #ifdef CONFIG_PPC_MPC512x
0407 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
0408 
0409 /* PSC FIFO Controller for mpc512x */
0410 struct psc_fifoc {
0411     u32 fifoc_cmd;
0412     u32 fifoc_int;
0413     u32 fifoc_dma;
0414     u32 fifoc_axe;
0415     u32 fifoc_debug;
0416 };
0417 
0418 static struct psc_fifoc __iomem *psc_fifoc;
0419 static unsigned int psc_fifoc_irq;
0420 static struct clk *psc_fifoc_clk;
0421 
0422 static void mpc512x_psc_fifo_init(struct uart_port *port)
0423 {
0424     /* /32 prescaler */
0425     out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
0426 
0427     out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
0428     out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
0429     out_be32(&FIFO_512x(port)->txalarm, 1);
0430     out_be32(&FIFO_512x(port)->tximr, 0);
0431 
0432     out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
0433     out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
0434     out_be32(&FIFO_512x(port)->rxalarm, 1);
0435     out_be32(&FIFO_512x(port)->rximr, 0);
0436 
0437     out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
0438     out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
0439 }
0440 
0441 static unsigned int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
0442 {
0443     return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
0444 }
0445 
0446 static unsigned int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
0447 {
0448     return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
0449 }
0450 
0451 static unsigned int mpc512x_psc_rx_rdy(struct uart_port *port)
0452 {
0453     return in_be32(&FIFO_512x(port)->rxsr)
0454         & in_be32(&FIFO_512x(port)->rximr)
0455         & MPC512x_PSC_FIFO_ALARM;
0456 }
0457 
0458 static unsigned int mpc512x_psc_tx_rdy(struct uart_port *port)
0459 {
0460     return in_be32(&FIFO_512x(port)->txsr)
0461         & in_be32(&FIFO_512x(port)->tximr)
0462         & MPC512x_PSC_FIFO_ALARM;
0463 }
0464 
0465 static unsigned int mpc512x_psc_tx_empty(struct uart_port *port)
0466 {
0467     return in_be32(&FIFO_512x(port)->txsr)
0468         & MPC512x_PSC_FIFO_EMPTY;
0469 }
0470 
0471 static void mpc512x_psc_stop_rx(struct uart_port *port)
0472 {
0473     unsigned long rx_fifo_imr;
0474 
0475     rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
0476     rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
0477     out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
0478 }
0479 
0480 static void mpc512x_psc_start_tx(struct uart_port *port)
0481 {
0482     unsigned long tx_fifo_imr;
0483 
0484     tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
0485     tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
0486     out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
0487 }
0488 
0489 static void mpc512x_psc_stop_tx(struct uart_port *port)
0490 {
0491     unsigned long tx_fifo_imr;
0492 
0493     tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
0494     tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
0495     out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
0496 }
0497 
0498 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
0499 {
0500     out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
0501 }
0502 
0503 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
0504 {
0505     out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
0506 }
0507 
0508 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
0509 {
0510     out_8(&FIFO_512x(port)->txdata_8, c);
0511 }
0512 
0513 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
0514 {
0515     return in_8(&FIFO_512x(port)->rxdata_8);
0516 }
0517 
0518 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
0519 {
0520     port->read_status_mask =
0521         in_be32(&FIFO_512x(port)->tximr) << 16 |
0522         in_be32(&FIFO_512x(port)->rximr);
0523     out_be32(&FIFO_512x(port)->tximr, 0);
0524     out_be32(&FIFO_512x(port)->rximr, 0);
0525 }
0526 
0527 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
0528 {
0529     out_be32(&FIFO_512x(port)->tximr,
0530         (port->read_status_mask >> 16) & 0x7f);
0531     out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
0532 }
0533 
0534 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
0535                          struct ktermios *new,
0536                          struct ktermios *old)
0537 {
0538     unsigned int baud;
0539     unsigned int divisor;
0540 
0541     /*
0542      * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
0543      * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
0544      * Furthermore, it states that "After reset, the prescaler by 10
0545      * for the UART mode is selected", but the reset register value is
0546      * 0x0000 which means a /32 prescaler. This is wrong.
0547      *
0548      * In reality using /32 prescaler doesn't work, as it is not supported!
0549      * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
0550      * Chapter 4.1 PSC in UART Mode.
0551      * Calculate with a /16 prescaler here.
0552      */
0553 
0554     /* uartclk contains the ips freq */
0555     baud = uart_get_baud_rate(port, new, old,
0556                   port->uartclk / (16 * 0xffff) + 1,
0557                   port->uartclk / 16);
0558     divisor = (port->uartclk + 8 * baud) / (16 * baud);
0559 
0560     /* enable the /16 prescaler and set the divisor */
0561     mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
0562     return baud;
0563 }
0564 
0565 /* Init PSC FIFO Controller */
0566 static int __init mpc512x_psc_fifoc_init(void)
0567 {
0568     int err;
0569     struct device_node *np;
0570     struct clk *clk;
0571 
0572     /* default error code, potentially overwritten by clock calls */
0573     err = -ENODEV;
0574 
0575     np = of_find_compatible_node(NULL, NULL,
0576                      "fsl,mpc5121-psc-fifo");
0577     if (!np) {
0578         pr_err("%s: Can't find FIFOC node\n", __func__);
0579         goto out_err;
0580     }
0581 
0582     clk = of_clk_get(np, 0);
0583     if (IS_ERR(clk)) {
0584         /* backwards compat with device trees that lack clock specs */
0585         clk = clk_get_sys(np->name, "ipg");
0586     }
0587     if (IS_ERR(clk)) {
0588         pr_err("%s: Can't lookup FIFO clock\n", __func__);
0589         err = PTR_ERR(clk);
0590         goto out_ofnode_put;
0591     }
0592     if (clk_prepare_enable(clk)) {
0593         pr_err("%s: Can't enable FIFO clock\n", __func__);
0594         clk_put(clk);
0595         goto out_ofnode_put;
0596     }
0597     psc_fifoc_clk = clk;
0598 
0599     psc_fifoc = of_iomap(np, 0);
0600     if (!psc_fifoc) {
0601         pr_err("%s: Can't map FIFOC\n", __func__);
0602         goto out_clk_disable;
0603     }
0604 
0605     psc_fifoc_irq = irq_of_parse_and_map(np, 0);
0606     if (psc_fifoc_irq == 0) {
0607         pr_err("%s: Can't get FIFOC irq\n", __func__);
0608         goto out_unmap;
0609     }
0610 
0611     of_node_put(np);
0612     return 0;
0613 
0614 out_unmap:
0615     iounmap(psc_fifoc);
0616 out_clk_disable:
0617     clk_disable_unprepare(psc_fifoc_clk);
0618     clk_put(psc_fifoc_clk);
0619 out_ofnode_put:
0620     of_node_put(np);
0621 out_err:
0622     return err;
0623 }
0624 
0625 static void __exit mpc512x_psc_fifoc_uninit(void)
0626 {
0627     iounmap(psc_fifoc);
0628 
0629     /* disable the clock, errors are not fatal */
0630     if (psc_fifoc_clk) {
0631         clk_disable_unprepare(psc_fifoc_clk);
0632         clk_put(psc_fifoc_clk);
0633         psc_fifoc_clk = NULL;
0634     }
0635 }
0636 
0637 /* 512x specific interrupt handler. The caller holds the port lock */
0638 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
0639 {
0640     unsigned long fifoc_int;
0641     int psc_num;
0642 
0643     /* Read pending PSC FIFOC interrupts */
0644     fifoc_int = in_be32(&psc_fifoc->fifoc_int);
0645 
0646     /* Check if it is an interrupt for this port */
0647     psc_num = (port->mapbase & 0xf00) >> 8;
0648     if (test_bit(psc_num, &fifoc_int) ||
0649         test_bit(psc_num + 16, &fifoc_int))
0650         return mpc5xxx_uart_process_int(port);
0651 
0652     return IRQ_NONE;
0653 }
0654 
0655 static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
0656 static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
0657 
0658 /* called from within the .request_port() callback (allocation) */
0659 static int mpc512x_psc_alloc_clock(struct uart_port *port)
0660 {
0661     int psc_num;
0662     struct clk *clk;
0663     int err;
0664 
0665     psc_num = (port->mapbase & 0xf00) >> 8;
0666 
0667     clk = devm_clk_get(port->dev, "mclk");
0668     if (IS_ERR(clk)) {
0669         dev_err(port->dev, "Failed to get MCLK!\n");
0670         err = PTR_ERR(clk);
0671         goto out_err;
0672     }
0673     err = clk_prepare_enable(clk);
0674     if (err) {
0675         dev_err(port->dev, "Failed to enable MCLK!\n");
0676         goto out_err;
0677     }
0678     psc_mclk_clk[psc_num] = clk;
0679 
0680     clk = devm_clk_get(port->dev, "ipg");
0681     if (IS_ERR(clk)) {
0682         dev_err(port->dev, "Failed to get IPG clock!\n");
0683         err = PTR_ERR(clk);
0684         goto out_err;
0685     }
0686     err = clk_prepare_enable(clk);
0687     if (err) {
0688         dev_err(port->dev, "Failed to enable IPG clock!\n");
0689         goto out_err;
0690     }
0691     psc_ipg_clk[psc_num] = clk;
0692 
0693     return 0;
0694 
0695 out_err:
0696     if (psc_mclk_clk[psc_num]) {
0697         clk_disable_unprepare(psc_mclk_clk[psc_num]);
0698         psc_mclk_clk[psc_num] = NULL;
0699     }
0700     if (psc_ipg_clk[psc_num]) {
0701         clk_disable_unprepare(psc_ipg_clk[psc_num]);
0702         psc_ipg_clk[psc_num] = NULL;
0703     }
0704     return err;
0705 }
0706 
0707 /* called from within the .release_port() callback (release) */
0708 static void mpc512x_psc_relse_clock(struct uart_port *port)
0709 {
0710     int psc_num;
0711     struct clk *clk;
0712 
0713     psc_num = (port->mapbase & 0xf00) >> 8;
0714     clk = psc_mclk_clk[psc_num];
0715     if (clk) {
0716         clk_disable_unprepare(clk);
0717         psc_mclk_clk[psc_num] = NULL;
0718     }
0719     if (psc_ipg_clk[psc_num]) {
0720         clk_disable_unprepare(psc_ipg_clk[psc_num]);
0721         psc_ipg_clk[psc_num] = NULL;
0722     }
0723 }
0724 
0725 /* implementation of the .clock() callback (enable/disable) */
0726 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
0727 {
0728     int psc_num;
0729     struct clk *psc_clk;
0730     int ret;
0731 
0732     if (uart_console(port))
0733         return 0;
0734 
0735     psc_num = (port->mapbase & 0xf00) >> 8;
0736     psc_clk = psc_mclk_clk[psc_num];
0737     if (!psc_clk) {
0738         dev_err(port->dev, "Failed to get PSC clock entry!\n");
0739         return -ENODEV;
0740     }
0741 
0742     dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
0743     if (enable) {
0744         ret = clk_enable(psc_clk);
0745         if (ret)
0746             dev_err(port->dev, "Failed to enable MCLK!\n");
0747         return ret;
0748     } else {
0749         clk_disable(psc_clk);
0750         return 0;
0751     }
0752 }
0753 
0754 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
0755 {
0756     port->irqflags = IRQF_SHARED;
0757     port->irq = psc_fifoc_irq;
0758 }
0759 
0760 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
0761 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
0762 
0763 static void mpc5125_psc_fifo_init(struct uart_port *port)
0764 {
0765     /* /32 prescaler */
0766     out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
0767 
0768     out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
0769     out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
0770     out_be32(&FIFO_5125(port)->txalarm, 1);
0771     out_be32(&FIFO_5125(port)->tximr, 0);
0772 
0773     out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
0774     out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
0775     out_be32(&FIFO_5125(port)->rxalarm, 1);
0776     out_be32(&FIFO_5125(port)->rximr, 0);
0777 
0778     out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
0779     out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
0780 }
0781 
0782 static unsigned int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
0783 {
0784     return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
0785 }
0786 
0787 static unsigned int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
0788 {
0789     return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
0790 }
0791 
0792 static unsigned int mpc5125_psc_rx_rdy(struct uart_port *port)
0793 {
0794     return in_be32(&FIFO_5125(port)->rxsr) &
0795            in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
0796 }
0797 
0798 static unsigned int mpc5125_psc_tx_rdy(struct uart_port *port)
0799 {
0800     return in_be32(&FIFO_5125(port)->txsr) &
0801            in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
0802 }
0803 
0804 static unsigned int mpc5125_psc_tx_empty(struct uart_port *port)
0805 {
0806     return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
0807 }
0808 
0809 static void mpc5125_psc_stop_rx(struct uart_port *port)
0810 {
0811     unsigned long rx_fifo_imr;
0812 
0813     rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
0814     rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
0815     out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
0816 }
0817 
0818 static void mpc5125_psc_start_tx(struct uart_port *port)
0819 {
0820     unsigned long tx_fifo_imr;
0821 
0822     tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
0823     tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
0824     out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
0825 }
0826 
0827 static void mpc5125_psc_stop_tx(struct uart_port *port)
0828 {
0829     unsigned long tx_fifo_imr;
0830 
0831     tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
0832     tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
0833     out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
0834 }
0835 
0836 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
0837 {
0838     out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
0839 }
0840 
0841 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
0842 {
0843     out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
0844 }
0845 
0846 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
0847 {
0848     out_8(&FIFO_5125(port)->txdata_8, c);
0849 }
0850 
0851 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
0852 {
0853     return in_8(&FIFO_5125(port)->rxdata_8);
0854 }
0855 
0856 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
0857 {
0858     port->read_status_mask =
0859         in_be32(&FIFO_5125(port)->tximr) << 16 |
0860         in_be32(&FIFO_5125(port)->rximr);
0861     out_be32(&FIFO_5125(port)->tximr, 0);
0862     out_be32(&FIFO_5125(port)->rximr, 0);
0863 }
0864 
0865 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
0866 {
0867     out_be32(&FIFO_5125(port)->tximr,
0868         (port->read_status_mask >> 16) & 0x7f);
0869     out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
0870 }
0871 
0872 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
0873         u8 prescaler, unsigned int divisor)
0874 {
0875     /* select prescaler */
0876     out_8(&psc->mpc52xx_psc_clock_select, prescaler);
0877     out_8(&psc->ctur, divisor >> 8);
0878     out_8(&psc->ctlr, divisor & 0xff);
0879 }
0880 
0881 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
0882                          struct ktermios *new,
0883                          struct ktermios *old)
0884 {
0885     unsigned int baud;
0886     unsigned int divisor;
0887 
0888     /*
0889      * Calculate with a /16 prescaler here.
0890      */
0891 
0892     /* uartclk contains the ips freq */
0893     baud = uart_get_baud_rate(port, new, old,
0894                   port->uartclk / (16 * 0xffff) + 1,
0895                   port->uartclk / 16);
0896     divisor = (port->uartclk + 8 * baud) / (16 * baud);
0897 
0898     /* enable the /16 prescaler and set the divisor */
0899     mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
0900     return baud;
0901 }
0902 
0903 /*
0904  * MPC5125 have compatible PSC FIFO Controller.
0905  * Special init not needed.
0906  */
0907 static u16 mpc5125_psc_get_status(struct uart_port *port)
0908 {
0909     return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
0910 }
0911 
0912 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
0913 {
0914     return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
0915 }
0916 
0917 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
0918 {
0919     out_8(&PSC_5125(port)->command, cmd);
0920 }
0921 
0922 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
0923 {
0924     out_8(&PSC_5125(port)->mr1, mr1);
0925     out_8(&PSC_5125(port)->mr2, mr2);
0926 }
0927 
0928 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
0929 {
0930     if (state & TIOCM_RTS)
0931         out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
0932     else
0933         out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
0934 }
0935 
0936 static void mpc5125_psc_enable_ms(struct uart_port *port)
0937 {
0938     struct mpc5125_psc __iomem *psc = PSC_5125(port);
0939 
0940     /* clear D_*-bits by reading them */
0941     in_8(&psc->mpc52xx_psc_ipcr);
0942     /* enable CTS and DCD as IPC interrupts */
0943     out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
0944 
0945     port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
0946     out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
0947 }
0948 
0949 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
0950 {
0951     out_be32(&PSC_5125(port)->sicr, val);
0952 }
0953 
0954 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
0955 {
0956     out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
0957 }
0958 
0959 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
0960 {
0961     return in_8(&PSC_5125(port)->mr1);
0962 }
0963 
0964 static const struct psc_ops mpc5125_psc_ops = {
0965     .fifo_init = mpc5125_psc_fifo_init,
0966     .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
0967     .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
0968     .rx_rdy = mpc5125_psc_rx_rdy,
0969     .tx_rdy = mpc5125_psc_tx_rdy,
0970     .tx_empty = mpc5125_psc_tx_empty,
0971     .stop_rx = mpc5125_psc_stop_rx,
0972     .start_tx = mpc5125_psc_start_tx,
0973     .stop_tx = mpc5125_psc_stop_tx,
0974     .rx_clr_irq = mpc5125_psc_rx_clr_irq,
0975     .tx_clr_irq = mpc5125_psc_tx_clr_irq,
0976     .write_char = mpc5125_psc_write_char,
0977     .read_char = mpc5125_psc_read_char,
0978     .cw_disable_ints = mpc5125_psc_cw_disable_ints,
0979     .cw_restore_ints = mpc5125_psc_cw_restore_ints,
0980     .set_baudrate = mpc5125_psc_set_baudrate,
0981     .clock_alloc = mpc512x_psc_alloc_clock,
0982     .clock_relse = mpc512x_psc_relse_clock,
0983     .clock = mpc512x_psc_endis_clock,
0984     .fifoc_init = mpc512x_psc_fifoc_init,
0985     .fifoc_uninit = mpc512x_psc_fifoc_uninit,
0986     .get_irq = mpc512x_psc_get_irq,
0987     .handle_irq = mpc512x_psc_handle_irq,
0988     .get_status = mpc5125_psc_get_status,
0989     .get_ipcr = mpc5125_psc_get_ipcr,
0990     .command = mpc5125_psc_command,
0991     .set_mode = mpc5125_psc_set_mode,
0992     .set_rts = mpc5125_psc_set_rts,
0993     .enable_ms = mpc5125_psc_enable_ms,
0994     .set_sicr = mpc5125_psc_set_sicr,
0995     .set_imr = mpc5125_psc_set_imr,
0996     .get_mr1 = mpc5125_psc_get_mr1,
0997 };
0998 
0999 static const struct psc_ops mpc512x_psc_ops = {
1000     .fifo_init = mpc512x_psc_fifo_init,
1001     .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1002     .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1003     .rx_rdy = mpc512x_psc_rx_rdy,
1004     .tx_rdy = mpc512x_psc_tx_rdy,
1005     .tx_empty = mpc512x_psc_tx_empty,
1006     .stop_rx = mpc512x_psc_stop_rx,
1007     .start_tx = mpc512x_psc_start_tx,
1008     .stop_tx = mpc512x_psc_stop_tx,
1009     .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1010     .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1011     .write_char = mpc512x_psc_write_char,
1012     .read_char = mpc512x_psc_read_char,
1013     .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1014     .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1015     .set_baudrate = mpc512x_psc_set_baudrate,
1016     .clock_alloc = mpc512x_psc_alloc_clock,
1017     .clock_relse = mpc512x_psc_relse_clock,
1018     .clock = mpc512x_psc_endis_clock,
1019     .fifoc_init = mpc512x_psc_fifoc_init,
1020     .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1021     .get_irq = mpc512x_psc_get_irq,
1022     .handle_irq = mpc512x_psc_handle_irq,
1023     .get_status = mpc52xx_psc_get_status,
1024     .get_ipcr = mpc52xx_psc_get_ipcr,
1025     .command = mpc52xx_psc_command,
1026     .set_mode = mpc52xx_psc_set_mode,
1027     .set_rts = mpc52xx_psc_set_rts,
1028     .enable_ms = mpc52xx_psc_enable_ms,
1029     .set_sicr = mpc52xx_psc_set_sicr,
1030     .set_imr = mpc52xx_psc_set_imr,
1031     .get_mr1 = mpc52xx_psc_get_mr1,
1032 };
1033 #endif /* CONFIG_PPC_MPC512x */
1034 
1035 
1036 static const struct psc_ops *psc_ops;
1037 
1038 /* ======================================================================== */
1039 /* UART operations                                                          */
1040 /* ======================================================================== */
1041 
1042 static unsigned int
1043 mpc52xx_uart_tx_empty(struct uart_port *port)
1044 {
1045     return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1046 }
1047 
1048 static void
1049 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1050 {
1051     psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1052 }
1053 
1054 static unsigned int
1055 mpc52xx_uart_get_mctrl(struct uart_port *port)
1056 {
1057     unsigned int ret = TIOCM_DSR;
1058     u8 status = psc_ops->get_ipcr(port);
1059 
1060     if (!(status & MPC52xx_PSC_CTS))
1061         ret |= TIOCM_CTS;
1062     if (!(status & MPC52xx_PSC_DCD))
1063         ret |= TIOCM_CAR;
1064 
1065     return ret;
1066 }
1067 
1068 static void
1069 mpc52xx_uart_stop_tx(struct uart_port *port)
1070 {
1071     /* port->lock taken by caller */
1072     psc_ops->stop_tx(port);
1073 }
1074 
1075 static void
1076 mpc52xx_uart_start_tx(struct uart_port *port)
1077 {
1078     /* port->lock taken by caller */
1079     psc_ops->start_tx(port);
1080 }
1081 
1082 static void
1083 mpc52xx_uart_stop_rx(struct uart_port *port)
1084 {
1085     /* port->lock taken by caller */
1086     psc_ops->stop_rx(port);
1087 }
1088 
1089 static void
1090 mpc52xx_uart_enable_ms(struct uart_port *port)
1091 {
1092     psc_ops->enable_ms(port);
1093 }
1094 
1095 static void
1096 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1097 {
1098     unsigned long flags;
1099     spin_lock_irqsave(&port->lock, flags);
1100 
1101     if (ctl == -1)
1102         psc_ops->command(port, MPC52xx_PSC_START_BRK);
1103     else
1104         psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1105 
1106     spin_unlock_irqrestore(&port->lock, flags);
1107 }
1108 
1109 static int
1110 mpc52xx_uart_startup(struct uart_port *port)
1111 {
1112     int ret;
1113 
1114     if (psc_ops->clock) {
1115         ret = psc_ops->clock(port, 1);
1116         if (ret)
1117             return ret;
1118     }
1119 
1120     /* Request IRQ */
1121     ret = request_irq(port->irq, mpc52xx_uart_int,
1122               port->irqflags, "mpc52xx_psc_uart", port);
1123     if (ret)
1124         return ret;
1125 
1126     /* Reset/activate the port, clear and enable interrupts */
1127     psc_ops->command(port, MPC52xx_PSC_RST_RX);
1128     psc_ops->command(port, MPC52xx_PSC_RST_TX);
1129 
1130     /*
1131      * According to Freescale's support the RST_TX command can produce a
1132      * spike on the TX pin. So they recommend to delay "for one character".
1133      * One millisecond should be enough for everyone.
1134      */
1135     msleep(1);
1136 
1137     psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1138 
1139     psc_ops->fifo_init(port);
1140 
1141     psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1142     psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1143 
1144     return 0;
1145 }
1146 
1147 static void
1148 mpc52xx_uart_shutdown(struct uart_port *port)
1149 {
1150     /* Shut down the port.  Leave TX active if on a console port */
1151     psc_ops->command(port, MPC52xx_PSC_RST_RX);
1152     if (!uart_console(port))
1153         psc_ops->command(port, MPC52xx_PSC_RST_TX);
1154 
1155     port->read_status_mask = 0;
1156     psc_ops->set_imr(port, port->read_status_mask);
1157 
1158     if (psc_ops->clock)
1159         psc_ops->clock(port, 0);
1160 
1161     /* Disable interrupt */
1162     psc_ops->cw_disable_ints(port);
1163 
1164     /* Release interrupt */
1165     free_irq(port->irq, port);
1166 }
1167 
1168 static void
1169 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1170              struct ktermios *old)
1171 {
1172     unsigned long flags;
1173     unsigned char mr1, mr2;
1174     unsigned int j;
1175     unsigned int baud;
1176 
1177     /* Prepare what we're gonna write */
1178     mr1 = 0;
1179 
1180     switch (new->c_cflag & CSIZE) {
1181     case CS5:   mr1 |= MPC52xx_PSC_MODE_5_BITS;
1182         break;
1183     case CS6:   mr1 |= MPC52xx_PSC_MODE_6_BITS;
1184         break;
1185     case CS7:   mr1 |= MPC52xx_PSC_MODE_7_BITS;
1186         break;
1187     case CS8:
1188     default:    mr1 |= MPC52xx_PSC_MODE_8_BITS;
1189     }
1190 
1191     if (new->c_cflag & PARENB) {
1192         if (new->c_cflag & CMSPAR)
1193             mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1194 
1195         /* With CMSPAR, PARODD also means high parity (same as termios) */
1196         mr1 |= (new->c_cflag & PARODD) ?
1197             MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1198     } else {
1199         mr1 |= MPC52xx_PSC_MODE_PARNONE;
1200     }
1201 
1202     mr2 = 0;
1203 
1204     if (new->c_cflag & CSTOPB)
1205         mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1206     else
1207         mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1208             MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1209             MPC52xx_PSC_MODE_ONE_STOP;
1210 
1211     if (new->c_cflag & CRTSCTS) {
1212         mr1 |= MPC52xx_PSC_MODE_RXRTS;
1213         mr2 |= MPC52xx_PSC_MODE_TXCTS;
1214     }
1215 
1216     /* Get the lock */
1217     spin_lock_irqsave(&port->lock, flags);
1218 
1219     /* Do our best to flush TX & RX, so we don't lose anything */
1220     /* But we don't wait indefinitely ! */
1221     j = 5000000;    /* Maximum wait */
1222     /* FIXME Can't receive chars since set_termios might be called at early
1223      * boot for the console, all stuff is not yet ready to receive at that
1224      * time and that just makes the kernel oops */
1225     /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1226     while (!mpc52xx_uart_tx_empty(port) && --j)
1227         udelay(1);
1228 
1229     if (!j)
1230         printk(KERN_ERR "mpc52xx_uart.c: "
1231             "Unable to flush RX & TX fifos in-time in set_termios."
1232             "Some chars may have been lost.\n");
1233 
1234     /* Reset the TX & RX */
1235     psc_ops->command(port, MPC52xx_PSC_RST_RX);
1236     psc_ops->command(port, MPC52xx_PSC_RST_TX);
1237 
1238     /* Send new mode settings */
1239     psc_ops->set_mode(port, mr1, mr2);
1240     baud = psc_ops->set_baudrate(port, new, old);
1241 
1242     /* Update the per-port timeout */
1243     uart_update_timeout(port, new->c_cflag, baud);
1244 
1245     if (UART_ENABLE_MS(port, new->c_cflag))
1246         mpc52xx_uart_enable_ms(port);
1247 
1248     /* Reenable TX & RX */
1249     psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1250     psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1251 
1252     /* We're all set, release the lock */
1253     spin_unlock_irqrestore(&port->lock, flags);
1254 }
1255 
1256 static const char *
1257 mpc52xx_uart_type(struct uart_port *port)
1258 {
1259     /*
1260      * We keep using PORT_MPC52xx for historic reasons although it applies
1261      * for MPC512x, too, but print "MPC5xxx" to not irritate users
1262      */
1263     return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1264 }
1265 
1266 static void
1267 mpc52xx_uart_release_port(struct uart_port *port)
1268 {
1269     if (psc_ops->clock_relse)
1270         psc_ops->clock_relse(port);
1271 
1272     /* remapped by us ? */
1273     if (port->flags & UPF_IOREMAP) {
1274         iounmap(port->membase);
1275         port->membase = NULL;
1276     }
1277 
1278     release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1279 }
1280 
1281 static int
1282 mpc52xx_uart_request_port(struct uart_port *port)
1283 {
1284     int err;
1285 
1286     if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1287         port->membase = ioremap(port->mapbase,
1288                     sizeof(struct mpc52xx_psc));
1289 
1290     if (!port->membase)
1291         return -EINVAL;
1292 
1293     err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1294             "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1295 
1296     if (err)
1297         goto out_membase;
1298 
1299     if (psc_ops->clock_alloc) {
1300         err = psc_ops->clock_alloc(port);
1301         if (err)
1302             goto out_mapregion;
1303     }
1304 
1305     return 0;
1306 
1307 out_mapregion:
1308     release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1309 out_membase:
1310     if (port->flags & UPF_IOREMAP) {
1311         iounmap(port->membase);
1312         port->membase = NULL;
1313     }
1314     return err;
1315 }
1316 
1317 static void
1318 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1319 {
1320     if ((flags & UART_CONFIG_TYPE)
1321         && (mpc52xx_uart_request_port(port) == 0))
1322         port->type = PORT_MPC52xx;
1323 }
1324 
1325 static int
1326 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1327 {
1328     if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1329         return -EINVAL;
1330 
1331     if ((ser->irq != port->irq) ||
1332         (ser->io_type != UPIO_MEM) ||
1333         (ser->baud_base != port->uartclk)  ||
1334         (ser->iomem_base != (void *)port->mapbase) ||
1335         (ser->hub6 != 0))
1336         return -EINVAL;
1337 
1338     return 0;
1339 }
1340 
1341 
1342 static const struct uart_ops mpc52xx_uart_ops = {
1343     .tx_empty   = mpc52xx_uart_tx_empty,
1344     .set_mctrl  = mpc52xx_uart_set_mctrl,
1345     .get_mctrl  = mpc52xx_uart_get_mctrl,
1346     .stop_tx    = mpc52xx_uart_stop_tx,
1347     .start_tx   = mpc52xx_uart_start_tx,
1348     .stop_rx    = mpc52xx_uart_stop_rx,
1349     .enable_ms  = mpc52xx_uart_enable_ms,
1350     .break_ctl  = mpc52xx_uart_break_ctl,
1351     .startup    = mpc52xx_uart_startup,
1352     .shutdown   = mpc52xx_uart_shutdown,
1353     .set_termios    = mpc52xx_uart_set_termios,
1354 /*  .pm     = mpc52xx_uart_pm,      Not supported yet */
1355     .type       = mpc52xx_uart_type,
1356     .release_port   = mpc52xx_uart_release_port,
1357     .request_port   = mpc52xx_uart_request_port,
1358     .config_port    = mpc52xx_uart_config_port,
1359     .verify_port    = mpc52xx_uart_verify_port
1360 };
1361 
1362 
1363 /* ======================================================================== */
1364 /* Interrupt handling                                                       */
1365 /* ======================================================================== */
1366 
1367 static inline unsigned int
1368 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1369 {
1370     struct tty_port *tport = &port->state->port;
1371     unsigned char ch, flag;
1372     unsigned short status;
1373 
1374     /* While we can read, do so ! */
1375     while (psc_ops->raw_rx_rdy(port)) {
1376         /* Get the char */
1377         ch = psc_ops->read_char(port);
1378 
1379         /* Handle sysreq char */
1380         if (uart_handle_sysrq_char(port, ch))
1381             continue;
1382 
1383         /* Store it */
1384 
1385         flag = TTY_NORMAL;
1386         port->icount.rx++;
1387 
1388         status = psc_ops->get_status(port);
1389 
1390         if (status & (MPC52xx_PSC_SR_PE |
1391                   MPC52xx_PSC_SR_FE |
1392                   MPC52xx_PSC_SR_RB)) {
1393 
1394             if (status & MPC52xx_PSC_SR_RB) {
1395                 flag = TTY_BREAK;
1396                 uart_handle_break(port);
1397                 port->icount.brk++;
1398             } else if (status & MPC52xx_PSC_SR_PE) {
1399                 flag = TTY_PARITY;
1400                 port->icount.parity++;
1401             }
1402             else if (status & MPC52xx_PSC_SR_FE) {
1403                 flag = TTY_FRAME;
1404                 port->icount.frame++;
1405             }
1406 
1407             /* Clear error condition */
1408             psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1409 
1410         }
1411         tty_insert_flip_char(tport, ch, flag);
1412         if (status & MPC52xx_PSC_SR_OE) {
1413             /*
1414              * Overrun is special, since it's
1415              * reported immediately, and doesn't
1416              * affect the current character
1417              */
1418             tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1419             port->icount.overrun++;
1420         }
1421     }
1422 
1423     tty_flip_buffer_push(tport);
1424 
1425     return psc_ops->raw_rx_rdy(port);
1426 }
1427 
1428 static inline int
1429 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1430 {
1431     struct circ_buf *xmit = &port->state->xmit;
1432 
1433     /* Process out of band chars */
1434     if (port->x_char) {
1435         psc_ops->write_char(port, port->x_char);
1436         port->icount.tx++;
1437         port->x_char = 0;
1438         return 1;
1439     }
1440 
1441     /* Nothing to do ? */
1442     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1443         mpc52xx_uart_stop_tx(port);
1444         return 0;
1445     }
1446 
1447     /* Send chars */
1448     while (psc_ops->raw_tx_rdy(port)) {
1449         psc_ops->write_char(port, xmit->buf[xmit->tail]);
1450         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1451         port->icount.tx++;
1452         if (uart_circ_empty(xmit))
1453             break;
1454     }
1455 
1456     /* Wake up */
1457     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1458         uart_write_wakeup(port);
1459 
1460     /* Maybe we're done after all */
1461     if (uart_circ_empty(xmit)) {
1462         mpc52xx_uart_stop_tx(port);
1463         return 0;
1464     }
1465 
1466     return 1;
1467 }
1468 
1469 static irqreturn_t
1470 mpc5xxx_uart_process_int(struct uart_port *port)
1471 {
1472     unsigned long pass = ISR_PASS_LIMIT;
1473     unsigned int keepgoing;
1474     u8 status;
1475 
1476     /* While we have stuff to do, we continue */
1477     do {
1478         /* If we don't find anything to do, we stop */
1479         keepgoing = 0;
1480 
1481         psc_ops->rx_clr_irq(port);
1482         if (psc_ops->rx_rdy(port))
1483             keepgoing |= mpc52xx_uart_int_rx_chars(port);
1484 
1485         psc_ops->tx_clr_irq(port);
1486         if (psc_ops->tx_rdy(port))
1487             keepgoing |= mpc52xx_uart_int_tx_chars(port);
1488 
1489         status = psc_ops->get_ipcr(port);
1490         if (status & MPC52xx_PSC_D_DCD)
1491             uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1492 
1493         if (status & MPC52xx_PSC_D_CTS)
1494             uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1495 
1496         /* Limit number of iteration */
1497         if (!(--pass))
1498             keepgoing = 0;
1499 
1500     } while (keepgoing);
1501 
1502     return IRQ_HANDLED;
1503 }
1504 
1505 static irqreturn_t
1506 mpc52xx_uart_int(int irq, void *dev_id)
1507 {
1508     struct uart_port *port = dev_id;
1509     irqreturn_t ret;
1510 
1511     spin_lock(&port->lock);
1512 
1513     ret = psc_ops->handle_irq(port);
1514 
1515     spin_unlock(&port->lock);
1516 
1517     return ret;
1518 }
1519 
1520 /* ======================================================================== */
1521 /* Console ( if applicable )                                                */
1522 /* ======================================================================== */
1523 
1524 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1525 
1526 static void __init
1527 mpc52xx_console_get_options(struct uart_port *port,
1528                 int *baud, int *parity, int *bits, int *flow)
1529 {
1530     unsigned char mr1;
1531 
1532     pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1533 
1534     /* Read the mode registers */
1535     mr1 = psc_ops->get_mr1(port);
1536 
1537     /* CT{U,L}R are write-only ! */
1538     *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1539 
1540     /* Parse them */
1541     switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1542     case MPC52xx_PSC_MODE_5_BITS:
1543         *bits = 5;
1544         break;
1545     case MPC52xx_PSC_MODE_6_BITS:
1546         *bits = 6;
1547         break;
1548     case MPC52xx_PSC_MODE_7_BITS:
1549         *bits = 7;
1550         break;
1551     case MPC52xx_PSC_MODE_8_BITS:
1552     default:
1553         *bits = 8;
1554     }
1555 
1556     if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1557         *parity = 'n';
1558     else
1559         *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1560 }
1561 
1562 static void
1563 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1564 {
1565     struct uart_port *port = &mpc52xx_uart_ports[co->index];
1566     unsigned int i, j;
1567 
1568     /* Disable interrupts */
1569     psc_ops->cw_disable_ints(port);
1570 
1571     /* Wait the TX buffer to be empty */
1572     j = 5000000;    /* Maximum wait */
1573     while (!mpc52xx_uart_tx_empty(port) && --j)
1574         udelay(1);
1575 
1576     /* Write all the chars */
1577     for (i = 0; i < count; i++, s++) {
1578         /* Line return handling */
1579         if (*s == '\n')
1580             psc_ops->write_char(port, '\r');
1581 
1582         /* Send the char */
1583         psc_ops->write_char(port, *s);
1584 
1585         /* Wait the TX buffer to be empty */
1586         j = 20000;  /* Maximum wait */
1587         while (!mpc52xx_uart_tx_empty(port) && --j)
1588             udelay(1);
1589     }
1590 
1591     /* Restore interrupt state */
1592     psc_ops->cw_restore_ints(port);
1593 }
1594 
1595 
1596 static int __init
1597 mpc52xx_console_setup(struct console *co, char *options)
1598 {
1599     struct uart_port *port = &mpc52xx_uart_ports[co->index];
1600     struct device_node *np = mpc52xx_uart_nodes[co->index];
1601     unsigned int uartclk;
1602     struct resource res;
1603     int ret;
1604 
1605     int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1606     int bits = 8;
1607     int parity = 'n';
1608     int flow = 'n';
1609 
1610     pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1611          co, co->index, options);
1612 
1613     if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1614         pr_debug("PSC%x out of range\n", co->index);
1615         return -EINVAL;
1616     }
1617 
1618     if (!np) {
1619         pr_debug("PSC%x not found in device tree\n", co->index);
1620         return -EINVAL;
1621     }
1622 
1623     pr_debug("Console on ttyPSC%x is %pOF\n",
1624          co->index, mpc52xx_uart_nodes[co->index]);
1625 
1626     /* Fetch register locations */
1627     ret = of_address_to_resource(np, 0, &res);
1628     if (ret) {
1629         pr_debug("Could not get resources for PSC%x\n", co->index);
1630         return ret;
1631     }
1632 
1633     uartclk = mpc5xxx_fwnode_get_bus_frequency(of_fwnode_handle(np));
1634     if (uartclk == 0) {
1635         pr_debug("Could not find uart clock frequency!\n");
1636         return -EINVAL;
1637     }
1638 
1639     /* Basic port init. Needed since we use some uart_??? func before
1640      * real init for early access */
1641     spin_lock_init(&port->lock);
1642     port->uartclk = uartclk;
1643     port->ops   = &mpc52xx_uart_ops;
1644     port->mapbase = res.start;
1645     port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1646     port->irq = irq_of_parse_and_map(np, 0);
1647 
1648     if (port->membase == NULL)
1649         return -EINVAL;
1650 
1651     pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1652          (void *)port->mapbase, port->membase,
1653          port->irq, port->uartclk);
1654 
1655     /* Setup the port parameters accoding to options */
1656     if (options)
1657         uart_parse_options(options, &baud, &parity, &bits, &flow);
1658     else
1659         mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1660 
1661     pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1662          baud, bits, parity, flow);
1663 
1664     return uart_set_options(port, co, baud, parity, bits, flow);
1665 }
1666 
1667 
1668 static struct uart_driver mpc52xx_uart_driver;
1669 
1670 static struct console mpc52xx_console = {
1671     .name   = "ttyPSC",
1672     .write  = mpc52xx_console_write,
1673     .device = uart_console_device,
1674     .setup  = mpc52xx_console_setup,
1675     .flags  = CON_PRINTBUFFER,
1676     .index  = -1,   /* Specified on the cmdline (e.g. console=ttyPSC0) */
1677     .data   = &mpc52xx_uart_driver,
1678 };
1679 
1680 
1681 static int __init
1682 mpc52xx_console_init(void)
1683 {
1684     mpc52xx_uart_of_enumerate();
1685     register_console(&mpc52xx_console);
1686     return 0;
1687 }
1688 
1689 console_initcall(mpc52xx_console_init);
1690 
1691 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1692 #else
1693 #define MPC52xx_PSC_CONSOLE NULL
1694 #endif
1695 
1696 
1697 /* ======================================================================== */
1698 /* UART Driver                                                              */
1699 /* ======================================================================== */
1700 
1701 static struct uart_driver mpc52xx_uart_driver = {
1702     .driver_name    = "mpc52xx_psc_uart",
1703     .dev_name   = "ttyPSC",
1704     .major      = SERIAL_PSC_MAJOR,
1705     .minor      = SERIAL_PSC_MINOR,
1706     .nr     = MPC52xx_PSC_MAXNUM,
1707     .cons       = MPC52xx_PSC_CONSOLE,
1708 };
1709 
1710 /* ======================================================================== */
1711 /* OF Platform Driver                                                       */
1712 /* ======================================================================== */
1713 
1714 static const struct of_device_id mpc52xx_uart_of_match[] = {
1715 #ifdef CONFIG_PPC_MPC52xx
1716     { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1717     { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1718     /* binding used by old lite5200 device trees: */
1719     { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1720     /* binding used by efika: */
1721     { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1722 #endif
1723 #ifdef CONFIG_PPC_MPC512x
1724     { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1725     { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1726 #endif
1727     {},
1728 };
1729 
1730 static int mpc52xx_uart_of_probe(struct platform_device *op)
1731 {
1732     int idx = -1;
1733     unsigned int uartclk;
1734     struct uart_port *port = NULL;
1735     struct resource res;
1736     int ret;
1737 
1738     /* Check validity & presence */
1739     for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1740         if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1741             break;
1742     if (idx >= MPC52xx_PSC_MAXNUM)
1743         return -EINVAL;
1744     pr_debug("Found %pOF assigned to ttyPSC%x\n",
1745          mpc52xx_uart_nodes[idx], idx);
1746 
1747     /* set the uart clock to the input clock of the psc, the different
1748      * prescalers are taken into account in the set_baudrate() methods
1749      * of the respective chip */
1750     uartclk = mpc5xxx_get_bus_frequency(&op->dev);
1751     if (uartclk == 0) {
1752         dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1753         return -EINVAL;
1754     }
1755 
1756     /* Init the port structure */
1757     port = &mpc52xx_uart_ports[idx];
1758 
1759     spin_lock_init(&port->lock);
1760     port->uartclk = uartclk;
1761     port->fifosize  = 512;
1762     port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE);
1763     port->iotype    = UPIO_MEM;
1764     port->flags = UPF_BOOT_AUTOCONF |
1765               (uart_console(port) ? 0 : UPF_IOREMAP);
1766     port->line  = idx;
1767     port->ops   = &mpc52xx_uart_ops;
1768     port->dev   = &op->dev;
1769 
1770     /* Search for IRQ and mapbase */
1771     ret = of_address_to_resource(op->dev.of_node, 0, &res);
1772     if (ret)
1773         return ret;
1774 
1775     port->mapbase = res.start;
1776     if (!port->mapbase) {
1777         dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1778         return -EINVAL;
1779     }
1780 
1781     psc_ops->get_irq(port, op->dev.of_node);
1782     if (port->irq == 0) {
1783         dev_dbg(&op->dev, "Could not get irq\n");
1784         return -EINVAL;
1785     }
1786 
1787     dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1788         (void *)port->mapbase, port->irq, port->uartclk);
1789 
1790     /* Add the port to the uart sub-system */
1791     ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1792     if (ret)
1793         return ret;
1794 
1795     platform_set_drvdata(op, (void *)port);
1796     return 0;
1797 }
1798 
1799 static int
1800 mpc52xx_uart_of_remove(struct platform_device *op)
1801 {
1802     struct uart_port *port = platform_get_drvdata(op);
1803 
1804     if (port)
1805         uart_remove_one_port(&mpc52xx_uart_driver, port);
1806 
1807     return 0;
1808 }
1809 
1810 #ifdef CONFIG_PM
1811 static int
1812 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1813 {
1814     struct uart_port *port = platform_get_drvdata(op);
1815 
1816     if (port)
1817         uart_suspend_port(&mpc52xx_uart_driver, port);
1818 
1819     return 0;
1820 }
1821 
1822 static int
1823 mpc52xx_uart_of_resume(struct platform_device *op)
1824 {
1825     struct uart_port *port = platform_get_drvdata(op);
1826 
1827     if (port)
1828         uart_resume_port(&mpc52xx_uart_driver, port);
1829 
1830     return 0;
1831 }
1832 #endif
1833 
1834 static void
1835 mpc52xx_uart_of_assign(struct device_node *np)
1836 {
1837     int i;
1838 
1839     /* Find the first free PSC number */
1840     for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1841         if (mpc52xx_uart_nodes[i] == NULL) {
1842             of_node_get(np);
1843             mpc52xx_uart_nodes[i] = np;
1844             return;
1845         }
1846     }
1847 }
1848 
1849 static void
1850 mpc52xx_uart_of_enumerate(void)
1851 {
1852     static int enum_done;
1853     struct device_node *np;
1854     const struct  of_device_id *match;
1855     int i;
1856 
1857     if (enum_done)
1858         return;
1859 
1860     /* Assign index to each PSC in device tree */
1861     for_each_matching_node(np, mpc52xx_uart_of_match) {
1862         match = of_match_node(mpc52xx_uart_of_match, np);
1863         psc_ops = match->data;
1864         mpc52xx_uart_of_assign(np);
1865     }
1866 
1867     enum_done = 1;
1868 
1869     for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1870         if (mpc52xx_uart_nodes[i])
1871             pr_debug("%pOF assigned to ttyPSC%x\n",
1872                  mpc52xx_uart_nodes[i], i);
1873     }
1874 }
1875 
1876 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1877 
1878 static struct platform_driver mpc52xx_uart_of_driver = {
1879     .probe      = mpc52xx_uart_of_probe,
1880     .remove     = mpc52xx_uart_of_remove,
1881 #ifdef CONFIG_PM
1882     .suspend    = mpc52xx_uart_of_suspend,
1883     .resume     = mpc52xx_uart_of_resume,
1884 #endif
1885     .driver = {
1886         .name = "mpc52xx-psc-uart",
1887         .of_match_table = mpc52xx_uart_of_match,
1888     },
1889 };
1890 
1891 
1892 /* ======================================================================== */
1893 /* Module                                                                   */
1894 /* ======================================================================== */
1895 
1896 static int __init
1897 mpc52xx_uart_init(void)
1898 {
1899     int ret;
1900 
1901     printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1902 
1903     ret = uart_register_driver(&mpc52xx_uart_driver);
1904     if (ret) {
1905         printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1906                __FILE__, ret);
1907         return ret;
1908     }
1909 
1910     mpc52xx_uart_of_enumerate();
1911 
1912     /*
1913      * Map the PSC FIFO Controller and init if on MPC512x.
1914      */
1915     if (psc_ops && psc_ops->fifoc_init) {
1916         ret = psc_ops->fifoc_init();
1917         if (ret)
1918             goto err_init;
1919     }
1920 
1921     ret = platform_driver_register(&mpc52xx_uart_of_driver);
1922     if (ret) {
1923         printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1924                __FILE__, ret);
1925         goto err_reg;
1926     }
1927 
1928     return 0;
1929 err_reg:
1930     if (psc_ops && psc_ops->fifoc_uninit)
1931         psc_ops->fifoc_uninit();
1932 err_init:
1933     uart_unregister_driver(&mpc52xx_uart_driver);
1934     return ret;
1935 }
1936 
1937 static void __exit
1938 mpc52xx_uart_exit(void)
1939 {
1940     if (psc_ops->fifoc_uninit)
1941         psc_ops->fifoc_uninit();
1942 
1943     platform_driver_unregister(&mpc52xx_uart_of_driver);
1944     uart_unregister_driver(&mpc52xx_uart_driver);
1945 }
1946 
1947 
1948 module_init(mpc52xx_uart_init);
1949 module_exit(mpc52xx_uart_exit);
1950 
1951 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1952 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1953 MODULE_LICENSE("GPL");
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