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0006 #include <linux/clk.h>
0007 #include <linux/console.h>
0008 #include <linux/module.h>
0009 #include <linux/of_irq.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/serial_core.h>
0012 #include <linux/tty.h>
0013 #include <linux/tty_flip.h>
0014
0015 #define USIO_NAME "mlb-usio-uart"
0016 #define USIO_UART_DEV_NAME "ttyUSI"
0017
0018 static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
0019
0020 #define RX 0
0021 #define TX 1
0022 static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
0023
0024 #define MLB_USIO_REG_SMR 0
0025 #define MLB_USIO_REG_SCR 1
0026 #define MLB_USIO_REG_ESCR 2
0027 #define MLB_USIO_REG_SSR 3
0028 #define MLB_USIO_REG_DR 4
0029 #define MLB_USIO_REG_BGR 6
0030 #define MLB_USIO_REG_FCR 12
0031 #define MLB_USIO_REG_FBYTE 14
0032
0033 #define MLB_USIO_SMR_SOE BIT(0)
0034 #define MLB_USIO_SMR_SBL BIT(3)
0035 #define MLB_USIO_SCR_TXE BIT(0)
0036 #define MLB_USIO_SCR_RXE BIT(1)
0037 #define MLB_USIO_SCR_TBIE BIT(2)
0038 #define MLB_USIO_SCR_TIE BIT(3)
0039 #define MLB_USIO_SCR_RIE BIT(4)
0040 #define MLB_USIO_SCR_UPCL BIT(7)
0041 #define MLB_USIO_ESCR_L_8BIT 0
0042 #define MLB_USIO_ESCR_L_5BIT 1
0043 #define MLB_USIO_ESCR_L_6BIT 2
0044 #define MLB_USIO_ESCR_L_7BIT 3
0045 #define MLB_USIO_ESCR_P BIT(3)
0046 #define MLB_USIO_ESCR_PEN BIT(4)
0047 #define MLB_USIO_ESCR_FLWEN BIT(7)
0048 #define MLB_USIO_SSR_TBI BIT(0)
0049 #define MLB_USIO_SSR_TDRE BIT(1)
0050 #define MLB_USIO_SSR_RDRF BIT(2)
0051 #define MLB_USIO_SSR_ORE BIT(3)
0052 #define MLB_USIO_SSR_FRE BIT(4)
0053 #define MLB_USIO_SSR_PE BIT(5)
0054 #define MLB_USIO_SSR_REC BIT(7)
0055 #define MLB_USIO_SSR_BRK BIT(8)
0056 #define MLB_USIO_FCR_FE1 BIT(0)
0057 #define MLB_USIO_FCR_FE2 BIT(1)
0058 #define MLB_USIO_FCR_FCL1 BIT(2)
0059 #define MLB_USIO_FCR_FCL2 BIT(3)
0060 #define MLB_USIO_FCR_FSET BIT(4)
0061 #define MLB_USIO_FCR_FTIE BIT(9)
0062 #define MLB_USIO_FCR_FDRQ BIT(10)
0063 #define MLB_USIO_FCR_FRIIE BIT(11)
0064
0065 static void mlb_usio_stop_tx(struct uart_port *port)
0066 {
0067 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
0068 port->membase + MLB_USIO_REG_FCR);
0069 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
0070 port->membase + MLB_USIO_REG_SCR);
0071 }
0072
0073 static void mlb_usio_tx_chars(struct uart_port *port)
0074 {
0075 struct circ_buf *xmit = &port->state->xmit;
0076 int count;
0077
0078 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
0079 port->membase + MLB_USIO_REG_FCR);
0080 writeb(readb(port->membase + MLB_USIO_REG_SCR) &
0081 ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
0082 port->membase + MLB_USIO_REG_SCR);
0083
0084 if (port->x_char) {
0085 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
0086 port->icount.tx++;
0087 port->x_char = 0;
0088 return;
0089 }
0090 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0091 mlb_usio_stop_tx(port);
0092 return;
0093 }
0094
0095 count = port->fifosize -
0096 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
0097
0098 do {
0099 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
0100
0101 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0102 port->icount.tx++;
0103 if (uart_circ_empty(xmit))
0104 break;
0105
0106 } while (--count > 0);
0107
0108 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
0109 port->membase + MLB_USIO_REG_FCR);
0110
0111 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
0112 port->membase + MLB_USIO_REG_SCR);
0113
0114 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0115 uart_write_wakeup(port);
0116
0117 if (uart_circ_empty(xmit))
0118 mlb_usio_stop_tx(port);
0119 }
0120
0121 static void mlb_usio_start_tx(struct uart_port *port)
0122 {
0123 u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
0124
0125 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
0126 if (!(fcr & MLB_USIO_FCR_FDRQ))
0127 return;
0128
0129 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
0130 port->membase + MLB_USIO_REG_SCR);
0131
0132 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
0133 mlb_usio_tx_chars(port);
0134 }
0135
0136 static void mlb_usio_stop_rx(struct uart_port *port)
0137 {
0138 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
0139 port->membase + MLB_USIO_REG_SCR);
0140 }
0141
0142 static void mlb_usio_enable_ms(struct uart_port *port)
0143 {
0144 writeb(readb(port->membase + MLB_USIO_REG_SCR) |
0145 MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
0146 port->membase + MLB_USIO_REG_SCR);
0147 }
0148
0149 static void mlb_usio_rx_chars(struct uart_port *port)
0150 {
0151 struct tty_port *ttyport = &port->state->port;
0152 unsigned long flag = 0;
0153 char ch = 0;
0154 u8 status;
0155 int max_count = 2;
0156
0157 while (max_count--) {
0158 status = readb(port->membase + MLB_USIO_REG_SSR);
0159
0160 if (!(status & MLB_USIO_SSR_RDRF))
0161 break;
0162
0163 if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
0164 MLB_USIO_SSR_PE))) {
0165 ch = readw(port->membase + MLB_USIO_REG_DR);
0166 flag = TTY_NORMAL;
0167 port->icount.rx++;
0168 if (uart_handle_sysrq_char(port, ch))
0169 continue;
0170 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
0171 ch, flag);
0172 continue;
0173 }
0174 if (status & MLB_USIO_SSR_PE)
0175 port->icount.parity++;
0176 if (status & MLB_USIO_SSR_ORE)
0177 port->icount.overrun++;
0178 status &= port->read_status_mask;
0179 if (status & MLB_USIO_SSR_BRK) {
0180 flag = TTY_BREAK;
0181 ch = 0;
0182 } else
0183 if (status & MLB_USIO_SSR_PE) {
0184 flag = TTY_PARITY;
0185 ch = 0;
0186 } else
0187 if (status & MLB_USIO_SSR_FRE) {
0188 flag = TTY_FRAME;
0189 ch = 0;
0190 }
0191 if (flag)
0192 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
0193 ch, flag);
0194
0195 writeb(readb(port->membase + MLB_USIO_REG_SSR) |
0196 MLB_USIO_SSR_REC,
0197 port->membase + MLB_USIO_REG_SSR);
0198
0199 max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
0200 writew(readw(port->membase + MLB_USIO_REG_FCR) |
0201 MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
0202 port->membase + MLB_USIO_REG_FCR);
0203 }
0204
0205 tty_flip_buffer_push(ttyport);
0206 }
0207
0208 static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
0209 {
0210 struct uart_port *port = dev_id;
0211
0212 spin_lock(&port->lock);
0213 mlb_usio_rx_chars(port);
0214 spin_unlock(&port->lock);
0215
0216 return IRQ_HANDLED;
0217 }
0218
0219 static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
0220 {
0221 struct uart_port *port = dev_id;
0222
0223 spin_lock(&port->lock);
0224 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
0225 mlb_usio_tx_chars(port);
0226 spin_unlock(&port->lock);
0227
0228 return IRQ_HANDLED;
0229 }
0230
0231 static unsigned int mlb_usio_tx_empty(struct uart_port *port)
0232 {
0233 return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
0234 TIOCSER_TEMT : 0;
0235 }
0236
0237 static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
0238 {
0239 }
0240
0241 static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
0242 {
0243 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
0244
0245 }
0246
0247 static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
0248 {
0249 }
0250
0251 static int mlb_usio_startup(struct uart_port *port)
0252 {
0253 const char *portname = to_platform_device(port->dev)->name;
0254 unsigned long flags;
0255 int ret, index = port->line;
0256 unsigned char escr;
0257
0258 ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
0259 0, portname, port);
0260 if (ret)
0261 return ret;
0262 ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
0263 0, portname, port);
0264 if (ret) {
0265 free_irq(mlb_usio_irq[index][RX], port);
0266 return ret;
0267 }
0268
0269 escr = readb(port->membase + MLB_USIO_REG_ESCR);
0270 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
0271 escr |= MLB_USIO_ESCR_FLWEN;
0272 spin_lock_irqsave(&port->lock, flags);
0273 writeb(0, port->membase + MLB_USIO_REG_SCR);
0274 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
0275 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
0276 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
0277 writew(0, port->membase + MLB_USIO_REG_FCR);
0278 writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
0279 port->membase + MLB_USIO_REG_FCR);
0280 writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
0281 port->membase + MLB_USIO_REG_FCR);
0282 writew(0, port->membase + MLB_USIO_REG_FBYTE);
0283 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
0284
0285 writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
0286 MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
0287 spin_unlock_irqrestore(&port->lock, flags);
0288
0289 return 0;
0290 }
0291
0292 static void mlb_usio_shutdown(struct uart_port *port)
0293 {
0294 int index = port->line;
0295
0296 free_irq(mlb_usio_irq[index][RX], port);
0297 free_irq(mlb_usio_irq[index][TX], port);
0298 }
0299
0300 static void mlb_usio_set_termios(struct uart_port *port,
0301 struct ktermios *termios, struct ktermios *old)
0302 {
0303 unsigned int escr, smr = MLB_USIO_SMR_SOE;
0304 unsigned long flags, baud, quot;
0305
0306 switch (termios->c_cflag & CSIZE) {
0307 case CS5:
0308 escr = MLB_USIO_ESCR_L_5BIT;
0309 break;
0310 case CS6:
0311 escr = MLB_USIO_ESCR_L_6BIT;
0312 break;
0313 case CS7:
0314 escr = MLB_USIO_ESCR_L_7BIT;
0315 break;
0316 case CS8:
0317 default:
0318 escr = MLB_USIO_ESCR_L_8BIT;
0319 break;
0320 }
0321
0322 if (termios->c_cflag & CSTOPB)
0323 smr |= MLB_USIO_SMR_SBL;
0324
0325 if (termios->c_cflag & PARENB) {
0326 escr |= MLB_USIO_ESCR_PEN;
0327 if (termios->c_cflag & PARODD)
0328 escr |= MLB_USIO_ESCR_P;
0329 }
0330
0331 if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
0332 (termios->c_cflag & CRTSCTS))
0333 escr |= MLB_USIO_ESCR_FLWEN;
0334
0335 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
0336 if (baud > 1)
0337 quot = port->uartclk / baud - 1;
0338 else
0339 quot = 0;
0340
0341 spin_lock_irqsave(&port->lock, flags);
0342 uart_update_timeout(port, termios->c_cflag, baud);
0343 port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
0344 MLB_USIO_SSR_TDRE;
0345 if (termios->c_iflag & INPCK)
0346 port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
0347
0348 port->ignore_status_mask = 0;
0349 if (termios->c_iflag & IGNPAR)
0350 port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
0351 if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
0352 port->ignore_status_mask |= MLB_USIO_SSR_ORE;
0353 if ((termios->c_cflag & CREAD) == 0)
0354 port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
0355
0356 writeb(0, port->membase + MLB_USIO_REG_SCR);
0357 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
0358 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
0359 writew(0, port->membase + MLB_USIO_REG_FCR);
0360 writeb(smr, port->membase + MLB_USIO_REG_SMR);
0361 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
0362 writew(quot, port->membase + MLB_USIO_REG_BGR);
0363 writew(0, port->membase + MLB_USIO_REG_FCR);
0364 writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
0365 MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
0366 port->membase + MLB_USIO_REG_FCR);
0367 writew(0, port->membase + MLB_USIO_REG_FBYTE);
0368 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
0369 writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
0370 MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
0371 spin_unlock_irqrestore(&port->lock, flags);
0372 }
0373
0374 static const char *mlb_usio_type(struct uart_port *port)
0375 {
0376 return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
0377 }
0378
0379 static void mlb_usio_config_port(struct uart_port *port, int flags)
0380 {
0381 if (flags & UART_CONFIG_TYPE)
0382 port->type = PORT_MLB_USIO;
0383 }
0384
0385 static const struct uart_ops mlb_usio_ops = {
0386 .tx_empty = mlb_usio_tx_empty,
0387 .set_mctrl = mlb_usio_set_mctrl,
0388 .get_mctrl = mlb_usio_get_mctrl,
0389 .stop_tx = mlb_usio_stop_tx,
0390 .start_tx = mlb_usio_start_tx,
0391 .stop_rx = mlb_usio_stop_rx,
0392 .enable_ms = mlb_usio_enable_ms,
0393 .break_ctl = mlb_usio_break_ctl,
0394 .startup = mlb_usio_startup,
0395 .shutdown = mlb_usio_shutdown,
0396 .set_termios = mlb_usio_set_termios,
0397 .type = mlb_usio_type,
0398 .config_port = mlb_usio_config_port,
0399 };
0400
0401 #ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
0402
0403 static void mlb_usio_console_putchar(struct uart_port *port, unsigned char c)
0404 {
0405 while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
0406 cpu_relax();
0407
0408 writew(c, port->membase + MLB_USIO_REG_DR);
0409 }
0410
0411 static void mlb_usio_console_write(struct console *co, const char *s,
0412 unsigned int count)
0413 {
0414 struct uart_port *port = &mlb_usio_ports[co->index];
0415
0416 uart_console_write(port, s, count, mlb_usio_console_putchar);
0417 }
0418
0419 static int __init mlb_usio_console_setup(struct console *co, char *options)
0420 {
0421 struct uart_port *port;
0422 int baud = 115200;
0423 int parity = 'n';
0424 int flow = 'n';
0425 int bits = 8;
0426
0427 if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
0428 return -ENODEV;
0429
0430 port = &mlb_usio_ports[co->index];
0431 if (!port->membase)
0432 return -ENODEV;
0433
0434
0435 if (options)
0436 uart_parse_options(options, &baud, &parity, &bits, &flow);
0437
0438 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
0439 flow = 'r';
0440
0441 return uart_set_options(port, co, baud, parity, bits, flow);
0442 }
0443
0444
0445 static struct uart_driver mlb_usio_uart_driver;
0446 static struct console mlb_usio_console = {
0447 .name = USIO_UART_DEV_NAME,
0448 .write = mlb_usio_console_write,
0449 .device = uart_console_device,
0450 .setup = mlb_usio_console_setup,
0451 .flags = CON_PRINTBUFFER,
0452 .index = -1,
0453 .data = &mlb_usio_uart_driver,
0454 };
0455
0456 static int __init mlb_usio_console_init(void)
0457 {
0458 register_console(&mlb_usio_console);
0459 return 0;
0460 }
0461 console_initcall(mlb_usio_console_init);
0462
0463
0464 static void mlb_usio_early_console_write(struct console *co, const char *s,
0465 u_int count)
0466 {
0467 struct earlycon_device *dev = co->data;
0468
0469 uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
0470 }
0471
0472 static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
0473 const char *opt)
0474 {
0475 if (!device->port.membase)
0476 return -ENODEV;
0477 device->con->write = mlb_usio_early_console_write;
0478 return 0;
0479 }
0480
0481 OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
0482 mlb_usio_early_console_setup);
0483
0484 #define USIO_CONSOLE (&mlb_usio_console)
0485 #else
0486 #define USIO_CONSOLE NULL
0487 #endif
0488
0489 static struct uart_driver mlb_usio_uart_driver = {
0490 .owner = THIS_MODULE,
0491 .driver_name = USIO_NAME,
0492 .dev_name = USIO_UART_DEV_NAME,
0493 .cons = USIO_CONSOLE,
0494 .nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
0495 };
0496
0497 static int mlb_usio_probe(struct platform_device *pdev)
0498 {
0499 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
0500 struct uart_port *port;
0501 struct resource *res;
0502 int index = 0;
0503 int ret;
0504
0505 if (IS_ERR(clk)) {
0506 dev_err(&pdev->dev, "Missing clock\n");
0507 return PTR_ERR(clk);
0508 }
0509 ret = clk_prepare_enable(clk);
0510 if (ret) {
0511 dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
0512 return ret;
0513 }
0514 of_property_read_u32(pdev->dev.of_node, "index", &index);
0515 port = &mlb_usio_ports[index];
0516
0517 port->private_data = (void *)clk;
0518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0519 if (res == NULL) {
0520 dev_err(&pdev->dev, "Missing regs\n");
0521 ret = -ENODEV;
0522 goto failed;
0523 }
0524 port->membase = devm_ioremap(&pdev->dev, res->start,
0525 resource_size(res));
0526
0527 ret = platform_get_irq_byname(pdev, "rx");
0528 mlb_usio_irq[index][RX] = ret;
0529
0530 ret = platform_get_irq_byname(pdev, "tx");
0531 mlb_usio_irq[index][TX] = ret;
0532
0533 port->irq = mlb_usio_irq[index][RX];
0534 port->uartclk = clk_get_rate(clk);
0535 port->fifosize = 128;
0536 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE);
0537 port->iotype = UPIO_MEM32;
0538 port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
0539 port->line = index;
0540 port->ops = &mlb_usio_ops;
0541 port->dev = &pdev->dev;
0542
0543 ret = uart_add_one_port(&mlb_usio_uart_driver, port);
0544 if (ret) {
0545 dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
0546 goto failed;
0547 }
0548 return 0;
0549
0550 failed:
0551 clk_disable_unprepare(clk);
0552
0553 return ret;
0554 }
0555
0556 static int mlb_usio_remove(struct platform_device *pdev)
0557 {
0558 struct uart_port *port = &mlb_usio_ports[pdev->id];
0559 struct clk *clk = port->private_data;
0560
0561 uart_remove_one_port(&mlb_usio_uart_driver, port);
0562 clk_disable_unprepare(clk);
0563
0564 return 0;
0565 }
0566
0567 static const struct of_device_id mlb_usio_dt_ids[] = {
0568 { .compatible = "socionext,milbeaut-usio-uart" },
0569 { }
0570 };
0571 MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
0572
0573 static struct platform_driver mlb_usio_driver = {
0574 .probe = mlb_usio_probe,
0575 .remove = mlb_usio_remove,
0576 .driver = {
0577 .name = USIO_NAME,
0578 .of_match_table = mlb_usio_dt_ids,
0579 },
0580 };
0581
0582 static int __init mlb_usio_init(void)
0583 {
0584 int ret = uart_register_driver(&mlb_usio_uart_driver);
0585
0586 if (ret) {
0587 pr_err("%s: uart registration failed: %d\n", __func__, ret);
0588 return ret;
0589 }
0590 ret = platform_driver_register(&mlb_usio_driver);
0591 if (ret) {
0592 uart_unregister_driver(&mlb_usio_uart_driver);
0593 pr_err("%s: drv registration failed: %d\n", __func__, ret);
0594 return ret;
0595 }
0596
0597 return 0;
0598 }
0599
0600 static void __exit mlb_usio_exit(void)
0601 {
0602 platform_driver_unregister(&mlb_usio_driver);
0603 uart_unregister_driver(&mlb_usio_uart_driver);
0604 }
0605
0606 module_init(mlb_usio_init);
0607 module_exit(mlb_usio_exit);
0608
0609 MODULE_AUTHOR("SOCIONEXT");
0610 MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
0611 MODULE_LICENSE("GPL");
