tty/serial/men_z135_uart.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MEN 16z135 High Speed UART
0004  *
0005  * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
0006  * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
0007  */
0008 #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
0009
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/serial_core.h>
0014 #include <linux/ioport.h>
0015 #include <linux/io.h>
0016 #include <linux/tty_flip.h>
0017 #include <linux/bitops.h>
0018 #include <linux/mcb.h>
0019
0020 #define MEN_Z135_MAX_PORTS      12
0021 #define MEN_Z135_BASECLK        29491200
0022 #define MEN_Z135_FIFO_SIZE      1024
0023 #define MEN_Z135_FIFO_WATERMARK     1020
0024
0025 #define MEN_Z135_STAT_REG       0x0
0026 #define MEN_Z135_RX_RAM         0x4
0027 #define MEN_Z135_TX_RAM         0x400
0028 #define MEN_Z135_RX_CTRL        0x800
0029 #define MEN_Z135_TX_CTRL        0x804
0030 #define MEN_Z135_CONF_REG       0x808
0031 #define MEN_Z135_UART_FREQ      0x80c
0032 #define MEN_Z135_BAUD_REG       0x810
0033 #define MEN_Z135_TIMEOUT        0x814
0034
0035 #define IRQ_ID(x) ((x) & 0x1f)
0036
0037 #define MEN_Z135_IER_RXCIEN BIT(0)      /* RX Space IRQ */
0038 #define MEN_Z135_IER_TXCIEN BIT(1)      /* TX Space IRQ */
0039 #define MEN_Z135_IER_RLSIEN BIT(2)      /* Receiver Line Status IRQ */
0040 #define MEN_Z135_IER_MSIEN  BIT(3)      /* Modem Status IRQ */
0041 #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN      \
0042                 | MEN_Z135_IER_RLSIEN   \
0043                 | MEN_Z135_IER_MSIEN    \
0044                 | MEN_Z135_IER_TXCIEN)
0045
0046 #define MEN_Z135_MCR_DTR    BIT(24)
0047 #define MEN_Z135_MCR_RTS    BIT(25)
0048 #define MEN_Z135_MCR_OUT1   BIT(26)
0049 #define MEN_Z135_MCR_OUT2   BIT(27)
0050 #define MEN_Z135_MCR_LOOP   BIT(28)
0051 #define MEN_Z135_MCR_RCFC   BIT(29)
0052
0053 #define MEN_Z135_MSR_DCTS   BIT(0)
0054 #define MEN_Z135_MSR_DDSR   BIT(1)
0055 #define MEN_Z135_MSR_DRI    BIT(2)
0056 #define MEN_Z135_MSR_DDCD   BIT(3)
0057 #define MEN_Z135_MSR_CTS    BIT(4)
0058 #define MEN_Z135_MSR_DSR    BIT(5)
0059 #define MEN_Z135_MSR_RI     BIT(6)
0060 #define MEN_Z135_MSR_DCD    BIT(7)
0061
0062 #define MEN_Z135_LCR_SHIFT 8    /* LCR shift mask */
0063
0064 #define MEN_Z135_WL5 0      /* CS5 */
0065 #define MEN_Z135_WL6 1      /* CS6 */
0066 #define MEN_Z135_WL7 2      /* CS7 */
0067 #define MEN_Z135_WL8 3      /* CS8 */
0068
0069 #define MEN_Z135_STB_SHIFT 2    /* Stopbits */
0070 #define MEN_Z135_NSTB1 0
0071 #define MEN_Z135_NSTB2 1
0072
0073 #define MEN_Z135_PEN_SHIFT 3    /* Parity enable */
0074 #define MEN_Z135_PAR_DIS 0
0075 #define MEN_Z135_PAR_ENA 1
0076
0077 #define MEN_Z135_PTY_SHIFT 4    /* Parity type */
0078 #define MEN_Z135_PTY_ODD 0
0079 #define MEN_Z135_PTY_EVN 1
0080
0081 #define MEN_Z135_LSR_DR BIT(0)
0082 #define MEN_Z135_LSR_OE BIT(1)
0083 #define MEN_Z135_LSR_PE BIT(2)
0084 #define MEN_Z135_LSR_FE BIT(3)
0085 #define MEN_Z135_LSR_BI BIT(4)
0086 #define MEN_Z135_LSR_THEP BIT(5)
0087 #define MEN_Z135_LSR_TEXP BIT(6)
0088 #define MEN_Z135_LSR_RXFIFOERR BIT(7)
0089
0090 #define MEN_Z135_IRQ_ID_RLS BIT(0)
0091 #define MEN_Z135_IRQ_ID_RDA BIT(1)
0092 #define MEN_Z135_IRQ_ID_CTI BIT(2)
0093 #define MEN_Z135_IRQ_ID_TSA BIT(3)
0094 #define MEN_Z135_IRQ_ID_MST BIT(4)
0095
0096 #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
0097
0098 #define BYTES_TO_ALIGN(x) ((x) & 0x3)
0099
0100 static int line;
0101
0102 static int txlvl = 5;
0103 module_param(txlvl, int, S_IRUGO);
0104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
0105
0106 static int rxlvl = 6;
0107 module_param(rxlvl, int, S_IRUGO);
0108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
0109
0110 static int align;
0111 module_param(align, int, S_IRUGO);
0112 MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
0113
0114 static uint rx_timeout;
0115 module_param(rx_timeout, uint, S_IRUGO);
0116 MODULE_PARM_DESC(rx_timeout, "RX timeout. "
0117         "Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
0118
0119 struct men_z135_port {
0120     struct uart_port port;
0121     struct mcb_device *mdev;
0122     struct resource *mem;
0123     unsigned char *rxbuf;
0124     u32 stat_reg;
0125     spinlock_t lock;
0126     bool automode;
0127 };
0128 #define to_men_z135(port) container_of((port), struct men_z135_port, port)
0129
0130 /**
0131  * men_z135_reg_set() - Set value in register
0132  * @uart: The UART port
0133  * @addr: Register address
0134  * @val: value to set
0135  */
0136 static inline void men_z135_reg_set(struct men_z135_port *uart,
0137                 u32 addr, u32 val)
0138 {
0139     struct uart_port *port = &uart->port;
0140     unsigned long flags;
0141     u32 reg;
0142
0143     spin_lock_irqsave(&uart->lock, flags);
0144
0145     reg = ioread32(port->membase + addr);
0146     reg |= val;
0147     iowrite32(reg, port->membase + addr);
0148
0149     spin_unlock_irqrestore(&uart->lock, flags);
0150 }
0151
0152 /**
0153  * men_z135_reg_clr() - Unset value in register
0154  * @uart: The UART port
0155  * @addr: Register address
0156  * @val: value to clear
0157  */
0158 static void men_z135_reg_clr(struct men_z135_port *uart,
0159                 u32 addr, u32 val)
0160 {
0161     struct uart_port *port = &uart->port;
0162     unsigned long flags;
0163     u32 reg;
0164
0165     spin_lock_irqsave(&uart->lock, flags);
0166
0167     reg = ioread32(port->membase + addr);
0168     reg &= ~val;
0169     iowrite32(reg, port->membase + addr);
0170
0171     spin_unlock_irqrestore(&uart->lock, flags);
0172 }
0173
0174 /**
0175  * men_z135_handle_modem_status() - Handle change of modem status
0176  * @uart: The UART port
0177  *
0178  * Handle change of modem status register. This is done by reading the "delta"
0179  * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
0180  */
0181 static void men_z135_handle_modem_status(struct men_z135_port *uart)
0182 {
0183     u8 msr;
0184
0185     msr = (uart->stat_reg >> 8) & 0xff;
0186
0187     if (msr & MEN_Z135_MSR_DDCD)
0188         uart_handle_dcd_change(&uart->port,
0189                 msr & MEN_Z135_MSR_DCD);
0190     if (msr & MEN_Z135_MSR_DCTS)
0191         uart_handle_cts_change(&uart->port,
0192                 msr & MEN_Z135_MSR_CTS);
0193 }
0194
0195 static void men_z135_handle_lsr(struct men_z135_port *uart)
0196 {
0197     struct uart_port *port = &uart->port;
0198     u8 lsr;
0199
0200     lsr = (uart->stat_reg >> 16) & 0xff;
0201
0202     if (lsr & MEN_Z135_LSR_OE)
0203         port->icount.overrun++;
0204     if (lsr & MEN_Z135_LSR_PE)
0205         port->icount.parity++;
0206     if (lsr & MEN_Z135_LSR_FE)
0207         port->icount.frame++;
0208     if (lsr & MEN_Z135_LSR_BI) {
0209         port->icount.brk++;
0210         uart_handle_break(port);
0211     }
0212 }
0213
0214 /**
0215  * get_rx_fifo_content() - Get the number of bytes in RX FIFO
0216  * @uart: The UART port
0217  *
0218  * Read RXC register from hardware and return current FIFO fill size.
0219  */
0220 static u16 get_rx_fifo_content(struct men_z135_port *uart)
0221 {
0222     struct uart_port *port = &uart->port;
0223     u32 stat_reg;
0224     u16 rxc;
0225     u8 rxc_lo;
0226     u8 rxc_hi;
0227
0228     stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
0229     rxc_lo = stat_reg >> 24;
0230     rxc_hi = (stat_reg & 0xC0) >> 6;
0231
0232     rxc = rxc_lo | (rxc_hi << 8);
0233
0234     return rxc;
0235 }
0236
0237 /**
0238  * men_z135_handle_rx() - RX tasklet routine
0239  * @uart: Pointer to struct men_z135_port
0240  *
0241  * Copy from RX FIFO and acknowledge number of bytes copied.
0242  */
0243 static void men_z135_handle_rx(struct men_z135_port *uart)
0244 {
0245     struct uart_port *port = &uart->port;
0246     struct tty_port *tport = &port->state->port;
0247     int copied;
0248     u16 size;
0249     int room;
0250
0251     size = get_rx_fifo_content(uart);
0252
0253     if (size == 0)
0254         return;
0255
0256     /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
0257      * longword in RX FIFO cannot be read.(0x004-0x3FF)
0258      */
0259     if (size > MEN_Z135_FIFO_WATERMARK)
0260         size = MEN_Z135_FIFO_WATERMARK;
0261
0262     room = tty_buffer_request_room(tport, size);
0263     if (room != size)
0264         dev_warn(&uart->mdev->dev,
0265             "Not enough room in flip buffer, truncating to %d\n",
0266             room);
0267
0268     if (room == 0)
0269         return;
0270
0271     memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
0272     /* Be sure to first copy all data and then acknowledge it */
0273     mb();
0274     iowrite32(room, port->membase +  MEN_Z135_RX_CTRL);
0275
0276     copied = tty_insert_flip_string(tport, uart->rxbuf, room);
0277     if (copied != room)
0278         dev_warn(&uart->mdev->dev,
0279             "Only copied %d instead of %d bytes\n",
0280             copied, room);
0281
0282     port->icount.rx += copied;
0283
0284     tty_flip_buffer_push(tport);
0285
0286 }
0287
0288 /**
0289  * men_z135_handle_tx() - TX tasklet routine
0290  * @uart: Pointer to struct men_z135_port
0291  *
0292  */
0293 static void men_z135_handle_tx(struct men_z135_port *uart)
0294 {
0295     struct uart_port *port = &uart->port;
0296     struct circ_buf *xmit = &port->state->xmit;
0297     u32 txc;
0298     u32 wptr;
0299     int qlen;
0300     int n;
0301     int txfree;
0302     int head;
0303     int tail;
0304     int s;
0305
0306     if (uart_circ_empty(xmit))
0307         goto out;
0308
0309     if (uart_tx_stopped(port))
0310         goto out;
0311
0312     if (port->x_char)
0313         goto out;
0314
0315     /* calculate bytes to copy */
0316     qlen = uart_circ_chars_pending(xmit);
0317     if (qlen <= 0)
0318         goto out;
0319
0320     wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
0321     txc = (wptr >> 16) & 0x3ff;
0322     wptr &= 0x3ff;
0323
0324     if (txc > MEN_Z135_FIFO_WATERMARK)
0325         txc = MEN_Z135_FIFO_WATERMARK;
0326
0327     txfree = MEN_Z135_FIFO_WATERMARK - txc;
0328     if (txfree <= 0) {
0329         dev_err(&uart->mdev->dev,
0330             "Not enough room in TX FIFO have %d, need %d\n",
0331             txfree, qlen);
0332         goto irq_en;
0333     }
0334
0335     /* if we're not aligned, it's better to copy only 1 or 2 bytes and
0336      * then the rest.
0337      */
0338     if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
0339         n = 4 - BYTES_TO_ALIGN(wptr);
0340     else if (qlen > txfree)
0341         n = txfree;
0342     else
0343         n = qlen;
0344
0345     if (n <= 0)
0346         goto irq_en;
0347
0348     head = xmit->head & (UART_XMIT_SIZE - 1);
0349     tail = xmit->tail & (UART_XMIT_SIZE - 1);
0350
0351     s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
0352     n = min(n, s);
0353
0354     memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
0355     xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
0356
0357     iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
0358
0359     port->icount.tx += n;
0360
0361     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0362         uart_write_wakeup(port);
0363
0364 irq_en:
0365     if (!uart_circ_empty(xmit))
0366         men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
0367     else
0368         men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
0369
0370 out:
0371     return;
0372
0373 }
0374
0375 /**
0376  * men_z135_intr() - Handle legacy IRQs
0377  * @irq: The IRQ number
0378  * @data: Pointer to UART port
0379  *
0380  * Check IIR register to find the cause of the interrupt and handle it.
0381  * It is possible that multiple interrupts reason bits are set and reading
0382  * the IIR is a destructive read, so we always need to check for all possible
0383  * interrupts and handle them.
0384  */
0385 static irqreturn_t men_z135_intr(int irq, void *data)
0386 {
0387     struct men_z135_port *uart = (struct men_z135_port *)data;
0388     struct uart_port *port = &uart->port;
0389     bool handled = false;
0390     int irq_id;
0391
0392     uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
0393     irq_id = IRQ_ID(uart->stat_reg);
0394
0395     if (!irq_id)
0396         goto out;
0397
0398     spin_lock(&port->lock);
0399     /* It's save to write to IIR[7:6] RXC[9:8] */
0400     iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
0401
0402     if (irq_id & MEN_Z135_IRQ_ID_RLS) {
0403         men_z135_handle_lsr(uart);
0404         handled = true;
0405     }
0406
0407     if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
0408         if (irq_id & MEN_Z135_IRQ_ID_CTI)
0409             dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
0410         men_z135_handle_rx(uart);
0411         handled = true;
0412     }
0413
0414     if (irq_id & MEN_Z135_IRQ_ID_TSA) {
0415         men_z135_handle_tx(uart);
0416         handled = true;
0417     }
0418
0419     if (irq_id & MEN_Z135_IRQ_ID_MST) {
0420         men_z135_handle_modem_status(uart);
0421         handled = true;
0422     }
0423
0424     spin_unlock(&port->lock);
0425 out:
0426     return IRQ_RETVAL(handled);
0427 }
0428
0429 /**
0430  * men_z135_request_irq() - Request IRQ for 16z135 core
0431  * @uart: z135 private uart port structure
0432  *
0433  * Request an IRQ for 16z135 to use. First try using MSI, if it fails
0434  * fall back to using legacy interrupts.
0435  */
0436 static int men_z135_request_irq(struct men_z135_port *uart)
0437 {
0438     struct device *dev = &uart->mdev->dev;
0439     struct uart_port *port = &uart->port;
0440     int err = 0;
0441
0442     err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
0443             "men_z135_intr", uart);
0444     if (err)
0445         dev_err(dev, "Error %d getting interrupt\n", err);
0446
0447     return err;
0448 }
0449
0450 /**
0451  * men_z135_tx_empty() - Handle tx_empty call
0452  * @port: The UART port
0453  *
0454  * This function tests whether the TX FIFO and shifter for the port
0455  * described by @port is empty.
0456  */
0457 static unsigned int men_z135_tx_empty(struct uart_port *port)
0458 {
0459     u32 wptr;
0460     u16 txc;
0461
0462     wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
0463     txc = (wptr >> 16) & 0x3ff;
0464
0465     if (txc == 0)
0466         return TIOCSER_TEMT;
0467     else
0468         return 0;
0469 }
0470
0471 /**
0472  * men_z135_set_mctrl() - Set modem control lines
0473  * @port: The UART port
0474  * @mctrl: The modem control lines
0475  *
0476  * This function sets the modem control lines for a port described by @port
0477  * to the state described by @mctrl
0478  */
0479 static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
0480 {
0481     u32 old;
0482     u32 conf_reg;
0483
0484     conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
0485     if (mctrl & TIOCM_RTS)
0486         conf_reg |= MEN_Z135_MCR_RTS;
0487     else
0488         conf_reg &= ~MEN_Z135_MCR_RTS;
0489
0490     if (mctrl & TIOCM_DTR)
0491         conf_reg |= MEN_Z135_MCR_DTR;
0492     else
0493         conf_reg &= ~MEN_Z135_MCR_DTR;
0494
0495     if (mctrl & TIOCM_OUT1)
0496         conf_reg |= MEN_Z135_MCR_OUT1;
0497     else
0498         conf_reg &= ~MEN_Z135_MCR_OUT1;
0499
0500     if (mctrl & TIOCM_OUT2)
0501         conf_reg |= MEN_Z135_MCR_OUT2;
0502     else
0503         conf_reg &= ~MEN_Z135_MCR_OUT2;
0504
0505     if (mctrl & TIOCM_LOOP)
0506         conf_reg |= MEN_Z135_MCR_LOOP;
0507     else
0508         conf_reg &= ~MEN_Z135_MCR_LOOP;
0509
0510     if (conf_reg != old)
0511         iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
0512 }
0513
0514 /**
0515  * men_z135_get_mctrl() - Get modem control lines
0516  * @port: The UART port
0517  *
0518  * Retruns the current state of modem control inputs.
0519  */
0520 static unsigned int men_z135_get_mctrl(struct uart_port *port)
0521 {
0522     unsigned int mctrl = 0;
0523     u8 msr;
0524
0525     msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
0526
0527     if (msr & MEN_Z135_MSR_CTS)
0528         mctrl |= TIOCM_CTS;
0529     if (msr & MEN_Z135_MSR_DSR)
0530         mctrl |= TIOCM_DSR;
0531     if (msr & MEN_Z135_MSR_RI)
0532         mctrl |= TIOCM_RI;
0533     if (msr & MEN_Z135_MSR_DCD)
0534         mctrl |= TIOCM_CAR;
0535
0536     return mctrl;
0537 }
0538
0539 /**
0540  * men_z135_stop_tx() - Stop transmitting characters
0541  * @port: The UART port
0542  *
0543  * Stop transmitting characters. This might be due to CTS line becomming
0544  * inactive or the tty layer indicating we want to stop transmission due to
0545  * an XOFF character.
0546  */
0547 static void men_z135_stop_tx(struct uart_port *port)
0548 {
0549     struct men_z135_port *uart = to_men_z135(port);
0550
0551     men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
0552 }
0553
0554 /*
0555  * men_z135_disable_ms() - Disable Modem Status
0556  * port: The UART port
0557  *
0558  * Enable Modem Status IRQ.
0559  */
0560 static void men_z135_disable_ms(struct uart_port *port)
0561 {
0562     struct men_z135_port *uart = to_men_z135(port);
0563
0564     men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
0565 }
0566
0567 /**
0568  * men_z135_start_tx() - Start transmitting characters
0569  * @port: The UART port
0570  *
0571  * Start transmitting character. This actually doesn't transmit anything, but
0572  * fires off the TX tasklet.
0573  */
0574 static void men_z135_start_tx(struct uart_port *port)
0575 {
0576     struct men_z135_port *uart = to_men_z135(port);
0577
0578     if (uart->automode)
0579         men_z135_disable_ms(port);
0580
0581     men_z135_handle_tx(uart);
0582 }
0583
0584 /**
0585  * men_z135_stop_rx() - Stop receiving characters
0586  * @port: The UART port
0587  *
0588  * Stop receiving characters; the port is in the process of being closed.
0589  */
0590 static void men_z135_stop_rx(struct uart_port *port)
0591 {
0592     struct men_z135_port *uart = to_men_z135(port);
0593
0594     men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
0595 }
0596
0597 /**
0598  * men_z135_enable_ms() - Enable Modem Status
0599  * @port: the port
0600  *
0601  * Enable Modem Status IRQ.
0602  */
0603 static void men_z135_enable_ms(struct uart_port *port)
0604 {
0605     struct men_z135_port *uart = to_men_z135(port);
0606
0607     men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
0608 }
0609
0610 static int men_z135_startup(struct uart_port *port)
0611 {
0612     struct men_z135_port *uart = to_men_z135(port);
0613     int err;
0614     u32 conf_reg = 0;
0615
0616     err = men_z135_request_irq(uart);
0617     if (err)
0618         return -ENODEV;
0619
0620     conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
0621
0622     /* Activate all but TX space available IRQ */
0623     conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
0624     conf_reg &= ~(0xff << 16);
0625     conf_reg |= (txlvl << 16);
0626     conf_reg |= (rxlvl << 20);
0627
0628     iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
0629
0630     if (rx_timeout)
0631         iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
0632
0633     return 0;
0634 }
0635
0636 static void men_z135_shutdown(struct uart_port *port)
0637 {
0638     struct men_z135_port *uart = to_men_z135(port);
0639     u32 conf_reg = 0;
0640
0641     conf_reg |= MEN_Z135_ALL_IRQS;
0642
0643     men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
0644
0645     free_irq(uart->port.irq, uart);
0646 }
0647
0648 static void men_z135_set_termios(struct uart_port *port,
0649                 struct ktermios *termios,
0650                 struct ktermios *old)
0651 {
0652     struct men_z135_port *uart = to_men_z135(port);
0653     unsigned int baud;
0654     u32 conf_reg;
0655     u32 bd_reg;
0656     u32 uart_freq;
0657     u8 lcr;
0658
0659     conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
0660     lcr = LCR(conf_reg);
0661
0662     /* byte size */
0663     switch (termios->c_cflag & CSIZE) {
0664     case CS5:
0665         lcr |= MEN_Z135_WL5;
0666         break;
0667     case CS6:
0668         lcr |= MEN_Z135_WL6;
0669         break;
0670     case CS7:
0671         lcr |= MEN_Z135_WL7;
0672         break;
0673     case CS8:
0674         lcr |= MEN_Z135_WL8;
0675         break;
0676     }
0677
0678     /* stop bits */
0679     if (termios->c_cflag & CSTOPB)
0680         lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
0681
0682     /* parity */
0683     if (termios->c_cflag & PARENB) {
0684         lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
0685
0686         if (termios->c_cflag & PARODD)
0687             lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
0688         else
0689             lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
0690     } else
0691         lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
0692
0693     conf_reg |= MEN_Z135_IER_MSIEN;
0694     if (termios->c_cflag & CRTSCTS) {
0695         conf_reg |= MEN_Z135_MCR_RCFC;
0696         uart->automode = true;
0697         termios->c_cflag &= ~CLOCAL;
0698     } else {
0699         conf_reg &= ~MEN_Z135_MCR_RCFC;
0700         uart->automode = false;
0701     }
0702
0703     termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
0704
0705     conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
0706     iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
0707
0708     uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
0709     if (uart_freq == 0)
0710         uart_freq = MEN_Z135_BASECLK;
0711
0712     baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
0713
0714     spin_lock_irq(&port->lock);
0715     if (tty_termios_baud_rate(termios))
0716         tty_termios_encode_baud_rate(termios, baud, baud);
0717
0718     bd_reg = uart_freq / (4 * baud);
0719     iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
0720
0721     uart_update_timeout(port, termios->c_cflag, baud);
0722     spin_unlock_irq(&port->lock);
0723 }
0724
0725 static const char *men_z135_type(struct uart_port *port)
0726 {
0727     return KBUILD_MODNAME;
0728 }
0729
0730 static void men_z135_release_port(struct uart_port *port)
0731 {
0732     struct men_z135_port *uart = to_men_z135(port);
0733
0734     iounmap(port->membase);
0735     port->membase = NULL;
0736
0737     mcb_release_mem(uart->mem);
0738 }
0739
0740 static int men_z135_request_port(struct uart_port *port)
0741 {
0742     struct men_z135_port *uart = to_men_z135(port);
0743     struct mcb_device *mdev = uart->mdev;
0744     struct resource *mem;
0745
0746     mem = mcb_request_mem(uart->mdev, dev_name(&mdev->dev));
0747     if (IS_ERR(mem))
0748         return PTR_ERR(mem);
0749
0750     port->mapbase = mem->start;
0751     uart->mem = mem;
0752
0753     port->membase = ioremap(mem->start, resource_size(mem));
0754     if (port->membase == NULL) {
0755         mcb_release_mem(mem);
0756         return -ENOMEM;
0757     }
0758
0759     return 0;
0760 }
0761
0762 static void men_z135_config_port(struct uart_port *port, int type)
0763 {
0764     port->type = PORT_MEN_Z135;
0765     men_z135_request_port(port);
0766 }
0767
0768 static int men_z135_verify_port(struct uart_port *port,
0769                 struct serial_struct *serinfo)
0770 {
0771     return -EINVAL;
0772 }
0773
0774 static const struct uart_ops men_z135_ops = {
0775     .tx_empty = men_z135_tx_empty,
0776     .set_mctrl = men_z135_set_mctrl,
0777     .get_mctrl = men_z135_get_mctrl,
0778     .stop_tx = men_z135_stop_tx,
0779     .start_tx = men_z135_start_tx,
0780     .stop_rx = men_z135_stop_rx,
0781     .enable_ms = men_z135_enable_ms,
0782     .startup = men_z135_startup,
0783     .shutdown = men_z135_shutdown,
0784     .set_termios = men_z135_set_termios,
0785     .type = men_z135_type,
0786     .release_port = men_z135_release_port,
0787     .request_port = men_z135_request_port,
0788     .config_port = men_z135_config_port,
0789     .verify_port = men_z135_verify_port,
0790 };
0791
0792 static struct uart_driver men_z135_driver = {
0793     .owner = THIS_MODULE,
0794     .driver_name = KBUILD_MODNAME,
0795     .dev_name = "ttyHSU",
0796     .major = 0,
0797     .minor = 0,
0798     .nr = MEN_Z135_MAX_PORTS,
0799 };
0800
0801 /**
0802  * men_z135_probe() - Probe a z135 instance
0803  * @mdev: The MCB device
0804  * @id: The MCB device ID
0805  *
0806  * men_z135_probe does the basic setup of hardware resources and registers the
0807  * new uart port to the tty layer.
0808  */
0809 static int men_z135_probe(struct mcb_device *mdev,
0810             const struct mcb_device_id *id)
0811 {
0812     struct men_z135_port *uart;
0813     struct resource *mem;
0814     struct device *dev;
0815     int err;
0816
0817     dev = &mdev->dev;
0818
0819     uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
0820     if (!uart)
0821         return -ENOMEM;
0822
0823     uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
0824     if (!uart->rxbuf)
0825         return -ENOMEM;
0826
0827     mem = &mdev->mem;
0828
0829     mcb_set_drvdata(mdev, uart);
0830
0831     uart->port.uartclk = MEN_Z135_BASECLK * 16;
0832     uart->port.fifosize = MEN_Z135_FIFO_SIZE;
0833     uart->port.iotype = UPIO_MEM;
0834     uart->port.ops = &men_z135_ops;
0835     uart->port.irq = mcb_get_irq(mdev);
0836     uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
0837     uart->port.line = line++;
0838     uart->port.dev = dev;
0839     uart->port.type = PORT_MEN_Z135;
0840     uart->port.mapbase = mem->start;
0841     uart->port.membase = NULL;
0842     uart->mdev = mdev;
0843
0844     spin_lock_init(&uart->lock);
0845
0846     err = uart_add_one_port(&men_z135_driver, &uart->port);
0847     if (err)
0848         goto err;
0849
0850     return 0;
0851
0852 err:
0853     free_page((unsigned long) uart->rxbuf);
0854     dev_err(dev, "Failed to add UART: %d\n", err);
0855
0856     return err;
0857 }
0858
0859 /**
0860  * men_z135_remove() - Remove a z135 instance from the system
0861  *
0862  * @mdev: The MCB device
0863  */
0864 static void men_z135_remove(struct mcb_device *mdev)
0865 {
0866     struct men_z135_port *uart = mcb_get_drvdata(mdev);
0867
0868     line--;
0869     uart_remove_one_port(&men_z135_driver, &uart->port);
0870     free_page((unsigned long) uart->rxbuf);
0871 }
0872
0873 static const struct mcb_device_id men_z135_ids[] = {
0874     { .device = 0x87 },
0875     { }
0876 };
0877 MODULE_DEVICE_TABLE(mcb, men_z135_ids);
0878
0879 static struct mcb_driver mcb_driver = {
0880     .driver = {
0881         .name = "z135-uart",
0882         .owner = THIS_MODULE,
0883     },
0884     .probe = men_z135_probe,
0885     .remove = men_z135_remove,
0886     .id_table = men_z135_ids,
0887 };
0888
0889 /**
0890  * men_z135_init() - Driver Registration Routine
0891  *
0892  * men_z135_init is the first routine called when the driver is loaded. All it
0893  * does is register with the legacy MEN Chameleon subsystem.
0894  */
0895 static int __init men_z135_init(void)
0896 {
0897     int err;
0898
0899     err = uart_register_driver(&men_z135_driver);
0900     if (err) {
0901         pr_err("Failed to register UART: %d\n", err);
0902         return err;
0903     }
0904
0905     err = mcb_register_driver(&mcb_driver);
0906     if  (err) {
0907         pr_err("Failed to register MCB driver: %d\n", err);
0908         uart_unregister_driver(&men_z135_driver);
0909         return err;
0910     }
0911
0912     return 0;
0913 }
0914 module_init(men_z135_init);
0915
0916 /**
0917  * men_z135_exit() - Driver Exit Routine
0918  *
0919  * men_z135_exit is called just before the driver is removed from memory.
0920  */
0921 static void __exit men_z135_exit(void)
0922 {
0923     mcb_unregister_driver(&mcb_driver);
0924     uart_unregister_driver(&men_z135_driver);
0925 }
0926 module_exit(men_z135_exit);
0927
0928 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
0929 MODULE_LICENSE("GPL v2");
0930 MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
0931 MODULE_ALIAS("mcb:16z135");
0932 MODULE_IMPORT_NS(MCB);