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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
0004  *
0005  *  Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
0006  *
0007  *  Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
0008  *  Based on max3110.c, by Feng Tang <feng.tang@intel.com>
0009  *  Based on max3107.c, by Aavamobile
0010  */
0011 
0012 #include <linux/bitops.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/device.h>
0016 #include <linux/gpio/driver.h>
0017 #include <linux/i2c.h>
0018 #include <linux/module.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/property.h>
0021 #include <linux/regmap.h>
0022 #include <linux/serial_core.h>
0023 #include <linux/serial.h>
0024 #include <linux/tty.h>
0025 #include <linux/tty_flip.h>
0026 #include <linux/spi/spi.h>
0027 #include <linux/uaccess.h>
0028 
0029 #define MAX310X_NAME            "max310x"
0030 #define MAX310X_MAJOR           204
0031 #define MAX310X_MINOR           209
0032 #define MAX310X_UART_NRMAX      16
0033 
0034 /* MAX310X register definitions */
0035 #define MAX310X_RHR_REG         (0x00) /* RX FIFO */
0036 #define MAX310X_THR_REG         (0x00) /* TX FIFO */
0037 #define MAX310X_IRQEN_REG       (0x01) /* IRQ enable */
0038 #define MAX310X_IRQSTS_REG      (0x02) /* IRQ status */
0039 #define MAX310X_LSR_IRQEN_REG       (0x03) /* LSR IRQ enable */
0040 #define MAX310X_LSR_IRQSTS_REG      (0x04) /* LSR IRQ status */
0041 #define MAX310X_REG_05          (0x05)
0042 #define MAX310X_SPCHR_IRQEN_REG     MAX310X_REG_05 /* Special char IRQ en */
0043 #define MAX310X_SPCHR_IRQSTS_REG    (0x06) /* Special char IRQ status */
0044 #define MAX310X_STS_IRQEN_REG       (0x07) /* Status IRQ enable */
0045 #define MAX310X_STS_IRQSTS_REG      (0x08) /* Status IRQ status */
0046 #define MAX310X_MODE1_REG       (0x09) /* MODE1 */
0047 #define MAX310X_MODE2_REG       (0x0a) /* MODE2 */
0048 #define MAX310X_LCR_REG         (0x0b) /* LCR */
0049 #define MAX310X_RXTO_REG        (0x0c) /* RX timeout */
0050 #define MAX310X_HDPIXDELAY_REG      (0x0d) /* Auto transceiver delays */
0051 #define MAX310X_IRDA_REG        (0x0e) /* IRDA settings */
0052 #define MAX310X_FLOWLVL_REG     (0x0f) /* Flow control levels */
0053 #define MAX310X_FIFOTRIGLVL_REG     (0x10) /* FIFO IRQ trigger levels */
0054 #define MAX310X_TXFIFOLVL_REG       (0x11) /* TX FIFO level */
0055 #define MAX310X_RXFIFOLVL_REG       (0x12) /* RX FIFO level */
0056 #define MAX310X_FLOWCTRL_REG        (0x13) /* Flow control */
0057 #define MAX310X_XON1_REG        (0x14) /* XON1 character */
0058 #define MAX310X_XON2_REG        (0x15) /* XON2 character */
0059 #define MAX310X_XOFF1_REG       (0x16) /* XOFF1 character */
0060 #define MAX310X_XOFF2_REG       (0x17) /* XOFF2 character */
0061 #define MAX310X_GPIOCFG_REG     (0x18) /* GPIO config */
0062 #define MAX310X_GPIODATA_REG        (0x19) /* GPIO data */
0063 #define MAX310X_PLLCFG_REG      (0x1a) /* PLL config */
0064 #define MAX310X_BRGCFG_REG      (0x1b) /* Baud rate generator conf */
0065 #define MAX310X_BRGDIVLSB_REG       (0x1c) /* Baud rate divisor LSB */
0066 #define MAX310X_BRGDIVMSB_REG       (0x1d) /* Baud rate divisor MSB */
0067 #define MAX310X_CLKSRC_REG      (0x1e) /* Clock source */
0068 #define MAX310X_REG_1F          (0x1f)
0069 
0070 #define MAX310X_REVID_REG       MAX310X_REG_1F /* Revision ID */
0071 
0072 #define MAX310X_GLOBALIRQ_REG       MAX310X_REG_1F /* Global IRQ (RO) */
0073 #define MAX310X_GLOBALCMD_REG       MAX310X_REG_1F /* Global Command (WO) */
0074 
0075 /* Extended registers */
0076 #define MAX310X_SPI_REVID_EXTREG    MAX310X_REG_05 /* Revision ID */
0077 #define MAX310X_I2C_REVID_EXTREG    (0x25) /* Revision ID */
0078 
0079 /* IRQ register bits */
0080 #define MAX310X_IRQ_LSR_BIT     (1 << 0) /* LSR interrupt */
0081 #define MAX310X_IRQ_SPCHR_BIT       (1 << 1) /* Special char interrupt */
0082 #define MAX310X_IRQ_STS_BIT     (1 << 2) /* Status interrupt */
0083 #define MAX310X_IRQ_RXFIFO_BIT      (1 << 3) /* RX FIFO interrupt */
0084 #define MAX310X_IRQ_TXFIFO_BIT      (1 << 4) /* TX FIFO interrupt */
0085 #define MAX310X_IRQ_TXEMPTY_BIT     (1 << 5) /* TX FIFO empty interrupt */
0086 #define MAX310X_IRQ_RXEMPTY_BIT     (1 << 6) /* RX FIFO empty interrupt */
0087 #define MAX310X_IRQ_CTS_BIT     (1 << 7) /* CTS interrupt */
0088 
0089 /* LSR register bits */
0090 #define MAX310X_LSR_RXTO_BIT        (1 << 0) /* RX timeout */
0091 #define MAX310X_LSR_RXOVR_BIT       (1 << 1) /* RX overrun */
0092 #define MAX310X_LSR_RXPAR_BIT       (1 << 2) /* RX parity error */
0093 #define MAX310X_LSR_FRERR_BIT       (1 << 3) /* Frame error */
0094 #define MAX310X_LSR_RXBRK_BIT       (1 << 4) /* RX break */
0095 #define MAX310X_LSR_RXNOISE_BIT     (1 << 5) /* RX noise */
0096 #define MAX310X_LSR_CTS_BIT     (1 << 7) /* CTS pin state */
0097 
0098 /* Special character register bits */
0099 #define MAX310X_SPCHR_XON1_BIT      (1 << 0) /* XON1 character */
0100 #define MAX310X_SPCHR_XON2_BIT      (1 << 1) /* XON2 character */
0101 #define MAX310X_SPCHR_XOFF1_BIT     (1 << 2) /* XOFF1 character */
0102 #define MAX310X_SPCHR_XOFF2_BIT     (1 << 3) /* XOFF2 character */
0103 #define MAX310X_SPCHR_BREAK_BIT     (1 << 4) /* RX break */
0104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
0105 
0106 /* Status register bits */
0107 #define MAX310X_STS_GPIO0_BIT       (1 << 0) /* GPIO 0 interrupt */
0108 #define MAX310X_STS_GPIO1_BIT       (1 << 1) /* GPIO 1 interrupt */
0109 #define MAX310X_STS_GPIO2_BIT       (1 << 2) /* GPIO 2 interrupt */
0110 #define MAX310X_STS_GPIO3_BIT       (1 << 3) /* GPIO 3 interrupt */
0111 #define MAX310X_STS_CLKREADY_BIT    (1 << 5) /* Clock ready */
0112 #define MAX310X_STS_SLEEP_BIT       (1 << 6) /* Sleep interrupt */
0113 
0114 /* MODE1 register bits */
0115 #define MAX310X_MODE1_RXDIS_BIT     (1 << 0) /* RX disable */
0116 #define MAX310X_MODE1_TXDIS_BIT     (1 << 1) /* TX disable */
0117 #define MAX310X_MODE1_TXHIZ_BIT     (1 << 2) /* TX pin three-state */
0118 #define MAX310X_MODE1_RTSHIZ_BIT    (1 << 3) /* RTS pin three-state */
0119 #define MAX310X_MODE1_TRNSCVCTRL_BIT    (1 << 4) /* Transceiver ctrl enable */
0120 #define MAX310X_MODE1_FORCESLEEP_BIT    (1 << 5) /* Force sleep mode */
0121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
0122 #define MAX310X_MODE1_IRQSEL_BIT    (1 << 7) /* IRQ pin enable */
0123 
0124 /* MODE2 register bits */
0125 #define MAX310X_MODE2_RST_BIT       (1 << 0) /* Chip reset */
0126 #define MAX310X_MODE2_FIFORST_BIT   (1 << 1) /* FIFO reset */
0127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
0128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
0129 #define MAX310X_MODE2_SPCHR_BIT     (1 << 4) /* Special chr detect enable */
0130 #define MAX310X_MODE2_LOOPBACK_BIT  (1 << 5) /* Internal loopback enable */
0131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
0132 #define MAX310X_MODE2_ECHOSUPR_BIT  (1 << 7) /* ECHO suppression enable */
0133 
0134 /* LCR register bits */
0135 #define MAX310X_LCR_LENGTH0_BIT     (1 << 0) /* Word length bit 0 */
0136 #define MAX310X_LCR_LENGTH1_BIT     (1 << 1) /* Word length bit 1
0137                           *
0138                           * Word length bits table:
0139                           * 00 -> 5 bit words
0140                           * 01 -> 6 bit words
0141                           * 10 -> 7 bit words
0142                           * 11 -> 8 bit words
0143                           */
0144 #define MAX310X_LCR_STOPLEN_BIT     (1 << 2) /* STOP length bit
0145                           *
0146                           * STOP length bit table:
0147                           * 0 -> 1 stop bit
0148                           * 1 -> 1-1.5 stop bits if
0149                           *      word length is 5,
0150                           *      2 stop bits otherwise
0151                           */
0152 #define MAX310X_LCR_PARITY_BIT      (1 << 3) /* Parity bit enable */
0153 #define MAX310X_LCR_EVENPARITY_BIT  (1 << 4) /* Even parity bit enable */
0154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
0155 #define MAX310X_LCR_TXBREAK_BIT     (1 << 6) /* TX break enable */
0156 #define MAX310X_LCR_RTS_BIT     (1 << 7) /* RTS pin control */
0157 
0158 /* IRDA register bits */
0159 #define MAX310X_IRDA_IRDAEN_BIT     (1 << 0) /* IRDA mode enable */
0160 #define MAX310X_IRDA_SIR_BIT        (1 << 1) /* SIR mode enable */
0161 
0162 /* Flow control trigger level register masks */
0163 #define MAX310X_FLOWLVL_HALT_MASK   (0x000f) /* Flow control halt level */
0164 #define MAX310X_FLOWLVL_RES_MASK    (0x00f0) /* Flow control resume level */
0165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
0166 #define MAX310X_FLOWLVL_RES(words)  (((words / 8) & 0x0f) << 4)
0167 
0168 /* FIFO interrupt trigger level register masks */
0169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
0170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
0171 #define MAX310X_FIFOTRIGLVL_TX(words)   ((words / 8) & 0x0f)
0172 #define MAX310X_FIFOTRIGLVL_RX(words)   (((words / 8) & 0x0f) << 4)
0173 
0174 /* Flow control register bits */
0175 #define MAX310X_FLOWCTRL_AUTORTS_BIT    (1 << 0) /* Auto RTS flow ctrl enable */
0176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT    (1 << 1) /* Auto CTS flow ctrl enable */
0177 #define MAX310X_FLOWCTRL_GPIADDR_BIT    (1 << 2) /* Enables that GPIO inputs
0178                           * are used in conjunction with
0179                           * XOFF2 for definition of
0180                           * special character */
0181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT   (1 << 3) /* Auto SW flow ctrl enable */
0182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT    (1 << 4) /* SWFLOW bit 0 */
0183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT    (1 << 5) /* SWFLOW bit 1
0184                           *
0185                           * SWFLOW bits 1 & 0 table:
0186                           * 00 -> no transmitter flow
0187                           *       control
0188                           * 01 -> receiver compares
0189                           *       XON2 and XOFF2
0190                           *       and controls
0191                           *       transmitter
0192                           * 10 -> receiver compares
0193                           *       XON1 and XOFF1
0194                           *       and controls
0195                           *       transmitter
0196                           * 11 -> receiver compares
0197                           *       XON1, XON2, XOFF1 and
0198                           *       XOFF2 and controls
0199                           *       transmitter
0200                           */
0201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT    (1 << 6) /* SWFLOW bit 2 */
0202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT    (1 << 7) /* SWFLOW bit 3
0203                           *
0204                           * SWFLOW bits 3 & 2 table:
0205                           * 00 -> no received flow
0206                           *       control
0207                           * 01 -> transmitter generates
0208                           *       XON2 and XOFF2
0209                           * 10 -> transmitter generates
0210                           *       XON1 and XOFF1
0211                           * 11 -> transmitter generates
0212                           *       XON1, XON2, XOFF1 and
0213                           *       XOFF2
0214                           */
0215 
0216 /* PLL configuration register masks */
0217 #define MAX310X_PLLCFG_PREDIV_MASK  (0x3f) /* PLL predivision value */
0218 #define MAX310X_PLLCFG_PLLFACTOR_MASK   (0xc0) /* PLL multiplication factor */
0219 
0220 /* Baud rate generator configuration register bits */
0221 #define MAX310X_BRGCFG_2XMODE_BIT   (1 << 4) /* Double baud rate */
0222 #define MAX310X_BRGCFG_4XMODE_BIT   (1 << 5) /* Quadruple baud rate */
0223 
0224 /* Clock source register bits */
0225 #define MAX310X_CLKSRC_CRYST_BIT    (1 << 1) /* Crystal osc enable */
0226 #define MAX310X_CLKSRC_PLL_BIT      (1 << 2) /* PLL enable */
0227 #define MAX310X_CLKSRC_PLLBYP_BIT   (1 << 3) /* PLL bypass */
0228 #define MAX310X_CLKSRC_EXTCLK_BIT   (1 << 4) /* External clock enable */
0229 #define MAX310X_CLKSRC_CLK2RTS_BIT  (1 << 7) /* Baud clk to RTS pin */
0230 
0231 /* Global commands */
0232 #define MAX310X_EXTREG_ENBL     (0xce)
0233 #define MAX310X_EXTREG_DSBL     (0xcd)
0234 
0235 /* Misc definitions */
0236 #define MAX310X_FIFO_SIZE       (128)
0237 #define MAX310x_REV_MASK        (0xf8)
0238 #define MAX310X_WRITE_BIT       0x80
0239 
0240 /* MAX3107 specific */
0241 #define MAX3107_REV_ID          (0xa0)
0242 
0243 /* MAX3109 specific */
0244 #define MAX3109_REV_ID          (0xc0)
0245 
0246 /* MAX14830 specific */
0247 #define MAX14830_BRGCFG_CLKDIS_BIT  (1 << 6) /* Clock Disable */
0248 #define MAX14830_REV_ID         (0xb0)
0249 
0250 struct max310x_if_cfg {
0251     int (*extended_reg_enable)(struct device *dev, bool enable);
0252 
0253     unsigned int rev_id_reg;
0254 };
0255 
0256 struct max310x_devtype {
0257     struct {
0258         unsigned short min;
0259         unsigned short max;
0260     } slave_addr;
0261     char    name[9];
0262     int nr;
0263     u8  mode1;
0264     int (*detect)(struct device *);
0265     void    (*power)(struct uart_port *, int);
0266 };
0267 
0268 struct max310x_one {
0269     struct uart_port    port;
0270     struct work_struct  tx_work;
0271     struct work_struct  md_work;
0272     struct work_struct  rs_work;
0273     struct regmap       *regmap;
0274 
0275     u8 rx_buf[MAX310X_FIFO_SIZE];
0276 };
0277 #define to_max310x_port(_port) \
0278     container_of(_port, struct max310x_one, port)
0279 
0280 struct max310x_port {
0281     const struct max310x_devtype *devtype;
0282     const struct max310x_if_cfg *if_cfg;
0283     struct regmap       *regmap;
0284     struct clk      *clk;
0285 #ifdef CONFIG_GPIOLIB
0286     struct gpio_chip    gpio;
0287 #endif
0288     struct max310x_one  p[];
0289 };
0290 
0291 static struct uart_driver max310x_uart = {
0292     .owner      = THIS_MODULE,
0293     .driver_name    = MAX310X_NAME,
0294     .dev_name   = "ttyMAX",
0295     .major      = MAX310X_MAJOR,
0296     .minor      = MAX310X_MINOR,
0297     .nr     = MAX310X_UART_NRMAX,
0298 };
0299 
0300 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
0301 
0302 static u8 max310x_port_read(struct uart_port *port, u8 reg)
0303 {
0304     struct max310x_one *one = to_max310x_port(port);
0305     unsigned int val = 0;
0306 
0307     regmap_read(one->regmap, reg, &val);
0308 
0309     return val;
0310 }
0311 
0312 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
0313 {
0314     struct max310x_one *one = to_max310x_port(port);
0315 
0316     regmap_write(one->regmap, reg, val);
0317 }
0318 
0319 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
0320 {
0321     struct max310x_one *one = to_max310x_port(port);
0322 
0323     regmap_update_bits(one->regmap, reg, mask, val);
0324 }
0325 
0326 static int max3107_detect(struct device *dev)
0327 {
0328     struct max310x_port *s = dev_get_drvdata(dev);
0329     unsigned int val = 0;
0330     int ret;
0331 
0332     ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
0333     if (ret)
0334         return ret;
0335 
0336     if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
0337         dev_err(dev,
0338             "%s ID 0x%02x does not match\n", s->devtype->name, val);
0339         return -ENODEV;
0340     }
0341 
0342     return 0;
0343 }
0344 
0345 static int max3108_detect(struct device *dev)
0346 {
0347     struct max310x_port *s = dev_get_drvdata(dev);
0348     unsigned int val = 0;
0349     int ret;
0350 
0351     /* MAX3108 have not REV ID register, we just check default value
0352      * from clocksource register to make sure everything works.
0353      */
0354     ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
0355     if (ret)
0356         return ret;
0357 
0358     if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
0359         dev_err(dev, "%s not present\n", s->devtype->name);
0360         return -ENODEV;
0361     }
0362 
0363     return 0;
0364 }
0365 
0366 static int max3109_detect(struct device *dev)
0367 {
0368     struct max310x_port *s = dev_get_drvdata(dev);
0369     unsigned int val = 0;
0370     int ret;
0371 
0372     ret = s->if_cfg->extended_reg_enable(dev, true);
0373     if (ret)
0374         return ret;
0375 
0376     regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
0377     s->if_cfg->extended_reg_enable(dev, false);
0378     if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
0379         dev_err(dev,
0380             "%s ID 0x%02x does not match\n", s->devtype->name, val);
0381         return -ENODEV;
0382     }
0383 
0384     return 0;
0385 }
0386 
0387 static void max310x_power(struct uart_port *port, int on)
0388 {
0389     max310x_port_update(port, MAX310X_MODE1_REG,
0390                 MAX310X_MODE1_FORCESLEEP_BIT,
0391                 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
0392     if (on)
0393         msleep(50);
0394 }
0395 
0396 static int max14830_detect(struct device *dev)
0397 {
0398     struct max310x_port *s = dev_get_drvdata(dev);
0399     unsigned int val = 0;
0400     int ret;
0401 
0402     ret = s->if_cfg->extended_reg_enable(dev, true);
0403     if (ret)
0404         return ret;
0405     
0406     regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
0407     s->if_cfg->extended_reg_enable(dev, false);
0408     if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
0409         dev_err(dev,
0410             "%s ID 0x%02x does not match\n", s->devtype->name, val);
0411         return -ENODEV;
0412     }
0413 
0414     return 0;
0415 }
0416 
0417 static void max14830_power(struct uart_port *port, int on)
0418 {
0419     max310x_port_update(port, MAX310X_BRGCFG_REG,
0420                 MAX14830_BRGCFG_CLKDIS_BIT,
0421                 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
0422     if (on)
0423         msleep(50);
0424 }
0425 
0426 static const struct max310x_devtype max3107_devtype = {
0427     .name   = "MAX3107",
0428     .nr = 1,
0429     .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
0430     .detect = max3107_detect,
0431     .power  = max310x_power,
0432     .slave_addr = {
0433         .min = 0x2c,
0434         .max = 0x2f,
0435     },
0436 };
0437 
0438 static const struct max310x_devtype max3108_devtype = {
0439     .name   = "MAX3108",
0440     .nr = 1,
0441     .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT,
0442     .detect = max3108_detect,
0443     .power  = max310x_power,
0444     .slave_addr = {
0445         .min = 0x60,
0446         .max = 0x6f,
0447     },
0448 };
0449 
0450 static const struct max310x_devtype max3109_devtype = {
0451     .name   = "MAX3109",
0452     .nr = 2,
0453     .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT,
0454     .detect = max3109_detect,
0455     .power  = max310x_power,
0456     .slave_addr = {
0457         .min = 0x60,
0458         .max = 0x6f,
0459     },
0460 };
0461 
0462 static const struct max310x_devtype max14830_devtype = {
0463     .name   = "MAX14830",
0464     .nr = 4,
0465     .mode1  = MAX310X_MODE1_IRQSEL_BIT,
0466     .detect = max14830_detect,
0467     .power  = max14830_power,
0468     .slave_addr = {
0469         .min = 0x60,
0470         .max = 0x6f,
0471     },
0472 };
0473 
0474 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
0475 {
0476     switch (reg) {
0477     case MAX310X_IRQSTS_REG:
0478     case MAX310X_LSR_IRQSTS_REG:
0479     case MAX310X_SPCHR_IRQSTS_REG:
0480     case MAX310X_STS_IRQSTS_REG:
0481     case MAX310X_TXFIFOLVL_REG:
0482     case MAX310X_RXFIFOLVL_REG:
0483         return false;
0484     default:
0485         break;
0486     }
0487 
0488     return true;
0489 }
0490 
0491 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
0492 {
0493     switch (reg) {
0494     case MAX310X_RHR_REG:
0495     case MAX310X_IRQSTS_REG:
0496     case MAX310X_LSR_IRQSTS_REG:
0497     case MAX310X_SPCHR_IRQSTS_REG:
0498     case MAX310X_STS_IRQSTS_REG:
0499     case MAX310X_TXFIFOLVL_REG:
0500     case MAX310X_RXFIFOLVL_REG:
0501     case MAX310X_GPIODATA_REG:
0502     case MAX310X_BRGDIVLSB_REG:
0503     case MAX310X_REG_05:
0504     case MAX310X_REG_1F:
0505         return true;
0506     default:
0507         break;
0508     }
0509 
0510     return false;
0511 }
0512 
0513 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
0514 {
0515     switch (reg) {
0516     case MAX310X_RHR_REG:
0517     case MAX310X_IRQSTS_REG:
0518     case MAX310X_SPCHR_IRQSTS_REG:
0519     case MAX310X_STS_IRQSTS_REG:
0520         return true;
0521     default:
0522         break;
0523     }
0524 
0525     return false;
0526 }
0527 
0528 static int max310x_set_baud(struct uart_port *port, int baud)
0529 {
0530     unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
0531 
0532     /*
0533      * Calculate the integer divisor first. Select a proper mode
0534      * in case if the requested baud is too high for the pre-defined
0535      * clocks frequency.
0536      */
0537     div = port->uartclk / baud;
0538     if (div < 8) {
0539         /* Mode x4 */
0540         c = 4;
0541         mode = MAX310X_BRGCFG_4XMODE_BIT;
0542     } else if (div < 16) {
0543         /* Mode x2 */
0544         c = 8;
0545         mode = MAX310X_BRGCFG_2XMODE_BIT;
0546     } else {
0547         c = 16;
0548     }
0549 
0550     /* Calculate the divisor in accordance with the fraction coefficient */
0551     div /= c;
0552     F = c*baud;
0553 
0554     /* Calculate the baud rate fraction */
0555     if (div > 0)
0556         frac = (16*(port->uartclk % F)) / F;
0557     else
0558         div = 1;
0559 
0560     max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
0561     max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
0562     max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
0563 
0564     /* Return the actual baud rate we just programmed */
0565     return (16*port->uartclk) / (c*(16*div + frac));
0566 }
0567 
0568 static int max310x_update_best_err(unsigned long f, long *besterr)
0569 {
0570     /* Use baudrate 115200 for calculate error */
0571     long err = f % (460800 * 16);
0572 
0573     if ((*besterr < 0) || (*besterr > err)) {
0574         *besterr = err;
0575         return 0;
0576     }
0577 
0578     return 1;
0579 }
0580 
0581 static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
0582                    unsigned long freq, bool xtal)
0583 {
0584     unsigned int div, clksrc, pllcfg = 0;
0585     long besterr = -1;
0586     unsigned long fdiv, fmul, bestfreq = freq;
0587 
0588     /* First, update error without PLL */
0589     max310x_update_best_err(freq, &besterr);
0590 
0591     /* Try all possible PLL dividers */
0592     for (div = 1; (div <= 63) && besterr; div++) {
0593         fdiv = DIV_ROUND_CLOSEST(freq, div);
0594 
0595         /* Try multiplier 6 */
0596         fmul = fdiv * 6;
0597         if ((fdiv >= 500000) && (fdiv <= 800000))
0598             if (!max310x_update_best_err(fmul, &besterr)) {
0599                 pllcfg = (0 << 6) | div;
0600                 bestfreq = fmul;
0601             }
0602         /* Try multiplier 48 */
0603         fmul = fdiv * 48;
0604         if ((fdiv >= 850000) && (fdiv <= 1200000))
0605             if (!max310x_update_best_err(fmul, &besterr)) {
0606                 pllcfg = (1 << 6) | div;
0607                 bestfreq = fmul;
0608             }
0609         /* Try multiplier 96 */
0610         fmul = fdiv * 96;
0611         if ((fdiv >= 425000) && (fdiv <= 1000000))
0612             if (!max310x_update_best_err(fmul, &besterr)) {
0613                 pllcfg = (2 << 6) | div;
0614                 bestfreq = fmul;
0615             }
0616         /* Try multiplier 144 */
0617         fmul = fdiv * 144;
0618         if ((fdiv >= 390000) && (fdiv <= 667000))
0619             if (!max310x_update_best_err(fmul, &besterr)) {
0620                 pllcfg = (3 << 6) | div;
0621                 bestfreq = fmul;
0622             }
0623     }
0624 
0625     /* Configure clock source */
0626     clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
0627 
0628     /* Configure PLL */
0629     if (pllcfg) {
0630         clksrc |= MAX310X_CLKSRC_PLL_BIT;
0631         regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
0632     } else
0633         clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
0634 
0635     regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
0636 
0637     /* Wait for crystal */
0638     if (xtal) {
0639         unsigned int val;
0640         msleep(10);
0641         regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
0642         if (!(val & MAX310X_STS_CLKREADY_BIT)) {
0643             dev_warn(dev, "clock is not stable yet\n");
0644         }
0645     }
0646 
0647     return bestfreq;
0648 }
0649 
0650 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
0651 {
0652     struct max310x_one *one = to_max310x_port(port);
0653 
0654     regmap_raw_write(one->regmap, MAX310X_THR_REG, txbuf, len);
0655 }
0656 
0657 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
0658 {
0659     struct max310x_one *one = to_max310x_port(port);
0660 
0661     regmap_raw_read(one->regmap, MAX310X_RHR_REG, rxbuf, len);
0662 }
0663 
0664 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
0665 {
0666     struct max310x_one *one = to_max310x_port(port);
0667     unsigned int sts, ch, flag, i;
0668 
0669     if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
0670         /* We are just reading, happily ignoring any error conditions.
0671          * Break condition, parity checking, framing errors -- they
0672          * are all ignored. That means that we can do a batch-read.
0673          *
0674          * There is a small opportunity for race if the RX FIFO
0675          * overruns while we're reading the buffer; the datasheets says
0676          * that the LSR register applies to the "current" character.
0677          * That's also the reason why we cannot do batched reads when
0678          * asked to check the individual statuses.
0679          * */
0680 
0681         sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
0682         max310x_batch_read(port, one->rx_buf, rxlen);
0683 
0684         port->icount.rx += rxlen;
0685         flag = TTY_NORMAL;
0686         sts &= port->read_status_mask;
0687 
0688         if (sts & MAX310X_LSR_RXOVR_BIT) {
0689             dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
0690             port->icount.overrun++;
0691         }
0692 
0693         for (i = 0; i < (rxlen - 1); ++i)
0694             uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
0695 
0696         /*
0697          * Handle the overrun case for the last character only, since
0698          * the RxFIFO overflow happens after it is pushed to the FIFO
0699          * tail.
0700          */
0701         uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
0702                  one->rx_buf[rxlen-1], flag);
0703 
0704     } else {
0705         if (unlikely(rxlen >= port->fifosize)) {
0706             dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
0707             port->icount.buf_overrun++;
0708             /* Ensure sanity of RX level */
0709             rxlen = port->fifosize;
0710         }
0711 
0712         while (rxlen--) {
0713             ch = max310x_port_read(port, MAX310X_RHR_REG);
0714             sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
0715 
0716             sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
0717                    MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
0718 
0719             port->icount.rx++;
0720             flag = TTY_NORMAL;
0721 
0722             if (unlikely(sts)) {
0723                 if (sts & MAX310X_LSR_RXBRK_BIT) {
0724                     port->icount.brk++;
0725                     if (uart_handle_break(port))
0726                         continue;
0727                 } else if (sts & MAX310X_LSR_RXPAR_BIT)
0728                     port->icount.parity++;
0729                 else if (sts & MAX310X_LSR_FRERR_BIT)
0730                     port->icount.frame++;
0731                 else if (sts & MAX310X_LSR_RXOVR_BIT)
0732                     port->icount.overrun++;
0733 
0734                 sts &= port->read_status_mask;
0735                 if (sts & MAX310X_LSR_RXBRK_BIT)
0736                     flag = TTY_BREAK;
0737                 else if (sts & MAX310X_LSR_RXPAR_BIT)
0738                     flag = TTY_PARITY;
0739                 else if (sts & MAX310X_LSR_FRERR_BIT)
0740                     flag = TTY_FRAME;
0741                 else if (sts & MAX310X_LSR_RXOVR_BIT)
0742                     flag = TTY_OVERRUN;
0743             }
0744 
0745             if (uart_handle_sysrq_char(port, ch))
0746                 continue;
0747 
0748             if (sts & port->ignore_status_mask)
0749                 continue;
0750 
0751             uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
0752         }
0753     }
0754 
0755     tty_flip_buffer_push(&port->state->port);
0756 }
0757 
0758 static void max310x_handle_tx(struct uart_port *port)
0759 {
0760     struct circ_buf *xmit = &port->state->xmit;
0761     unsigned int txlen, to_send, until_end;
0762 
0763     if (unlikely(port->x_char)) {
0764         max310x_port_write(port, MAX310X_THR_REG, port->x_char);
0765         port->icount.tx++;
0766         port->x_char = 0;
0767         return;
0768     }
0769 
0770     if (uart_circ_empty(xmit) || uart_tx_stopped(port))
0771         return;
0772 
0773     /* Get length of data pending in circular buffer */
0774     to_send = uart_circ_chars_pending(xmit);
0775     until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
0776     if (likely(to_send)) {
0777         /* Limit to size of TX FIFO */
0778         txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
0779         txlen = port->fifosize - txlen;
0780         to_send = (to_send > txlen) ? txlen : to_send;
0781 
0782         if (until_end < to_send) {
0783             /* It's a circ buffer -- wrap around.
0784              * We could do that in one SPI transaction, but meh. */
0785             max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
0786             max310x_batch_write(port, xmit->buf, to_send - until_end);
0787         } else {
0788             max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
0789         }
0790 
0791         /* Add data to send */
0792         port->icount.tx += to_send;
0793         xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
0794     }
0795 
0796     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0797         uart_write_wakeup(port);
0798 }
0799 
0800 static void max310x_start_tx(struct uart_port *port)
0801 {
0802     struct max310x_one *one = to_max310x_port(port);
0803 
0804     schedule_work(&one->tx_work);
0805 }
0806 
0807 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
0808 {
0809     struct uart_port *port = &s->p[portno].port;
0810     irqreturn_t res = IRQ_NONE;
0811 
0812     do {
0813         unsigned int ists, lsr, rxlen;
0814 
0815         /* Read IRQ status & RX FIFO level */
0816         ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
0817         rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
0818         if (!ists && !rxlen)
0819             break;
0820 
0821         res = IRQ_HANDLED;
0822 
0823         if (ists & MAX310X_IRQ_CTS_BIT) {
0824             lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
0825             uart_handle_cts_change(port,
0826                            !!(lsr & MAX310X_LSR_CTS_BIT));
0827         }
0828         if (rxlen)
0829             max310x_handle_rx(port, rxlen);
0830         if (ists & MAX310X_IRQ_TXEMPTY_BIT)
0831             max310x_start_tx(port);
0832     } while (1);
0833     return res;
0834 }
0835 
0836 static irqreturn_t max310x_ist(int irq, void *dev_id)
0837 {
0838     struct max310x_port *s = (struct max310x_port *)dev_id;
0839     bool handled = false;
0840 
0841     if (s->devtype->nr > 1) {
0842         do {
0843             unsigned int val = ~0;
0844 
0845             WARN_ON_ONCE(regmap_read(s->regmap,
0846                          MAX310X_GLOBALIRQ_REG, &val));
0847             val = ((1 << s->devtype->nr) - 1) & ~val;
0848             if (!val)
0849                 break;
0850             if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
0851                 handled = true;
0852         } while (1);
0853     } else {
0854         if (max310x_port_irq(s, 0) == IRQ_HANDLED)
0855             handled = true;
0856     }
0857 
0858     return IRQ_RETVAL(handled);
0859 }
0860 
0861 static void max310x_tx_proc(struct work_struct *ws)
0862 {
0863     struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
0864 
0865     max310x_handle_tx(&one->port);
0866 }
0867 
0868 static unsigned int max310x_tx_empty(struct uart_port *port)
0869 {
0870     u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
0871 
0872     return lvl ? 0 : TIOCSER_TEMT;
0873 }
0874 
0875 static unsigned int max310x_get_mctrl(struct uart_port *port)
0876 {
0877     /* DCD and DSR are not wired and CTS/RTS is handled automatically
0878      * so just indicate DSR and CAR asserted
0879      */
0880     return TIOCM_DSR | TIOCM_CAR;
0881 }
0882 
0883 static void max310x_md_proc(struct work_struct *ws)
0884 {
0885     struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
0886 
0887     max310x_port_update(&one->port, MAX310X_MODE2_REG,
0888                 MAX310X_MODE2_LOOPBACK_BIT,
0889                 (one->port.mctrl & TIOCM_LOOP) ?
0890                 MAX310X_MODE2_LOOPBACK_BIT : 0);
0891 }
0892 
0893 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
0894 {
0895     struct max310x_one *one = to_max310x_port(port);
0896 
0897     schedule_work(&one->md_work);
0898 }
0899 
0900 static void max310x_break_ctl(struct uart_port *port, int break_state)
0901 {
0902     max310x_port_update(port, MAX310X_LCR_REG,
0903                 MAX310X_LCR_TXBREAK_BIT,
0904                 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
0905 }
0906 
0907 static void max310x_set_termios(struct uart_port *port,
0908                 struct ktermios *termios,
0909                 struct ktermios *old)
0910 {
0911     unsigned int lcr = 0, flow = 0;
0912     int baud;
0913 
0914     /* Mask termios capabilities we don't support */
0915     termios->c_cflag &= ~CMSPAR;
0916 
0917     /* Word size */
0918     switch (termios->c_cflag & CSIZE) {
0919     case CS5:
0920         break;
0921     case CS6:
0922         lcr = MAX310X_LCR_LENGTH0_BIT;
0923         break;
0924     case CS7:
0925         lcr = MAX310X_LCR_LENGTH1_BIT;
0926         break;
0927     case CS8:
0928     default:
0929         lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
0930         break;
0931     }
0932 
0933     /* Parity */
0934     if (termios->c_cflag & PARENB) {
0935         lcr |= MAX310X_LCR_PARITY_BIT;
0936         if (!(termios->c_cflag & PARODD))
0937             lcr |= MAX310X_LCR_EVENPARITY_BIT;
0938     }
0939 
0940     /* Stop bits */
0941     if (termios->c_cflag & CSTOPB)
0942         lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
0943 
0944     /* Update LCR register */
0945     max310x_port_write(port, MAX310X_LCR_REG, lcr);
0946 
0947     /* Set read status mask */
0948     port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
0949     if (termios->c_iflag & INPCK)
0950         port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
0951                       MAX310X_LSR_FRERR_BIT;
0952     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0953         port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
0954 
0955     /* Set status ignore mask */
0956     port->ignore_status_mask = 0;
0957     if (termios->c_iflag & IGNBRK)
0958         port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
0959     if (!(termios->c_cflag & CREAD))
0960         port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
0961                         MAX310X_LSR_RXOVR_BIT |
0962                         MAX310X_LSR_FRERR_BIT |
0963                         MAX310X_LSR_RXBRK_BIT;
0964 
0965     /* Configure flow control */
0966     max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
0967     max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
0968 
0969     /* Disable transmitter before enabling AutoCTS or auto transmitter
0970      * flow control
0971      */
0972     if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
0973         max310x_port_update(port, MAX310X_MODE1_REG,
0974                     MAX310X_MODE1_TXDIS_BIT,
0975                     MAX310X_MODE1_TXDIS_BIT);
0976     }
0977 
0978     port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
0979 
0980     if (termios->c_cflag & CRTSCTS) {
0981         /* Enable AUTORTS and AUTOCTS */
0982         port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
0983         flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
0984             MAX310X_FLOWCTRL_AUTORTS_BIT;
0985     }
0986     if (termios->c_iflag & IXON)
0987         flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
0988             MAX310X_FLOWCTRL_SWFLOWEN_BIT;
0989     if (termios->c_iflag & IXOFF) {
0990         port->status |= UPSTAT_AUTOXOFF;
0991         flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
0992             MAX310X_FLOWCTRL_SWFLOWEN_BIT;
0993     }
0994     max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
0995 
0996     /* Enable transmitter after disabling AutoCTS and auto transmitter
0997      * flow control
0998      */
0999     if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
1000         max310x_port_update(port, MAX310X_MODE1_REG,
1001                     MAX310X_MODE1_TXDIS_BIT,
1002                     0);
1003     }
1004 
1005     /* Get baud rate generator configuration */
1006     baud = uart_get_baud_rate(port, termios, old,
1007                   port->uartclk / 16 / 0xffff,
1008                   port->uartclk / 4);
1009 
1010     /* Setup baudrate generator */
1011     baud = max310x_set_baud(port, baud);
1012 
1013     /* Update timeout according to new baud rate */
1014     uart_update_timeout(port, termios->c_cflag, baud);
1015 }
1016 
1017 static void max310x_rs_proc(struct work_struct *ws)
1018 {
1019     struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1020     unsigned int delay, mode1 = 0, mode2 = 0;
1021 
1022     delay = (one->port.rs485.delay_rts_before_send << 4) |
1023         one->port.rs485.delay_rts_after_send;
1024     max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1025 
1026     if (one->port.rs485.flags & SER_RS485_ENABLED) {
1027         mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1028 
1029         if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1030             mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1031     }
1032 
1033     max310x_port_update(&one->port, MAX310X_MODE1_REG,
1034             MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1035     max310x_port_update(&one->port, MAX310X_MODE2_REG,
1036             MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1037 }
1038 
1039 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios,
1040                 struct serial_rs485 *rs485)
1041 {
1042     struct max310x_one *one = to_max310x_port(port);
1043 
1044     if ((rs485->delay_rts_before_send > 0x0f) ||
1045         (rs485->delay_rts_after_send > 0x0f))
1046         return -ERANGE;
1047 
1048     port->rs485 = *rs485;
1049 
1050     schedule_work(&one->rs_work);
1051 
1052     return 0;
1053 }
1054 
1055 static int max310x_startup(struct uart_port *port)
1056 {
1057     struct max310x_port *s = dev_get_drvdata(port->dev);
1058     unsigned int val;
1059 
1060     s->devtype->power(port, 1);
1061 
1062     /* Configure MODE1 register */
1063     max310x_port_update(port, MAX310X_MODE1_REG,
1064                 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1065 
1066     /* Configure MODE2 register & Reset FIFOs*/
1067     val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1068     max310x_port_write(port, MAX310X_MODE2_REG, val);
1069     max310x_port_update(port, MAX310X_MODE2_REG,
1070                 MAX310X_MODE2_FIFORST_BIT, 0);
1071 
1072     /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1073     val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1074         clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1075     max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1076 
1077     if (port->rs485.flags & SER_RS485_ENABLED) {
1078         max310x_port_update(port, MAX310X_MODE1_REG,
1079                     MAX310X_MODE1_TRNSCVCTRL_BIT,
1080                     MAX310X_MODE1_TRNSCVCTRL_BIT);
1081 
1082         if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1083             max310x_port_update(port, MAX310X_MODE2_REG,
1084                         MAX310X_MODE2_ECHOSUPR_BIT,
1085                         MAX310X_MODE2_ECHOSUPR_BIT);
1086     }
1087 
1088     /* Configure flow control levels */
1089     /* Flow control halt level 96, resume level 48 */
1090     max310x_port_write(port, MAX310X_FLOWLVL_REG,
1091                MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1092 
1093     /* Clear IRQ status register */
1094     max310x_port_read(port, MAX310X_IRQSTS_REG);
1095 
1096     /* Enable RX, TX, CTS change interrupts */
1097     val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1098     max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1099 
1100     return 0;
1101 }
1102 
1103 static void max310x_shutdown(struct uart_port *port)
1104 {
1105     struct max310x_port *s = dev_get_drvdata(port->dev);
1106 
1107     /* Disable all interrupts */
1108     max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1109 
1110     s->devtype->power(port, 0);
1111 }
1112 
1113 static const char *max310x_type(struct uart_port *port)
1114 {
1115     struct max310x_port *s = dev_get_drvdata(port->dev);
1116 
1117     return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1118 }
1119 
1120 static int max310x_request_port(struct uart_port *port)
1121 {
1122     /* Do nothing */
1123     return 0;
1124 }
1125 
1126 static void max310x_config_port(struct uart_port *port, int flags)
1127 {
1128     if (flags & UART_CONFIG_TYPE)
1129         port->type = PORT_MAX310X;
1130 }
1131 
1132 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1133 {
1134     if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1135         return -EINVAL;
1136     if (s->irq != port->irq)
1137         return -EINVAL;
1138 
1139     return 0;
1140 }
1141 
1142 static void max310x_null_void(struct uart_port *port)
1143 {
1144     /* Do nothing */
1145 }
1146 
1147 static const struct uart_ops max310x_ops = {
1148     .tx_empty   = max310x_tx_empty,
1149     .set_mctrl  = max310x_set_mctrl,
1150     .get_mctrl  = max310x_get_mctrl,
1151     .stop_tx    = max310x_null_void,
1152     .start_tx   = max310x_start_tx,
1153     .stop_rx    = max310x_null_void,
1154     .break_ctl  = max310x_break_ctl,
1155     .startup    = max310x_startup,
1156     .shutdown   = max310x_shutdown,
1157     .set_termios    = max310x_set_termios,
1158     .type       = max310x_type,
1159     .request_port   = max310x_request_port,
1160     .release_port   = max310x_null_void,
1161     .config_port    = max310x_config_port,
1162     .verify_port    = max310x_verify_port,
1163 };
1164 
1165 static int __maybe_unused max310x_suspend(struct device *dev)
1166 {
1167     struct max310x_port *s = dev_get_drvdata(dev);
1168     int i;
1169 
1170     for (i = 0; i < s->devtype->nr; i++) {
1171         uart_suspend_port(&max310x_uart, &s->p[i].port);
1172         s->devtype->power(&s->p[i].port, 0);
1173     }
1174 
1175     return 0;
1176 }
1177 
1178 static int __maybe_unused max310x_resume(struct device *dev)
1179 {
1180     struct max310x_port *s = dev_get_drvdata(dev);
1181     int i;
1182 
1183     for (i = 0; i < s->devtype->nr; i++) {
1184         s->devtype->power(&s->p[i].port, 1);
1185         uart_resume_port(&max310x_uart, &s->p[i].port);
1186     }
1187 
1188     return 0;
1189 }
1190 
1191 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1192 
1193 #ifdef CONFIG_GPIOLIB
1194 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1195 {
1196     unsigned int val;
1197     struct max310x_port *s = gpiochip_get_data(chip);
1198     struct uart_port *port = &s->p[offset / 4].port;
1199 
1200     val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1201 
1202     return !!((val >> 4) & (1 << (offset % 4)));
1203 }
1204 
1205 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1206 {
1207     struct max310x_port *s = gpiochip_get_data(chip);
1208     struct uart_port *port = &s->p[offset / 4].port;
1209 
1210     max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1211                 value ? 1 << (offset % 4) : 0);
1212 }
1213 
1214 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1215 {
1216     struct max310x_port *s = gpiochip_get_data(chip);
1217     struct uart_port *port = &s->p[offset / 4].port;
1218 
1219     max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1220 
1221     return 0;
1222 }
1223 
1224 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1225                      unsigned offset, int value)
1226 {
1227     struct max310x_port *s = gpiochip_get_data(chip);
1228     struct uart_port *port = &s->p[offset / 4].port;
1229 
1230     max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1231                 value ? 1 << (offset % 4) : 0);
1232     max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1233                 1 << (offset % 4));
1234 
1235     return 0;
1236 }
1237 
1238 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1239                    unsigned long config)
1240 {
1241     struct max310x_port *s = gpiochip_get_data(chip);
1242     struct uart_port *port = &s->p[offset / 4].port;
1243 
1244     switch (pinconf_to_config_param(config)) {
1245     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1246         max310x_port_update(port, MAX310X_GPIOCFG_REG,
1247                 1 << ((offset % 4) + 4),
1248                 1 << ((offset % 4) + 4));
1249         return 0;
1250     case PIN_CONFIG_DRIVE_PUSH_PULL:
1251         max310x_port_update(port, MAX310X_GPIOCFG_REG,
1252                 1 << ((offset % 4) + 4), 0);
1253         return 0;
1254     default:
1255         return -ENOTSUPP;
1256     }
1257 }
1258 #endif
1259 
1260 static const struct serial_rs485 max310x_rs485_supported = {
1261     .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX,
1262     .delay_rts_before_send = 1,
1263     .delay_rts_after_send = 1,
1264 };
1265 
1266 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype,
1267              const struct max310x_if_cfg *if_cfg,
1268              struct regmap *regmaps[], int irq)
1269 {
1270     int i, ret, fmin, fmax, freq;
1271     struct max310x_port *s;
1272     u32 uartclk = 0;
1273     bool xtal;
1274 
1275     for (i = 0; i < devtype->nr; i++)
1276         if (IS_ERR(regmaps[i]))
1277             return PTR_ERR(regmaps[i]);
1278 
1279     /* Alloc port structure */
1280     s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1281     if (!s) {
1282         dev_err(dev, "Error allocating port structure\n");
1283         return -ENOMEM;
1284     }
1285 
1286     /* Always ask for fixed clock rate from a property. */
1287     device_property_read_u32(dev, "clock-frequency", &uartclk);
1288 
1289     xtal = device_property_match_string(dev, "clock-names", "osc") < 0;
1290     if (xtal)
1291         s->clk = devm_clk_get_optional(dev, "xtal");
1292     else
1293         s->clk = devm_clk_get_optional(dev, "osc");
1294     if (IS_ERR(s->clk))
1295         return PTR_ERR(s->clk);
1296 
1297     ret = clk_prepare_enable(s->clk);
1298     if (ret)
1299         return ret;
1300 
1301     freq = clk_get_rate(s->clk);
1302     if (freq == 0)
1303         freq = uartclk;
1304     if (freq == 0) {
1305         dev_err(dev, "Cannot get clock rate\n");
1306         ret = -EINVAL;
1307         goto out_clk;
1308     }
1309 
1310     if (xtal) {
1311         fmin = 1000000;
1312         fmax = 4000000;
1313     } else {
1314         fmin = 500000;
1315         fmax = 35000000;
1316     }
1317 
1318     /* Check frequency limits */
1319     if (freq < fmin || freq > fmax) {
1320         ret = -ERANGE;
1321         goto out_clk;
1322     }
1323 
1324     s->regmap = regmaps[0];
1325     s->devtype = devtype;
1326     s->if_cfg = if_cfg;
1327     dev_set_drvdata(dev, s);
1328 
1329     /* Check device to ensure we are talking to what we expect */
1330     ret = devtype->detect(dev);
1331     if (ret)
1332         goto out_clk;
1333 
1334     for (i = 0; i < devtype->nr; i++) {
1335         /* Reset port */
1336         regmap_write(regmaps[i], MAX310X_MODE2_REG,
1337                  MAX310X_MODE2_RST_BIT);
1338         /* Clear port reset */
1339         regmap_write(regmaps[i], MAX310X_MODE2_REG, 0);
1340 
1341         /* Wait for port startup */
1342         do {
1343             regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret);
1344         } while (ret != 0x01);
1345 
1346         regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1);
1347     }
1348 
1349     uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1350     dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1351 
1352     for (i = 0; i < devtype->nr; i++) {
1353         unsigned int line;
1354 
1355         line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1356         if (line == MAX310X_UART_NRMAX) {
1357             ret = -ERANGE;
1358             goto out_uart;
1359         }
1360 
1361         /* Initialize port data */
1362         s->p[i].port.line   = line;
1363         s->p[i].port.dev    = dev;
1364         s->p[i].port.irq    = irq;
1365         s->p[i].port.type   = PORT_MAX310X;
1366         s->p[i].port.fifosize   = MAX310X_FIFO_SIZE;
1367         s->p[i].port.flags  = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1368         s->p[i].port.iotype = UPIO_PORT;
1369         s->p[i].port.iobase = i;
1370         s->p[i].port.membase    = (void __iomem *)~0;
1371         s->p[i].port.uartclk    = uartclk;
1372         s->p[i].port.rs485_config = max310x_rs485_config;
1373         s->p[i].port.rs485_supported = max310x_rs485_supported;
1374         s->p[i].port.ops    = &max310x_ops;
1375         s->p[i].regmap      = regmaps[i];
1376 
1377         /* Disable all interrupts */
1378         max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1379         /* Clear IRQ status register */
1380         max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1381         /* Initialize queue for start TX */
1382         INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1383         /* Initialize queue for changing LOOPBACK mode */
1384         INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1385         /* Initialize queue for changing RS485 mode */
1386         INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1387 
1388         /* Register port */
1389         ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1390         if (ret) {
1391             s->p[i].port.dev = NULL;
1392             goto out_uart;
1393         }
1394         set_bit(line, max310x_lines);
1395 
1396         /* Go to suspend mode */
1397         devtype->power(&s->p[i].port, 0);
1398     }
1399 
1400 #ifdef CONFIG_GPIOLIB
1401     /* Setup GPIO cotroller */
1402     s->gpio.owner       = THIS_MODULE;
1403     s->gpio.parent      = dev;
1404     s->gpio.label       = devtype->name;
1405     s->gpio.direction_input = max310x_gpio_direction_input;
1406     s->gpio.get     = max310x_gpio_get;
1407     s->gpio.direction_output= max310x_gpio_direction_output;
1408     s->gpio.set     = max310x_gpio_set;
1409     s->gpio.set_config  = max310x_gpio_set_config;
1410     s->gpio.base        = -1;
1411     s->gpio.ngpio       = devtype->nr * 4;
1412     s->gpio.can_sleep   = 1;
1413     ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1414     if (ret)
1415         goto out_uart;
1416 #endif
1417 
1418     /* Setup interrupt */
1419     ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1420                     IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1421     if (!ret)
1422         return 0;
1423 
1424     dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1425 
1426 out_uart:
1427     for (i = 0; i < devtype->nr; i++) {
1428         if (s->p[i].port.dev) {
1429             uart_remove_one_port(&max310x_uart, &s->p[i].port);
1430             clear_bit(s->p[i].port.line, max310x_lines);
1431         }
1432     }
1433 
1434 out_clk:
1435     clk_disable_unprepare(s->clk);
1436 
1437     return ret;
1438 }
1439 
1440 static void max310x_remove(struct device *dev)
1441 {
1442     struct max310x_port *s = dev_get_drvdata(dev);
1443     int i;
1444 
1445     for (i = 0; i < s->devtype->nr; i++) {
1446         cancel_work_sync(&s->p[i].tx_work);
1447         cancel_work_sync(&s->p[i].md_work);
1448         cancel_work_sync(&s->p[i].rs_work);
1449         uart_remove_one_port(&max310x_uart, &s->p[i].port);
1450         clear_bit(s->p[i].port.line, max310x_lines);
1451         s->devtype->power(&s->p[i].port, 0);
1452     }
1453 
1454     clk_disable_unprepare(s->clk);
1455 }
1456 
1457 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1458     { .compatible = "maxim,max3107",    .data = &max3107_devtype, },
1459     { .compatible = "maxim,max3108",    .data = &max3108_devtype, },
1460     { .compatible = "maxim,max3109",    .data = &max3109_devtype, },
1461     { .compatible = "maxim,max14830",   .data = &max14830_devtype },
1462     { }
1463 };
1464 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1465 
1466 static struct regmap_config regcfg = {
1467     .reg_bits = 8,
1468     .val_bits = 8,
1469     .write_flag_mask = MAX310X_WRITE_BIT,
1470     .cache_type = REGCACHE_RBTREE,
1471     .max_register = MAX310X_REG_1F,
1472     .writeable_reg = max310x_reg_writeable,
1473     .volatile_reg = max310x_reg_volatile,
1474     .precious_reg = max310x_reg_precious,
1475 };
1476 
1477 #ifdef CONFIG_SPI_MASTER
1478 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable)
1479 {
1480     struct max310x_port *s = dev_get_drvdata(dev);
1481 
1482     return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
1483                 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL);
1484 }
1485 
1486 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = {
1487     .extended_reg_enable = max310x_spi_extended_reg_enable,
1488     .rev_id_reg = MAX310X_SPI_REVID_EXTREG,
1489 };
1490 
1491 static int max310x_spi_probe(struct spi_device *spi)
1492 {
1493     const struct max310x_devtype *devtype;
1494     struct regmap *regmaps[4];
1495     unsigned int i;
1496     int ret;
1497 
1498     /* Setup SPI bus */
1499     spi->bits_per_word  = 8;
1500     spi->mode       = spi->mode ? : SPI_MODE_0;
1501     spi->max_speed_hz   = spi->max_speed_hz ? : 26000000;
1502     ret = spi_setup(spi);
1503     if (ret)
1504         return ret;
1505 
1506     devtype = device_get_match_data(&spi->dev);
1507     if (!devtype)
1508         devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data;
1509 
1510     for (i = 0; i < devtype->nr; i++) {
1511         u8 port_mask = i * 0x20;
1512         regcfg.read_flag_mask = port_mask;
1513         regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT;
1514         regmaps[i] = devm_regmap_init_spi(spi, &regcfg);
1515     }
1516 
1517     return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq);
1518 }
1519 
1520 static void max310x_spi_remove(struct spi_device *spi)
1521 {
1522     max310x_remove(&spi->dev);
1523 }
1524 
1525 static const struct spi_device_id max310x_id_table[] = {
1526     { "max3107",    (kernel_ulong_t)&max3107_devtype, },
1527     { "max3108",    (kernel_ulong_t)&max3108_devtype, },
1528     { "max3109",    (kernel_ulong_t)&max3109_devtype, },
1529     { "max14830",   (kernel_ulong_t)&max14830_devtype, },
1530     { }
1531 };
1532 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1533 
1534 static struct spi_driver max310x_spi_driver = {
1535     .driver = {
1536         .name       = MAX310X_NAME,
1537         .of_match_table = max310x_dt_ids,
1538         .pm     = &max310x_pm_ops,
1539     },
1540     .probe      = max310x_spi_probe,
1541     .remove     = max310x_spi_remove,
1542     .id_table   = max310x_id_table,
1543 };
1544 #endif
1545 
1546 #ifdef CONFIG_I2C
1547 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable)
1548 {
1549     return 0;
1550 }
1551 
1552 static struct regmap_config regcfg_i2c = {
1553     .reg_bits = 8,
1554     .val_bits = 8,
1555     .cache_type = REGCACHE_RBTREE,
1556     .writeable_reg = max310x_reg_writeable,
1557     .volatile_reg = max310x_reg_volatile,
1558     .precious_reg = max310x_reg_precious,
1559     .max_register = MAX310X_I2C_REVID_EXTREG,
1560 };
1561 
1562 static const struct max310x_if_cfg max310x_i2c_if_cfg = {
1563     .extended_reg_enable = max310x_i2c_extended_reg_enable,
1564     .rev_id_reg = MAX310X_I2C_REVID_EXTREG,
1565 };
1566 
1567 static unsigned short max310x_i2c_slave_addr(unsigned short addr,
1568                          unsigned int nr)
1569 {
1570     /*
1571      * For MAX14830 and MAX3109, the slave address depends on what the
1572      * A0 and A1 pins are tied to.
1573      * See Table I2C Address Map of the datasheet.
1574      * Based on that table, the following formulas were determined.
1575      * UART1 - UART0 = 0x10
1576      * UART2 - UART1 = 0x20 + 0x10
1577      * UART3 - UART2 = 0x10
1578      */
1579 
1580     addr -= nr * 0x10;
1581 
1582     if (nr >= 2)
1583         addr -= 0x20;
1584 
1585     return addr;
1586 }
1587 
1588 static int max310x_i2c_probe(struct i2c_client *client)
1589 {
1590     const struct max310x_devtype *devtype =
1591             device_get_match_data(&client->dev);
1592     struct i2c_client *port_client;
1593     struct regmap *regmaps[4];
1594     unsigned int i;
1595     u8 port_addr;
1596 
1597     if (client->addr < devtype->slave_addr.min ||
1598         client->addr > devtype->slave_addr.max)
1599         return dev_err_probe(&client->dev, -EINVAL,
1600                      "Slave addr 0x%x outside of range [0x%x, 0x%x]\n",
1601                      client->addr, devtype->slave_addr.min,
1602                      devtype->slave_addr.max);
1603 
1604     regmaps[0] = devm_regmap_init_i2c(client, &regcfg_i2c);
1605 
1606     for (i = 1; i < devtype->nr; i++) {
1607         port_addr = max310x_i2c_slave_addr(client->addr, i);
1608         port_client = devm_i2c_new_dummy_device(&client->dev,
1609                             client->adapter,
1610                             port_addr);
1611 
1612         regmaps[i] = devm_regmap_init_i2c(port_client, &regcfg_i2c);
1613     }
1614 
1615     return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg,
1616                  regmaps, client->irq);
1617 }
1618 
1619 static int max310x_i2c_remove(struct i2c_client *client)
1620 {
1621     max310x_remove(&client->dev);
1622 
1623     return 0;
1624 }
1625 
1626 static struct i2c_driver max310x_i2c_driver = {
1627     .driver = {
1628         .name       = MAX310X_NAME,
1629         .of_match_table = max310x_dt_ids,
1630         .pm     = &max310x_pm_ops,
1631     },
1632     .probe_new  = max310x_i2c_probe,
1633     .remove     = max310x_i2c_remove,
1634 };
1635 #endif
1636 
1637 static int __init max310x_uart_init(void)
1638 {
1639     int ret;
1640 
1641     bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1642 
1643     ret = uart_register_driver(&max310x_uart);
1644     if (ret)
1645         return ret;
1646 
1647 #ifdef CONFIG_SPI_MASTER
1648     ret = spi_register_driver(&max310x_spi_driver);
1649     if (ret)
1650         goto err_spi_register;
1651 #endif
1652 
1653 #ifdef CONFIG_I2C
1654     ret = i2c_add_driver(&max310x_i2c_driver);
1655     if (ret)
1656         goto err_i2c_register;
1657 #endif
1658 
1659     return 0;
1660 
1661 #ifdef CONFIG_I2C
1662 err_i2c_register:
1663     spi_unregister_driver(&max310x_spi_driver);
1664 #endif
1665 
1666 err_spi_register:
1667     uart_unregister_driver(&max310x_uart);
1668 
1669     return ret;
1670 }
1671 module_init(max310x_uart_init);
1672 
1673 static void __exit max310x_uart_exit(void)
1674 {
1675 #ifdef CONFIG_I2C
1676     i2c_del_driver(&max310x_i2c_driver);
1677 #endif
1678 
1679 #ifdef CONFIG_SPI_MASTER
1680     spi_unregister_driver(&max310x_spi_driver);
1681 #endif
1682 
1683     uart_unregister_driver(&max310x_uart);
1684 }
1685 module_exit(max310x_uart_exit);
1686 
1687 MODULE_LICENSE("GPL");
1688 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1689 MODULE_DESCRIPTION("MAX310X serial driver");
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