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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
0004  *
0005  * Copyright (C) 2004 Infineon IFAP DC COM CPE
0006  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
0007  * Copyright (C) 2007 John Crispin <john@phrozen.org>
0008  * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/console.h>
0013 #include <linux/device.h>
0014 #include <linux/init.h>
0015 #include <linux/io.h>
0016 #include <linux/ioport.h>
0017 #include <linux/lantiq.h>
0018 #include <linux/module.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/serial.h>
0021 #include <linux/serial_core.h>
0022 #include <linux/slab.h>
0023 #include <linux/sysrq.h>
0024 #include <linux/tty.h>
0025 #include <linux/tty_flip.h>
0026 
0027 #define PORT_LTQ_ASC        111
0028 #define MAXPORTS        2
0029 #define UART_DUMMY_UER_RX   1
0030 #define DRVNAME         "lantiq,asc"
0031 #ifdef __BIG_ENDIAN
0032 #define LTQ_ASC_TBUF        (0x0020 + 3)
0033 #define LTQ_ASC_RBUF        (0x0024 + 3)
0034 #else
0035 #define LTQ_ASC_TBUF        0x0020
0036 #define LTQ_ASC_RBUF        0x0024
0037 #endif
0038 #define LTQ_ASC_FSTAT       0x0048
0039 #define LTQ_ASC_WHBSTATE    0x0018
0040 #define LTQ_ASC_STATE       0x0014
0041 #define LTQ_ASC_IRNCR       0x00F8
0042 #define LTQ_ASC_CLC     0x0000
0043 #define LTQ_ASC_ID      0x0008
0044 #define LTQ_ASC_PISEL       0x0004
0045 #define LTQ_ASC_TXFCON      0x0044
0046 #define LTQ_ASC_RXFCON      0x0040
0047 #define LTQ_ASC_CON     0x0010
0048 #define LTQ_ASC_BG      0x0050
0049 #define LTQ_ASC_IRNREN      0x00F4
0050 
0051 #define ASC_IRNREN_TX       0x1
0052 #define ASC_IRNREN_RX       0x2
0053 #define ASC_IRNREN_ERR      0x4
0054 #define ASC_IRNREN_TX_BUF   0x8
0055 #define ASC_IRNCR_TIR       0x1
0056 #define ASC_IRNCR_RIR       0x2
0057 #define ASC_IRNCR_EIR       0x4
0058 #define ASC_IRNCR_MASK      GENMASK(2, 0)
0059 
0060 #define ASCOPT_CSIZE        0x3
0061 #define TXFIFO_FL       1
0062 #define RXFIFO_FL       1
0063 #define ASCCLC_DISS     0x2
0064 #define ASCCLC_RMCMASK      0x0000FF00
0065 #define ASCCLC_RMCOFFSET    8
0066 #define ASCCON_M_8ASYNC     0x0
0067 #define ASCCON_M_7ASYNC     0x2
0068 #define ASCCON_ODD      0x00000020
0069 #define ASCCON_STP      0x00000080
0070 #define ASCCON_BRS      0x00000100
0071 #define ASCCON_FDE      0x00000200
0072 #define ASCCON_R        0x00008000
0073 #define ASCCON_FEN      0x00020000
0074 #define ASCCON_ROEN     0x00080000
0075 #define ASCCON_TOEN     0x00100000
0076 #define ASCSTATE_PE     0x00010000
0077 #define ASCSTATE_FE     0x00020000
0078 #define ASCSTATE_ROE        0x00080000
0079 #define ASCSTATE_ANY        (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
0080 #define ASCWHBSTATE_CLRREN  0x00000001
0081 #define ASCWHBSTATE_SETREN  0x00000002
0082 #define ASCWHBSTATE_CLRPE   0x00000004
0083 #define ASCWHBSTATE_CLRFE   0x00000008
0084 #define ASCWHBSTATE_CLRROE  0x00000020
0085 #define ASCTXFCON_TXFEN     0x0001
0086 #define ASCTXFCON_TXFFLU    0x0002
0087 #define ASCTXFCON_TXFITLMASK    0x3F00
0088 #define ASCTXFCON_TXFITLOFF 8
0089 #define ASCRXFCON_RXFEN     0x0001
0090 #define ASCRXFCON_RXFFLU    0x0002
0091 #define ASCRXFCON_RXFITLMASK    0x3F00
0092 #define ASCRXFCON_RXFITLOFF 8
0093 #define ASCFSTAT_RXFFLMASK  0x003F
0094 #define ASCFSTAT_TXFFLMASK  0x3F00
0095 #define ASCFSTAT_TXFREEMASK 0x3F000000
0096 #define ASCFSTAT_TXFREEOFF  24
0097 
0098 static void lqasc_tx_chars(struct uart_port *port);
0099 static struct ltq_uart_port *lqasc_port[MAXPORTS];
0100 static struct uart_driver lqasc_reg;
0101 
0102 struct ltq_soc_data {
0103     int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
0104     int (*request_irq)(struct uart_port *port);
0105     void    (*free_irq)(struct uart_port *port);
0106 };
0107 
0108 struct ltq_uart_port {
0109     struct uart_port    port;
0110     /* clock used to derive divider */
0111     struct clk      *freqclk;
0112     /* clock gating of the ASC core */
0113     struct clk      *clk;
0114     unsigned int        tx_irq;
0115     unsigned int        rx_irq;
0116     unsigned int        err_irq;
0117     unsigned int        common_irq;
0118     spinlock_t      lock; /* exclusive access for multi core */
0119 
0120     const struct ltq_soc_data   *soc;
0121 };
0122 
0123 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
0124 {
0125     u32 tmp = __raw_readl(reg);
0126 
0127     __raw_writel((tmp & ~clear) | set, reg);
0128 }
0129 
0130 static inline struct
0131 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
0132 {
0133     return container_of(port, struct ltq_uart_port, port);
0134 }
0135 
0136 static void
0137 lqasc_stop_tx(struct uart_port *port)
0138 {
0139     return;
0140 }
0141 
0142 static void
0143 lqasc_start_tx(struct uart_port *port)
0144 {
0145     unsigned long flags;
0146     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0147 
0148     spin_lock_irqsave(&ltq_port->lock, flags);
0149     lqasc_tx_chars(port);
0150     spin_unlock_irqrestore(&ltq_port->lock, flags);
0151     return;
0152 }
0153 
0154 static void
0155 lqasc_stop_rx(struct uart_port *port)
0156 {
0157     __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
0158 }
0159 
0160 static int
0161 lqasc_rx_chars(struct uart_port *port)
0162 {
0163     struct tty_port *tport = &port->state->port;
0164     unsigned int ch = 0, rsr = 0, fifocnt;
0165 
0166     fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
0167           ASCFSTAT_RXFFLMASK;
0168     while (fifocnt--) {
0169         u8 flag = TTY_NORMAL;
0170         ch = readb(port->membase + LTQ_ASC_RBUF);
0171         rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
0172             & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
0173         tty_flip_buffer_push(tport);
0174         port->icount.rx++;
0175 
0176         /*
0177          * Note that the error handling code is
0178          * out of the main execution path
0179          */
0180         if (rsr & ASCSTATE_ANY) {
0181             if (rsr & ASCSTATE_PE) {
0182                 port->icount.parity++;
0183                 asc_update_bits(0, ASCWHBSTATE_CLRPE,
0184                     port->membase + LTQ_ASC_WHBSTATE);
0185             } else if (rsr & ASCSTATE_FE) {
0186                 port->icount.frame++;
0187                 asc_update_bits(0, ASCWHBSTATE_CLRFE,
0188                     port->membase + LTQ_ASC_WHBSTATE);
0189             }
0190             if (rsr & ASCSTATE_ROE) {
0191                 port->icount.overrun++;
0192                 asc_update_bits(0, ASCWHBSTATE_CLRROE,
0193                     port->membase + LTQ_ASC_WHBSTATE);
0194             }
0195 
0196             rsr &= port->read_status_mask;
0197 
0198             if (rsr & ASCSTATE_PE)
0199                 flag = TTY_PARITY;
0200             else if (rsr & ASCSTATE_FE)
0201                 flag = TTY_FRAME;
0202         }
0203 
0204         if ((rsr & port->ignore_status_mask) == 0)
0205             tty_insert_flip_char(tport, ch, flag);
0206 
0207         if (rsr & ASCSTATE_ROE)
0208             /*
0209              * Overrun is special, since it's reported
0210              * immediately, and doesn't affect the current
0211              * character
0212              */
0213             tty_insert_flip_char(tport, 0, TTY_OVERRUN);
0214     }
0215 
0216     if (ch != 0)
0217         tty_flip_buffer_push(tport);
0218 
0219     return 0;
0220 }
0221 
0222 static void
0223 lqasc_tx_chars(struct uart_port *port)
0224 {
0225     struct circ_buf *xmit = &port->state->xmit;
0226     if (uart_tx_stopped(port)) {
0227         lqasc_stop_tx(port);
0228         return;
0229     }
0230 
0231     while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
0232         ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
0233         if (port->x_char) {
0234             writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
0235             port->icount.tx++;
0236             port->x_char = 0;
0237             continue;
0238         }
0239 
0240         if (uart_circ_empty(xmit))
0241             break;
0242 
0243         writeb(port->state->xmit.buf[port->state->xmit.tail],
0244             port->membase + LTQ_ASC_TBUF);
0245         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0246         port->icount.tx++;
0247     }
0248 
0249     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0250         uart_write_wakeup(port);
0251 }
0252 
0253 static irqreturn_t
0254 lqasc_tx_int(int irq, void *_port)
0255 {
0256     unsigned long flags;
0257     struct uart_port *port = (struct uart_port *)_port;
0258     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0259 
0260     spin_lock_irqsave(&ltq_port->lock, flags);
0261     __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
0262     spin_unlock_irqrestore(&ltq_port->lock, flags);
0263     lqasc_start_tx(port);
0264     return IRQ_HANDLED;
0265 }
0266 
0267 static irqreturn_t
0268 lqasc_err_int(int irq, void *_port)
0269 {
0270     unsigned long flags;
0271     struct uart_port *port = (struct uart_port *)_port;
0272     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0273 
0274     spin_lock_irqsave(&ltq_port->lock, flags);
0275     /* clear any pending interrupts */
0276     asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
0277         ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
0278     spin_unlock_irqrestore(&ltq_port->lock, flags);
0279     return IRQ_HANDLED;
0280 }
0281 
0282 static irqreturn_t
0283 lqasc_rx_int(int irq, void *_port)
0284 {
0285     unsigned long flags;
0286     struct uart_port *port = (struct uart_port *)_port;
0287     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0288 
0289     spin_lock_irqsave(&ltq_port->lock, flags);
0290     __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
0291     lqasc_rx_chars(port);
0292     spin_unlock_irqrestore(&ltq_port->lock, flags);
0293     return IRQ_HANDLED;
0294 }
0295 
0296 static irqreturn_t lqasc_irq(int irq, void *p)
0297 {
0298     unsigned long flags;
0299     u32 stat;
0300     struct uart_port *port = p;
0301     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0302 
0303     spin_lock_irqsave(&ltq_port->lock, flags);
0304     stat = readl(port->membase + LTQ_ASC_IRNCR);
0305     spin_unlock_irqrestore(&ltq_port->lock, flags);
0306     if (!(stat & ASC_IRNCR_MASK))
0307         return IRQ_NONE;
0308 
0309     if (stat & ASC_IRNCR_TIR)
0310         lqasc_tx_int(irq, p);
0311 
0312     if (stat & ASC_IRNCR_RIR)
0313         lqasc_rx_int(irq, p);
0314 
0315     if (stat & ASC_IRNCR_EIR)
0316         lqasc_err_int(irq, p);
0317 
0318     return IRQ_HANDLED;
0319 }
0320 
0321 static unsigned int
0322 lqasc_tx_empty(struct uart_port *port)
0323 {
0324     int status;
0325     status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
0326          ASCFSTAT_TXFFLMASK;
0327     return status ? 0 : TIOCSER_TEMT;
0328 }
0329 
0330 static unsigned int
0331 lqasc_get_mctrl(struct uart_port *port)
0332 {
0333     return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
0334 }
0335 
0336 static void
0337 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
0338 {
0339 }
0340 
0341 static void
0342 lqasc_break_ctl(struct uart_port *port, int break_state)
0343 {
0344 }
0345 
0346 static int
0347 lqasc_startup(struct uart_port *port)
0348 {
0349     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0350     int retval;
0351     unsigned long flags;
0352 
0353     if (!IS_ERR(ltq_port->clk))
0354         clk_prepare_enable(ltq_port->clk);
0355     port->uartclk = clk_get_rate(ltq_port->freqclk);
0356 
0357     spin_lock_irqsave(&ltq_port->lock, flags);
0358     asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
0359         port->membase + LTQ_ASC_CLC);
0360 
0361     __raw_writel(0, port->membase + LTQ_ASC_PISEL);
0362     __raw_writel(
0363         ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
0364         ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
0365         port->membase + LTQ_ASC_TXFCON);
0366     __raw_writel(
0367         ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
0368         | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
0369         port->membase + LTQ_ASC_RXFCON);
0370     /* make sure other settings are written to hardware before
0371      * setting enable bits
0372      */
0373     wmb();
0374     asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
0375         ASCCON_ROEN, port->membase + LTQ_ASC_CON);
0376 
0377     spin_unlock_irqrestore(&ltq_port->lock, flags);
0378 
0379     retval = ltq_port->soc->request_irq(port);
0380     if (retval)
0381         return retval;
0382 
0383     __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
0384         port->membase + LTQ_ASC_IRNREN);
0385     return retval;
0386 }
0387 
0388 static void
0389 lqasc_shutdown(struct uart_port *port)
0390 {
0391     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0392     unsigned long flags;
0393 
0394     ltq_port->soc->free_irq(port);
0395 
0396     spin_lock_irqsave(&ltq_port->lock, flags);
0397     __raw_writel(0, port->membase + LTQ_ASC_CON);
0398     asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
0399         port->membase + LTQ_ASC_RXFCON);
0400     asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
0401         port->membase + LTQ_ASC_TXFCON);
0402     spin_unlock_irqrestore(&ltq_port->lock, flags);
0403     if (!IS_ERR(ltq_port->clk))
0404         clk_disable_unprepare(ltq_port->clk);
0405 }
0406 
0407 static void
0408 lqasc_set_termios(struct uart_port *port,
0409     struct ktermios *new, struct ktermios *old)
0410 {
0411     unsigned int cflag;
0412     unsigned int iflag;
0413     unsigned int divisor;
0414     unsigned int baud;
0415     unsigned int con = 0;
0416     unsigned long flags;
0417     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0418 
0419     cflag = new->c_cflag;
0420     iflag = new->c_iflag;
0421 
0422     switch (cflag & CSIZE) {
0423     case CS7:
0424         con = ASCCON_M_7ASYNC;
0425         break;
0426 
0427     case CS5:
0428     case CS6:
0429     default:
0430         new->c_cflag &= ~ CSIZE;
0431         new->c_cflag |= CS8;
0432         con = ASCCON_M_8ASYNC;
0433         break;
0434     }
0435 
0436     cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
0437 
0438     if (cflag & CSTOPB)
0439         con |= ASCCON_STP;
0440 
0441     if (cflag & PARENB) {
0442         if (!(cflag & PARODD))
0443             con &= ~ASCCON_ODD;
0444         else
0445             con |= ASCCON_ODD;
0446     }
0447 
0448     port->read_status_mask = ASCSTATE_ROE;
0449     if (iflag & INPCK)
0450         port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
0451 
0452     port->ignore_status_mask = 0;
0453     if (iflag & IGNPAR)
0454         port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
0455 
0456     if (iflag & IGNBRK) {
0457         /*
0458          * If we're ignoring parity and break indicators,
0459          * ignore overruns too (for real raw support).
0460          */
0461         if (iflag & IGNPAR)
0462             port->ignore_status_mask |= ASCSTATE_ROE;
0463     }
0464 
0465     if ((cflag & CREAD) == 0)
0466         port->ignore_status_mask |= UART_DUMMY_UER_RX;
0467 
0468     /* set error signals  - framing, parity  and overrun, enable receiver */
0469     con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
0470 
0471     spin_lock_irqsave(&ltq_port->lock, flags);
0472 
0473     /* set up CON */
0474     asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
0475 
0476     /* Set baud rate - take a divider of 2 into account */
0477     baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
0478     divisor = uart_get_divisor(port, baud);
0479     divisor = divisor / 2 - 1;
0480 
0481     /* disable the baudrate generator */
0482     asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
0483 
0484     /* make sure the fractional divider is off */
0485     asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
0486 
0487     /* set up to use divisor of 2 */
0488     asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
0489 
0490     /* now we can write the new baudrate into the register */
0491     __raw_writel(divisor, port->membase + LTQ_ASC_BG);
0492 
0493     /* turn the baudrate generator back on */
0494     asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
0495 
0496     /* enable rx */
0497     __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
0498 
0499     spin_unlock_irqrestore(&ltq_port->lock, flags);
0500 
0501     /* Don't rewrite B0 */
0502     if (tty_termios_baud_rate(new))
0503         tty_termios_encode_baud_rate(new, baud, baud);
0504 
0505     uart_update_timeout(port, cflag, baud);
0506 }
0507 
0508 static const char*
0509 lqasc_type(struct uart_port *port)
0510 {
0511     if (port->type == PORT_LTQ_ASC)
0512         return DRVNAME;
0513     else
0514         return NULL;
0515 }
0516 
0517 static void
0518 lqasc_release_port(struct uart_port *port)
0519 {
0520     struct platform_device *pdev = to_platform_device(port->dev);
0521 
0522     if (port->flags & UPF_IOREMAP) {
0523         devm_iounmap(&pdev->dev, port->membase);
0524         port->membase = NULL;
0525     }
0526 }
0527 
0528 static int
0529 lqasc_request_port(struct uart_port *port)
0530 {
0531     struct platform_device *pdev = to_platform_device(port->dev);
0532     struct resource *res;
0533     int size;
0534 
0535     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0536     if (!res) {
0537         dev_err(&pdev->dev, "cannot obtain I/O memory region");
0538         return -ENODEV;
0539     }
0540     size = resource_size(res);
0541 
0542     res = devm_request_mem_region(&pdev->dev, res->start,
0543         size, dev_name(&pdev->dev));
0544     if (!res) {
0545         dev_err(&pdev->dev, "cannot request I/O memory region");
0546         return -EBUSY;
0547     }
0548 
0549     if (port->flags & UPF_IOREMAP) {
0550         port->membase = devm_ioremap(&pdev->dev,
0551             port->mapbase, size);
0552         if (port->membase == NULL)
0553             return -ENOMEM;
0554     }
0555     return 0;
0556 }
0557 
0558 static void
0559 lqasc_config_port(struct uart_port *port, int flags)
0560 {
0561     if (flags & UART_CONFIG_TYPE) {
0562         port->type = PORT_LTQ_ASC;
0563         lqasc_request_port(port);
0564     }
0565 }
0566 
0567 static int
0568 lqasc_verify_port(struct uart_port *port,
0569     struct serial_struct *ser)
0570 {
0571     int ret = 0;
0572     if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
0573         ret = -EINVAL;
0574     if (ser->irq < 0 || ser->irq >= NR_IRQS)
0575         ret = -EINVAL;
0576     if (ser->baud_base < 9600)
0577         ret = -EINVAL;
0578     return ret;
0579 }
0580 
0581 static const struct uart_ops lqasc_pops = {
0582     .tx_empty = lqasc_tx_empty,
0583     .set_mctrl =    lqasc_set_mctrl,
0584     .get_mctrl =    lqasc_get_mctrl,
0585     .stop_tx =  lqasc_stop_tx,
0586     .start_tx = lqasc_start_tx,
0587     .stop_rx =  lqasc_stop_rx,
0588     .break_ctl =    lqasc_break_ctl,
0589     .startup =  lqasc_startup,
0590     .shutdown = lqasc_shutdown,
0591     .set_termios =  lqasc_set_termios,
0592     .type =     lqasc_type,
0593     .release_port = lqasc_release_port,
0594     .request_port = lqasc_request_port,
0595     .config_port =  lqasc_config_port,
0596     .verify_port =  lqasc_verify_port,
0597 };
0598 
0599 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
0600 static void
0601 lqasc_console_putchar(struct uart_port *port, unsigned char ch)
0602 {
0603     int fifofree;
0604 
0605     if (!port->membase)
0606         return;
0607 
0608     do {
0609         fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
0610             & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
0611     } while (fifofree == 0);
0612     writeb(ch, port->membase + LTQ_ASC_TBUF);
0613 }
0614 
0615 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
0616                     u_int count)
0617 {
0618     uart_console_write(port, s, count, lqasc_console_putchar);
0619 }
0620 
0621 static void
0622 lqasc_console_write(struct console *co, const char *s, u_int count)
0623 {
0624     struct ltq_uart_port *ltq_port;
0625     unsigned long flags;
0626 
0627     if (co->index >= MAXPORTS)
0628         return;
0629 
0630     ltq_port = lqasc_port[co->index];
0631     if (!ltq_port)
0632         return;
0633 
0634     spin_lock_irqsave(&ltq_port->lock, flags);
0635     lqasc_serial_port_write(&ltq_port->port, s, count);
0636     spin_unlock_irqrestore(&ltq_port->lock, flags);
0637 }
0638 
0639 static int __init
0640 lqasc_console_setup(struct console *co, char *options)
0641 {
0642     struct ltq_uart_port *ltq_port;
0643     struct uart_port *port;
0644     int baud = 115200;
0645     int bits = 8;
0646     int parity = 'n';
0647     int flow = 'n';
0648 
0649     if (co->index >= MAXPORTS)
0650         return -ENODEV;
0651 
0652     ltq_port = lqasc_port[co->index];
0653     if (!ltq_port)
0654         return -ENODEV;
0655 
0656     port = &ltq_port->port;
0657 
0658     if (!IS_ERR(ltq_port->clk))
0659         clk_prepare_enable(ltq_port->clk);
0660 
0661     port->uartclk = clk_get_rate(ltq_port->freqclk);
0662 
0663     if (options)
0664         uart_parse_options(options, &baud, &parity, &bits, &flow);
0665     return uart_set_options(port, co, baud, parity, bits, flow);
0666 }
0667 
0668 static struct console lqasc_console = {
0669     .name =     "ttyLTQ",
0670     .write =    lqasc_console_write,
0671     .device =   uart_console_device,
0672     .setup =    lqasc_console_setup,
0673     .flags =    CON_PRINTBUFFER,
0674     .index =    -1,
0675     .data =     &lqasc_reg,
0676 };
0677 
0678 static int __init
0679 lqasc_console_init(void)
0680 {
0681     register_console(&lqasc_console);
0682     return 0;
0683 }
0684 console_initcall(lqasc_console_init);
0685 
0686 static void lqasc_serial_early_console_write(struct console *co,
0687                          const char *s,
0688                          u_int count)
0689 {
0690     struct earlycon_device *dev = co->data;
0691 
0692     lqasc_serial_port_write(&dev->port, s, count);
0693 }
0694 
0695 static int __init
0696 lqasc_serial_early_console_setup(struct earlycon_device *device,
0697                  const char *opt)
0698 {
0699     if (!device->port.membase)
0700         return -ENODEV;
0701 
0702     device->con->write = lqasc_serial_early_console_write;
0703     return 0;
0704 }
0705 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
0706 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
0707 
0708 #define LANTIQ_SERIAL_CONSOLE   (&lqasc_console)
0709 
0710 #else
0711 
0712 #define LANTIQ_SERIAL_CONSOLE   NULL
0713 
0714 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
0715 
0716 static struct uart_driver lqasc_reg = {
0717     .owner =    THIS_MODULE,
0718     .driver_name =  DRVNAME,
0719     .dev_name = "ttyLTQ",
0720     .major =    0,
0721     .minor =    0,
0722     .nr =       MAXPORTS,
0723     .cons =     LANTIQ_SERIAL_CONSOLE,
0724 };
0725 
0726 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
0727 {
0728     struct uart_port *port = &ltq_port->port;
0729     struct platform_device *pdev = to_platform_device(dev);
0730     int irq;
0731 
0732     irq = platform_get_irq(pdev, 0);
0733     if (irq < 0)
0734         return irq;
0735     ltq_port->tx_irq = irq;
0736     irq = platform_get_irq(pdev, 1);
0737     if (irq < 0)
0738         return irq;
0739     ltq_port->rx_irq = irq;
0740     irq = platform_get_irq(pdev, 2);
0741     if (irq < 0)
0742         return irq;
0743     ltq_port->err_irq = irq;
0744 
0745     port->irq = ltq_port->tx_irq;
0746 
0747     return 0;
0748 }
0749 
0750 static int request_irq_lantiq(struct uart_port *port)
0751 {
0752     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0753     int retval;
0754 
0755     retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
0756                  0, "asc_tx", port);
0757     if (retval) {
0758         dev_err(port->dev, "failed to request asc_tx\n");
0759         return retval;
0760     }
0761 
0762     retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
0763                  0, "asc_rx", port);
0764     if (retval) {
0765         dev_err(port->dev, "failed to request asc_rx\n");
0766         goto err1;
0767     }
0768 
0769     retval = request_irq(ltq_port->err_irq, lqasc_err_int,
0770                  0, "asc_err", port);
0771     if (retval) {
0772         dev_err(port->dev, "failed to request asc_err\n");
0773         goto err2;
0774     }
0775     return 0;
0776 
0777 err2:
0778     free_irq(ltq_port->rx_irq, port);
0779 err1:
0780     free_irq(ltq_port->tx_irq, port);
0781     return retval;
0782 }
0783 
0784 static void free_irq_lantiq(struct uart_port *port)
0785 {
0786     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0787 
0788     free_irq(ltq_port->tx_irq, port);
0789     free_irq(ltq_port->rx_irq, port);
0790     free_irq(ltq_port->err_irq, port);
0791 }
0792 
0793 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
0794 {
0795     struct uart_port *port = &ltq_port->port;
0796     int ret;
0797 
0798     ret = platform_get_irq(to_platform_device(dev), 0);
0799     if (ret < 0) {
0800         dev_err(dev, "failed to fetch IRQ for serial port\n");
0801         return ret;
0802     }
0803     ltq_port->common_irq = ret;
0804     port->irq = ret;
0805 
0806     return 0;
0807 }
0808 
0809 static int request_irq_intel(struct uart_port *port)
0810 {
0811     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0812     int retval;
0813 
0814     retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
0815                  "asc_irq", port);
0816     if (retval)
0817         dev_err(port->dev, "failed to request asc_irq\n");
0818 
0819     return retval;
0820 }
0821 
0822 static void free_irq_intel(struct uart_port *port)
0823 {
0824     struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
0825 
0826     free_irq(ltq_port->common_irq, port);
0827 }
0828 
0829 static int lqasc_probe(struct platform_device *pdev)
0830 {
0831     struct device_node *node = pdev->dev.of_node;
0832     struct ltq_uart_port *ltq_port;
0833     struct uart_port *port;
0834     struct resource *mmres;
0835     int line;
0836     int ret;
0837 
0838     mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0839     if (!mmres) {
0840         dev_err(&pdev->dev,
0841             "failed to get memory for serial port\n");
0842         return -ENODEV;
0843     }
0844 
0845     ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
0846                 GFP_KERNEL);
0847     if (!ltq_port)
0848         return -ENOMEM;
0849 
0850     port = &ltq_port->port;
0851 
0852     ltq_port->soc = of_device_get_match_data(&pdev->dev);
0853     ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
0854     if (ret)
0855         return ret;
0856 
0857     /* get serial id */
0858     line = of_alias_get_id(node, "serial");
0859     if (line < 0) {
0860         if (IS_ENABLED(CONFIG_LANTIQ)) {
0861             if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
0862                 line = 0;
0863             else
0864                 line = 1;
0865         } else {
0866             dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
0867                 line);
0868             return line;
0869         }
0870     }
0871 
0872     if (lqasc_port[line]) {
0873         dev_err(&pdev->dev, "port %d already allocated\n", line);
0874         return -EBUSY;
0875     }
0876 
0877     port->iotype    = SERIAL_IO_MEM;
0878     port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
0879     port->ops   = &lqasc_pops;
0880     port->fifosize  = 16;
0881     port->type  = PORT_LTQ_ASC;
0882     port->line  = line;
0883     port->dev   = &pdev->dev;
0884     /* unused, just to be backward-compatible */
0885     port->mapbase   = mmres->start;
0886 
0887     if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
0888         ltq_port->freqclk = clk_get_fpi();
0889     else
0890         ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
0891 
0892 
0893     if (IS_ERR(ltq_port->freqclk)) {
0894         pr_err("failed to get fpi clk\n");
0895         return -ENOENT;
0896     }
0897 
0898     /* not all asc ports have clock gates, lets ignore the return code */
0899     if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
0900         ltq_port->clk = clk_get(&pdev->dev, NULL);
0901     else
0902         ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
0903 
0904     spin_lock_init(&ltq_port->lock);
0905     lqasc_port[line] = ltq_port;
0906     platform_set_drvdata(pdev, ltq_port);
0907 
0908     ret = uart_add_one_port(&lqasc_reg, port);
0909 
0910     return ret;
0911 }
0912 
0913 static int lqasc_remove(struct platform_device *pdev)
0914 {
0915     struct uart_port *port = platform_get_drvdata(pdev);
0916 
0917     return uart_remove_one_port(&lqasc_reg, port);
0918 }
0919 
0920 static const struct ltq_soc_data soc_data_lantiq = {
0921     .fetch_irq = fetch_irq_lantiq,
0922     .request_irq = request_irq_lantiq,
0923     .free_irq = free_irq_lantiq,
0924 };
0925 
0926 static const struct ltq_soc_data soc_data_intel = {
0927     .fetch_irq = fetch_irq_intel,
0928     .request_irq = request_irq_intel,
0929     .free_irq = free_irq_intel,
0930 };
0931 
0932 static const struct of_device_id ltq_asc_match[] = {
0933     { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
0934     { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
0935     {},
0936 };
0937 MODULE_DEVICE_TABLE(of, ltq_asc_match);
0938 
0939 static struct platform_driver lqasc_driver = {
0940     .probe      = lqasc_probe,
0941     .remove     = lqasc_remove,
0942     .driver     = {
0943         .name   = DRVNAME,
0944         .of_match_table = ltq_asc_match,
0945     },
0946 };
0947 
0948 static int __init
0949 init_lqasc(void)
0950 {
0951     int ret;
0952 
0953     ret = uart_register_driver(&lqasc_reg);
0954     if (ret != 0)
0955         return ret;
0956 
0957     ret = platform_driver_register(&lqasc_driver);
0958     if (ret != 0)
0959         uart_unregister_driver(&lqasc_reg);
0960 
0961     return ret;
0962 }
0963 
0964 static void __exit exit_lqasc(void)
0965 {
0966     platform_driver_unregister(&lqasc_driver);
0967     uart_unregister_driver(&lqasc_reg);
0968 }
0969 
0970 module_init(init_lqasc);
0971 module_exit(exit_lqasc);
0972 
0973 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
0974 MODULE_LICENSE("GPL v2");
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