tty/serial/ip22zilog.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _IP22_ZILOG_H
0003 #define _IP22_ZILOG_H
0004
0005 #include <asm/byteorder.h>
0006
0007 struct zilog_channel {
0008 #ifdef __BIG_ENDIAN
0009     volatile unsigned char unused0[3];
0010     volatile unsigned char control;
0011     volatile unsigned char unused1[3];
0012     volatile unsigned char data;
0013 #else /* __LITTLE_ENDIAN */
0014     volatile unsigned char control;
0015     volatile unsigned char unused0[3];
0016     volatile unsigned char data;
0017     volatile unsigned char unused1[3];
0018 #endif
0019 };
0020
0021 struct zilog_layout {
0022     struct zilog_channel channelB;
0023     struct zilog_channel channelA;
0024 };
0025
0026 #define NUM_ZSREGS    16
0027
0028 /* Conversion routines to/from brg time constants from/to bits
0029  * per second.
0030  */
0031 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
0032 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
0033
0034 /* The Zilog register set */
0035
0036 #define FLAG    0x7e
0037
0038 /* Write Register 0 */
0039 #define R0  0       /* Register selects */
0040 #define R1  1
0041 #define R2  2
0042 #define R3  3
0043 #define R4  4
0044 #define R5  5
0045 #define R6  6
0046 #define R7  7
0047 #define R8  8
0048 #define R9  9
0049 #define R10 10
0050 #define R11 11
0051 #define R12 12
0052 #define R13 13
0053 #define R14 14
0054 #define R15 15
0055
0056 #define NULLCODE    0   /* Null Code */
0057 #define POINT_HIGH  0x8 /* Select upper half of registers */
0058 #define RES_EXT_INT 0x10    /* Reset Ext. Status Interrupts */
0059 #define SEND_ABORT  0x18    /* HDLC Abort */
0060 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
0061 #define RES_Tx_P    0x28    /* Reset TxINT Pending */
0062 #define ERR_RES     0x30    /* Error Reset */
0063 #define RES_H_IUS   0x38    /* Reset highest IUS */
0064
0065 #define RES_Rx_CRC  0x40    /* Reset Rx CRC Checker */
0066 #define RES_Tx_CRC  0x80    /* Reset Tx CRC Checker */
0067 #define RES_EOM_L   0xC0    /* Reset EOM latch */
0068
0069 /* Write Register 1 */
0070
0071 #define EXT_INT_ENAB    0x1 /* Ext Int Enable */
0072 #define TxINT_ENAB  0x2 /* Tx Int Enable */
0073 #define PAR_SPEC    0x4 /* Parity is special condition */
0074
0075 #define RxINT_DISAB 0   /* Rx Int Disable */
0076 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
0077 #define INT_ALL_Rx  0x10    /* Int on all Rx Characters or error */
0078 #define INT_ERR_Rx  0x18    /* Int on error only */
0079 #define RxINT_MASK  0x18
0080
0081 #define WT_RDY_RT   0x20    /* Wait/Ready on R/T */
0082 #define WT_FN_RDYFN 0x40    /* Wait/FN/Ready FN */
0083 #define WT_RDY_ENAB 0x80    /* Wait/Ready Enable */
0084
0085 /* Write Register #2 (Interrupt Vector) */
0086
0087 /* Write Register 3 */
0088
0089 #define RxENAB      0x1 /* Rx Enable */
0090 #define SYNC_L_INH  0x2 /* Sync Character Load Inhibit */
0091 #define ADD_SM      0x4 /* Address Search Mode (SDLC) */
0092 #define RxCRC_ENAB  0x8 /* Rx CRC Enable */
0093 #define ENT_HM      0x10    /* Enter Hunt Mode */
0094 #define AUTO_ENAB   0x20    /* Auto Enables */
0095 #define Rx5     0x0 /* Rx 5 Bits/Character */
0096 #define Rx7     0x40    /* Rx 7 Bits/Character */
0097 #define Rx6     0x80    /* Rx 6 Bits/Character */
0098 #define Rx8     0xc0    /* Rx 8 Bits/Character */
0099 #define RxN_MASK    0xc0
0100
0101 /* Write Register 4 */
0102
0103 #define PAR_ENAB    0x1 /* Parity Enable */
0104 #define PAR_EVEN    0x2 /* Parity Even/Odd* */
0105
0106 #define SYNC_ENAB   0   /* Sync Modes Enable */
0107 #define SB1     0x4 /* 1 stop bit/char */
0108 #define SB15        0x8 /* 1.5 stop bits/char */
0109 #define SB2     0xc /* 2 stop bits/char */
0110
0111 #define MONSYNC     0   /* 8 Bit Sync character */
0112 #define BISYNC      0x10    /* 16 bit sync character */
0113 #define SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
0114 #define EXTSYNC     0x30    /* External Sync Mode */
0115
0116 #define X1CLK       0x0 /* x1 clock mode */
0117 #define X16CLK      0x40    /* x16 clock mode */
0118 #define X32CLK      0x80    /* x32 clock mode */
0119 #define X64CLK      0xC0    /* x64 clock mode */
0120 #define XCLK_MASK   0xC0
0121
0122 /* Write Register 5 */
0123
0124 #define TxCRC_ENAB  0x1 /* Tx CRC Enable */
0125 #define RTS     0x2 /* RTS */
0126 #define SDLC_CRC    0x4 /* SDLC/CRC-16 */
0127 #define TxENAB      0x8 /* Tx Enable */
0128 #define SND_BRK     0x10    /* Send Break */
0129 #define Tx5     0x0 /* Tx 5 bits (or less)/character */
0130 #define Tx7     0x20    /* Tx 7 bits/character */
0131 #define Tx6     0x40    /* Tx 6 bits/character */
0132 #define Tx8     0x60    /* Tx 8 bits/character */
0133 #define TxN_MASK    0x60
0134 #define DTR     0x80    /* DTR */
0135
0136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
0137
0138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
0139
0140 /* Write Register 8 (transmit buffer) */
0141
0142 /* Write Register 9 (Master interrupt control) */
0143 #define VIS 1   /* Vector Includes Status */
0144 #define NV  2   /* No Vector */
0145 #define DLC 4   /* Disable Lower Chain */
0146 #define MIE 8   /* Master Interrupt Enable */
0147 #define STATHI  0x10    /* Status high */
0148 #define NORESET 0   /* No reset on write to R9 */
0149 #define CHRB    0x40    /* Reset channel B */
0150 #define CHRA    0x80    /* Reset channel A */
0151 #define FHWRES  0xc0    /* Force hardware reset */
0152
0153 /* Write Register 10 (misc control bits) */
0154 #define BIT6    1   /* 6 bit/8bit sync */
0155 #define LOOPMODE 2  /* SDLC Loop mode */
0156 #define ABUNDER 4   /* Abort/flag on SDLC xmit underrun */
0157 #define MARKIDLE 8  /* Mark/flag on idle */
0158 #define GAOP    0x10    /* Go active on poll */
0159 #define NRZ 0   /* NRZ mode */
0160 #define NRZI    0x20    /* NRZI mode */
0161 #define FM1 0x40    /* FM1 (transition = 1) */
0162 #define FM0 0x60    /* FM0 (transition = 0) */
0163 #define CRCPS   0x80    /* CRC Preset I/O */
0164
0165 /* Write Register 11 (Clock Mode control) */
0166 #define TRxCXT  0   /* TRxC = Xtal output */
0167 #define TRxCTC  1   /* TRxC = Transmit clock */
0168 #define TRxCBR  2   /* TRxC = BR Generator Output */
0169 #define TRxCDP  3   /* TRxC = DPLL output */
0170 #define TRxCOI  4   /* TRxC O/I */
0171 #define TCRTxCP 0   /* Transmit clock = RTxC pin */
0172 #define TCTRxCP 8   /* Transmit clock = TRxC pin */
0173 #define TCBR    0x10    /* Transmit clock = BR Generator output */
0174 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
0175 #define RCRTxCP 0   /* Receive clock = RTxC pin */
0176 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
0177 #define RCBR    0x40    /* Receive clock = BR Generator output */
0178 #define RCDPLL  0x60    /* Receive clock = DPLL output */
0179 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
0180
0181 /* Write Register 12 (lower byte of baud rate generator time constant) */
0182
0183 /* Write Register 13 (upper byte of baud rate generator time constant) */
0184
0185 /* Write Register 14 (Misc control bits) */
0186 #define BRENAB  1   /* Baud rate generator enable */
0187 #define BRSRC   2   /* Baud rate generator source */
0188 #define DTRREQ  4   /* DTR/Request function */
0189 #define AUTOECHO 8  /* Auto Echo */
0190 #define LOOPBAK 0x10    /* Local loopback */
0191 #define SEARCH  0x20    /* Enter search mode */
0192 #define RMC 0x40    /* Reset missing clock */
0193 #define DISDPLL 0x60    /* Disable DPLL */
0194 #define SSBR    0x80    /* Set DPLL source = BR generator */
0195 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
0196 #define SFMM    0xc0    /* Set FM mode */
0197 #define SNRZI   0xe0    /* Set NRZI mode */
0198
0199 /* Write Register 15 (external/status interrupt control) */
0200 #define ZCIE    2   /* Zero count IE */
0201 #define DCDIE   8   /* DCD IE */
0202 #define SYNCIE  0x10    /* Sync/hunt IE */
0203 #define CTSIE   0x20    /* CTS IE */
0204 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
0205 #define BRKIE   0x80    /* Break/Abort IE */
0206
0207
0208 /* Read Register 0 */
0209 #define Rx_CH_AV    0x1 /* Rx Character Available */
0210 #define ZCOUNT      0x2 /* Zero count */
0211 #define Tx_BUF_EMP  0x4 /* Tx Buffer empty */
0212 #define DCD     0x8 /* DCD */
0213 #define SYNC        0x10    /* Sync/hunt */
0214 #define CTS     0x20    /* CTS */
0215 #define TxEOM       0x40    /* Tx underrun */
0216 #define BRK_ABRT    0x80    /* Break/Abort */
0217
0218 /* Read Register 1 */
0219 #define ALL_SNT     0x1 /* All sent */
0220 /* Residue Data for 8 Rx bits/char programmed */
0221 #define RES3        0x8 /* 0/3 */
0222 #define RES4        0x4 /* 0/4 */
0223 #define RES5        0xc /* 0/5 */
0224 #define RES6        0x2 /* 0/6 */
0225 #define RES7        0xa /* 0/7 */
0226 #define RES8        0x6 /* 0/8 */
0227 #define RES18       0xe /* 1/8 */
0228 #define RES28       0x0 /* 2/8 */
0229 /* Special Rx Condition Interrupts */
0230 #define PAR_ERR     0x10    /* Parity error */
0231 #define Rx_OVR      0x20    /* Rx Overrun Error */
0232 #define CRC_ERR     0x40    /* CRC/Framing Error */
0233 #define END_FR      0x80    /* End of Frame (SDLC) */
0234
0235 /* Read Register 2 (channel b only) - Interrupt vector */
0236 #define CHB_Tx_EMPTY    0x00
0237 #define CHB_EXT_STAT    0x02
0238 #define CHB_Rx_AVAIL    0x04
0239 #define CHB_SPECIAL 0x06
0240 #define CHA_Tx_EMPTY    0x08
0241 #define CHA_EXT_STAT    0x0a
0242 #define CHA_Rx_AVAIL    0x0c
0243 #define CHA_SPECIAL 0x0e
0244 #define STATUS_MASK 0x0e
0245
0246 /* Read Register 3 (interrupt pending register) ch a only */
0247 #define CHBEXT  0x1     /* Channel B Ext/Stat IP */
0248 #define CHBTxIP 0x2     /* Channel B Tx IP */
0249 #define CHBRxIP 0x4     /* Channel B Rx IP */
0250 #define CHAEXT  0x8     /* Channel A Ext/Stat IP */
0251 #define CHATxIP 0x10        /* Channel A Tx IP */
0252 #define CHARxIP 0x20        /* Channel A Rx IP */
0253
0254 /* Read Register 8 (receive data register) */
0255
0256 /* Read Register 10  (misc status bits) */
0257 #define ONLOOP  2       /* On loop */
0258 #define LOOPSEND 0x10       /* Loop sending */
0259 #define CLK2MIS 0x40        /* Two clocks missing */
0260 #define CLK1MIS 0x80        /* One clock missing */
0261
0262 /* Read Register 12 (lower byte of baud rate generator constant) */
0263
0264 /* Read Register 13 (upper byte of baud rate generator constant) */
0265
0266 /* Read Register 15 (value of WR 15) */
0267
0268 /* Misc macros */
0269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
0270                      udelay(5); } while(0)
0271
0272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
0273                      udelay(5); } while(0)
0274
0275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
0276                      udelay(2); \
0277                      readb(&channel->data); \
0278                      udelay(2); \
0279                      readb(&channel->data); \
0280                      udelay(2); } while(0)
0281
0282 #endif /* _IP22_ZILOG_H */