Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale LINFlexD UART serial port driver
0004  *
0005  * Copyright 2012-2016 Freescale Semiconductor, Inc.
0006  * Copyright 2017-2019 NXP
0007  */
0008 
0009 #include <linux/console.h>
0010 #include <linux/io.h>
0011 #include <linux/irq.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/serial_core.h>
0016 #include <linux/slab.h>
0017 #include <linux/tty_flip.h>
0018 #include <linux/delay.h>
0019 
0020 /* All registers are 32-bit width */
0021 
0022 #define LINCR1  0x0000  /* LIN control register             */
0023 #define LINIER  0x0004  /* LIN interrupt enable register        */
0024 #define LINSR   0x0008  /* LIN status register              */
0025 #define LINESR  0x000C  /* LIN error status register            */
0026 #define UARTCR  0x0010  /* UART mode control register           */
0027 #define UARTSR  0x0014  /* UART mode status register            */
0028 #define LINTCSR 0x0018  /* LIN timeout control status register      */
0029 #define LINOCR  0x001C  /* LIN output compare register          */
0030 #define LINTOCR 0x0020  /* LIN timeout control register         */
0031 #define LINFBRR 0x0024  /* LIN fractional baud rate register        */
0032 #define LINIBRR 0x0028  /* LIN integer baud rate register       */
0033 #define LINCFR  0x002C  /* LIN checksum field register          */
0034 #define LINCR2  0x0030  /* LIN control register 2           */
0035 #define BIDR    0x0034  /* Buffer identifier register           */
0036 #define BDRL    0x0038  /* Buffer data register least significant   */
0037 #define BDRM    0x003C  /* Buffer data register most significant    */
0038 #define IFER    0x0040  /* Identifier filter enable register        */
0039 #define IFMI    0x0044  /* Identifier filter match index        */
0040 #define IFMR    0x0048  /* Identifier filter mode register      */
0041 #define GCR 0x004C  /* Global control register          */
0042 #define UARTPTO 0x0050  /* UART preset timeout register         */
0043 #define UARTCTO 0x0054  /* UART current timeout register        */
0044 
0045 /*
0046  * Register field definitions
0047  */
0048 
0049 #define LINFLEXD_LINCR1_INIT        BIT(0)
0050 #define LINFLEXD_LINCR1_MME     BIT(4)
0051 #define LINFLEXD_LINCR1_BF      BIT(7)
0052 
0053 #define LINFLEXD_LINSR_LINS_INITMODE    BIT(12)
0054 #define LINFLEXD_LINSR_LINS_MASK    (0xF << 12)
0055 
0056 #define LINFLEXD_LINIER_SZIE        BIT(15)
0057 #define LINFLEXD_LINIER_OCIE        BIT(14)
0058 #define LINFLEXD_LINIER_BEIE        BIT(13)
0059 #define LINFLEXD_LINIER_CEIE        BIT(12)
0060 #define LINFLEXD_LINIER_HEIE        BIT(11)
0061 #define LINFLEXD_LINIER_FEIE        BIT(8)
0062 #define LINFLEXD_LINIER_BOIE        BIT(7)
0063 #define LINFLEXD_LINIER_LSIE        BIT(6)
0064 #define LINFLEXD_LINIER_WUIE        BIT(5)
0065 #define LINFLEXD_LINIER_DBFIE       BIT(4)
0066 #define LINFLEXD_LINIER_DBEIETOIE   BIT(3)
0067 #define LINFLEXD_LINIER_DRIE        BIT(2)
0068 #define LINFLEXD_LINIER_DTIE        BIT(1)
0069 #define LINFLEXD_LINIER_HRIE        BIT(0)
0070 
0071 #define LINFLEXD_UARTCR_OSR_MASK    (0xF << 24)
0072 #define LINFLEXD_UARTCR_OSR(uartcr) (((uartcr) \
0073                     & LINFLEXD_UARTCR_OSR_MASK) >> 24)
0074 
0075 #define LINFLEXD_UARTCR_ROSE        BIT(23)
0076 
0077 #define LINFLEXD_UARTCR_RFBM        BIT(9)
0078 #define LINFLEXD_UARTCR_TFBM        BIT(8)
0079 #define LINFLEXD_UARTCR_WL1     BIT(7)
0080 #define LINFLEXD_UARTCR_PC1     BIT(6)
0081 
0082 #define LINFLEXD_UARTCR_RXEN        BIT(5)
0083 #define LINFLEXD_UARTCR_TXEN        BIT(4)
0084 #define LINFLEXD_UARTCR_PC0     BIT(3)
0085 
0086 #define LINFLEXD_UARTCR_PCE     BIT(2)
0087 #define LINFLEXD_UARTCR_WL0     BIT(1)
0088 #define LINFLEXD_UARTCR_UART        BIT(0)
0089 
0090 #define LINFLEXD_UARTSR_SZF     BIT(15)
0091 #define LINFLEXD_UARTSR_OCF     BIT(14)
0092 #define LINFLEXD_UARTSR_PE3     BIT(13)
0093 #define LINFLEXD_UARTSR_PE2     BIT(12)
0094 #define LINFLEXD_UARTSR_PE1     BIT(11)
0095 #define LINFLEXD_UARTSR_PE0     BIT(10)
0096 #define LINFLEXD_UARTSR_RMB     BIT(9)
0097 #define LINFLEXD_UARTSR_FEF     BIT(8)
0098 #define LINFLEXD_UARTSR_BOF     BIT(7)
0099 #define LINFLEXD_UARTSR_RPS     BIT(6)
0100 #define LINFLEXD_UARTSR_WUF     BIT(5)
0101 #define LINFLEXD_UARTSR_4       BIT(4)
0102 
0103 #define LINFLEXD_UARTSR_TO      BIT(3)
0104 
0105 #define LINFLEXD_UARTSR_DRFRFE      BIT(2)
0106 #define LINFLEXD_UARTSR_DTFTFF      BIT(1)
0107 #define LINFLEXD_UARTSR_NF      BIT(0)
0108 #define LINFLEXD_UARTSR_PE      (LINFLEXD_UARTSR_PE0 |\
0109                      LINFLEXD_UARTSR_PE1 |\
0110                      LINFLEXD_UARTSR_PE2 |\
0111                      LINFLEXD_UARTSR_PE3)
0112 
0113 #define LINFLEX_LDIV_MULTIPLIER     (16)
0114 
0115 #define DRIVER_NAME "fsl-linflexuart"
0116 #define DEV_NAME    "ttyLF"
0117 #define UART_NR     4
0118 
0119 #define EARLYCON_BUFFER_INITIAL_CAP 8
0120 
0121 #define PREINIT_DELAY           2000 /* us */
0122 
0123 static const struct of_device_id linflex_dt_ids[] = {
0124     {
0125         .compatible = "fsl,s32v234-linflexuart",
0126     },
0127     { /* sentinel */ }
0128 };
0129 MODULE_DEVICE_TABLE(of, linflex_dt_ids);
0130 
0131 #ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
0132 static struct uart_port *earlycon_port;
0133 static bool linflex_earlycon_same_instance;
0134 static DEFINE_SPINLOCK(init_lock);
0135 static bool during_init;
0136 
0137 static struct {
0138     char *content;
0139     unsigned int len, cap;
0140 } earlycon_buf;
0141 #endif
0142 
0143 static void linflex_stop_tx(struct uart_port *port)
0144 {
0145     unsigned long ier;
0146 
0147     ier = readl(port->membase + LINIER);
0148     ier &= ~(LINFLEXD_LINIER_DTIE);
0149     writel(ier, port->membase + LINIER);
0150 }
0151 
0152 static void linflex_stop_rx(struct uart_port *port)
0153 {
0154     unsigned long ier;
0155 
0156     ier = readl(port->membase + LINIER);
0157     writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER);
0158 }
0159 
0160 static void linflex_put_char(struct uart_port *sport, unsigned char c)
0161 {
0162     unsigned long status;
0163 
0164     writeb(c, sport->membase + BDRL);
0165 
0166     /* Waiting for data transmission completed. */
0167     while (((status = readl(sport->membase + UARTSR)) &
0168                 LINFLEXD_UARTSR_DTFTFF) !=
0169                 LINFLEXD_UARTSR_DTFTFF)
0170         ;
0171 
0172     writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR);
0173 }
0174 
0175 static inline void linflex_transmit_buffer(struct uart_port *sport)
0176 {
0177     struct circ_buf *xmit = &sport->state->xmit;
0178 
0179     while (!uart_circ_empty(xmit)) {
0180         linflex_put_char(sport, xmit->buf[xmit->tail]);
0181         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0182         sport->icount.tx++;
0183     }
0184 
0185     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0186         uart_write_wakeup(sport);
0187 
0188     if (uart_circ_empty(xmit))
0189         linflex_stop_tx(sport);
0190 }
0191 
0192 static void linflex_start_tx(struct uart_port *port)
0193 {
0194     unsigned long ier;
0195 
0196     linflex_transmit_buffer(port);
0197     ier = readl(port->membase + LINIER);
0198     writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER);
0199 }
0200 
0201 static irqreturn_t linflex_txint(int irq, void *dev_id)
0202 {
0203     struct uart_port *sport = dev_id;
0204     struct circ_buf *xmit = &sport->state->xmit;
0205     unsigned long flags;
0206 
0207     spin_lock_irqsave(&sport->lock, flags);
0208 
0209     if (sport->x_char) {
0210         linflex_put_char(sport, sport->x_char);
0211         goto out;
0212     }
0213 
0214     if (uart_circ_empty(xmit) || uart_tx_stopped(sport)) {
0215         linflex_stop_tx(sport);
0216         goto out;
0217     }
0218 
0219     linflex_transmit_buffer(sport);
0220 out:
0221     spin_unlock_irqrestore(&sport->lock, flags);
0222     return IRQ_HANDLED;
0223 }
0224 
0225 static irqreturn_t linflex_rxint(int irq, void *dev_id)
0226 {
0227     struct uart_port *sport = dev_id;
0228     unsigned int flg;
0229     struct tty_port *port = &sport->state->port;
0230     unsigned long flags, status;
0231     unsigned char rx;
0232     bool brk;
0233 
0234     spin_lock_irqsave(&sport->lock, flags);
0235 
0236     status = readl(sport->membase + UARTSR);
0237     while (status & LINFLEXD_UARTSR_RMB) {
0238         rx = readb(sport->membase + BDRM);
0239         brk = false;
0240         flg = TTY_NORMAL;
0241         sport->icount.rx++;
0242 
0243         if (status & (LINFLEXD_UARTSR_BOF | LINFLEXD_UARTSR_FEF |
0244                 LINFLEXD_UARTSR_PE)) {
0245             if (status & LINFLEXD_UARTSR_BOF)
0246                 sport->icount.overrun++;
0247             if (status & LINFLEXD_UARTSR_FEF) {
0248                 if (!rx) {
0249                     brk = true;
0250                     sport->icount.brk++;
0251                 } else
0252                     sport->icount.frame++;
0253             }
0254             if (status & LINFLEXD_UARTSR_PE)
0255                 sport->icount.parity++;
0256         }
0257 
0258         writel(status, sport->membase + UARTSR);
0259         status = readl(sport->membase + UARTSR);
0260 
0261         if (brk) {
0262             uart_handle_break(sport);
0263         } else {
0264             if (uart_handle_sysrq_char(sport, (unsigned char)rx))
0265                 continue;
0266             tty_insert_flip_char(port, rx, flg);
0267         }
0268     }
0269 
0270     spin_unlock_irqrestore(&sport->lock, flags);
0271 
0272     tty_flip_buffer_push(port);
0273 
0274     return IRQ_HANDLED;
0275 }
0276 
0277 static irqreturn_t linflex_int(int irq, void *dev_id)
0278 {
0279     struct uart_port *sport = dev_id;
0280     unsigned long status;
0281 
0282     status = readl(sport->membase + UARTSR);
0283 
0284     if (status & LINFLEXD_UARTSR_DRFRFE)
0285         linflex_rxint(irq, dev_id);
0286     if (status & LINFLEXD_UARTSR_DTFTFF)
0287         linflex_txint(irq, dev_id);
0288 
0289     return IRQ_HANDLED;
0290 }
0291 
0292 /* return TIOCSER_TEMT when transmitter is not busy */
0293 static unsigned int linflex_tx_empty(struct uart_port *port)
0294 {
0295     unsigned long status;
0296 
0297     status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF;
0298 
0299     return status ? TIOCSER_TEMT : 0;
0300 }
0301 
0302 static unsigned int linflex_get_mctrl(struct uart_port *port)
0303 {
0304     return 0;
0305 }
0306 
0307 static void linflex_set_mctrl(struct uart_port *port, unsigned int mctrl)
0308 {
0309 }
0310 
0311 static void linflex_break_ctl(struct uart_port *port, int break_state)
0312 {
0313 }
0314 
0315 static void linflex_setup_watermark(struct uart_port *sport)
0316 {
0317     unsigned long cr, ier, cr1;
0318 
0319     /* Disable transmission/reception */
0320     ier = readl(sport->membase + LINIER);
0321     ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
0322     writel(ier, sport->membase + LINIER);
0323 
0324     cr = readl(sport->membase + UARTCR);
0325     cr &= ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN);
0326     writel(cr, sport->membase + UARTCR);
0327 
0328     /* Enter initialization mode by setting INIT bit */
0329 
0330     /* set the Linflex in master mode and activate by-pass filter */
0331     cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME
0332           | LINFLEXD_LINCR1_INIT;
0333     writel(cr1, sport->membase + LINCR1);
0334 
0335     /* wait for init mode entry */
0336     while ((readl(sport->membase + LINSR)
0337         & LINFLEXD_LINSR_LINS_MASK)
0338         != LINFLEXD_LINSR_LINS_INITMODE)
0339         ;
0340 
0341     /*
0342      *  UART = 0x1;     - Linflex working in UART mode
0343      *  TXEN = 0x1;     - Enable transmission of data now
0344      *  RXEn = 0x1;     - Receiver enabled
0345      *  WL0 = 0x1;      - 8 bit data
0346      *  PCE = 0x0;      - No parity
0347      */
0348 
0349     /* set UART bit to allow writing other bits */
0350     writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR);
0351 
0352     cr = (LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN |
0353           LINFLEXD_UARTCR_WL0 | LINFLEXD_UARTCR_UART);
0354 
0355     writel(cr, sport->membase + UARTCR);
0356 
0357     cr1 &= ~(LINFLEXD_LINCR1_INIT);
0358 
0359     writel(cr1, sport->membase + LINCR1);
0360 
0361     ier = readl(sport->membase + LINIER);
0362     ier |= LINFLEXD_LINIER_DRIE;
0363     ier |= LINFLEXD_LINIER_DTIE;
0364 
0365     writel(ier, sport->membase + LINIER);
0366 }
0367 
0368 static int linflex_startup(struct uart_port *port)
0369 {
0370     int ret = 0;
0371     unsigned long flags;
0372 
0373     spin_lock_irqsave(&port->lock, flags);
0374 
0375     linflex_setup_watermark(port);
0376 
0377     spin_unlock_irqrestore(&port->lock, flags);
0378 
0379     ret = devm_request_irq(port->dev, port->irq, linflex_int, 0,
0380                    DRIVER_NAME, port);
0381 
0382     return ret;
0383 }
0384 
0385 static void linflex_shutdown(struct uart_port *port)
0386 {
0387     unsigned long ier;
0388     unsigned long flags;
0389 
0390     spin_lock_irqsave(&port->lock, flags);
0391 
0392     /* disable interrupts */
0393     ier = readl(port->membase + LINIER);
0394     ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
0395     writel(ier, port->membase + LINIER);
0396 
0397     spin_unlock_irqrestore(&port->lock, flags);
0398 
0399     devm_free_irq(port->dev, port->irq, port);
0400 }
0401 
0402 static void
0403 linflex_set_termios(struct uart_port *port, struct ktermios *termios,
0404             struct ktermios *old)
0405 {
0406     unsigned long flags;
0407     unsigned long cr, old_cr, cr1;
0408     unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
0409 
0410     cr = readl(port->membase + UARTCR);
0411     old_cr = cr;
0412 
0413     /* Enter initialization mode by setting INIT bit */
0414     cr1 = readl(port->membase + LINCR1);
0415     cr1 |= LINFLEXD_LINCR1_INIT;
0416     writel(cr1, port->membase + LINCR1);
0417 
0418     /* wait for init mode entry */
0419     while ((readl(port->membase + LINSR)
0420         & LINFLEXD_LINSR_LINS_MASK)
0421         != LINFLEXD_LINSR_LINS_INITMODE)
0422         ;
0423 
0424     /*
0425      * only support CS8 and CS7, and for CS7 must enable PE.
0426      * supported mode:
0427      *  - (7,e/o,1)
0428      *  - (8,n,1)
0429      *  - (8,e/o,1)
0430      */
0431     /* enter the UART into configuration mode */
0432 
0433     while ((termios->c_cflag & CSIZE) != CS8 &&
0434            (termios->c_cflag & CSIZE) != CS7) {
0435         termios->c_cflag &= ~CSIZE;
0436         termios->c_cflag |= old_csize;
0437         old_csize = CS8;
0438     }
0439 
0440     if ((termios->c_cflag & CSIZE) == CS7) {
0441         /* Word length: WL1WL0:00 */
0442         cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0;
0443     }
0444 
0445     if ((termios->c_cflag & CSIZE) == CS8) {
0446         /* Word length: WL1WL0:01 */
0447         cr = (old_cr | LINFLEXD_UARTCR_WL0) & ~LINFLEXD_UARTCR_WL1;
0448     }
0449 
0450     if (termios->c_cflag & CMSPAR) {
0451         if ((termios->c_cflag & CSIZE) != CS8) {
0452             termios->c_cflag &= ~CSIZE;
0453             termios->c_cflag |= CS8;
0454         }
0455         /* has a space/sticky bit */
0456         cr |= LINFLEXD_UARTCR_WL0;
0457     }
0458 
0459     if (termios->c_cflag & CSTOPB)
0460         termios->c_cflag &= ~CSTOPB;
0461 
0462     /* parity must be enabled when CS7 to match 8-bits format */
0463     if ((termios->c_cflag & CSIZE) == CS7)
0464         termios->c_cflag |= PARENB;
0465 
0466     if ((termios->c_cflag & PARENB)) {
0467         cr |= LINFLEXD_UARTCR_PCE;
0468         if (termios->c_cflag & PARODD)
0469             cr = (cr | LINFLEXD_UARTCR_PC0) &
0470                  (~LINFLEXD_UARTCR_PC1);
0471         else
0472             cr = cr & (~LINFLEXD_UARTCR_PC1 &
0473                    ~LINFLEXD_UARTCR_PC0);
0474     } else {
0475         cr &= ~LINFLEXD_UARTCR_PCE;
0476     }
0477 
0478     spin_lock_irqsave(&port->lock, flags);
0479 
0480     port->read_status_mask = 0;
0481 
0482     if (termios->c_iflag & INPCK)
0483         port->read_status_mask |=   (LINFLEXD_UARTSR_FEF |
0484                          LINFLEXD_UARTSR_PE0 |
0485                          LINFLEXD_UARTSR_PE1 |
0486                          LINFLEXD_UARTSR_PE2 |
0487                          LINFLEXD_UARTSR_PE3);
0488     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0489         port->read_status_mask |= LINFLEXD_UARTSR_FEF;
0490 
0491     /* characters to ignore */
0492     port->ignore_status_mask = 0;
0493     if (termios->c_iflag & IGNPAR)
0494         port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
0495     if (termios->c_iflag & IGNBRK) {
0496         port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
0497         /*
0498          * if we're ignoring parity and break indicators,
0499          * ignore overruns too (for real raw support).
0500          */
0501         if (termios->c_iflag & IGNPAR)
0502             port->ignore_status_mask |= LINFLEXD_UARTSR_BOF;
0503     }
0504 
0505     writel(cr, port->membase + UARTCR);
0506 
0507     cr1 &= ~(LINFLEXD_LINCR1_INIT);
0508 
0509     writel(cr1, port->membase + LINCR1);
0510 
0511     spin_unlock_irqrestore(&port->lock, flags);
0512 }
0513 
0514 static const char *linflex_type(struct uart_port *port)
0515 {
0516     return "FSL_LINFLEX";
0517 }
0518 
0519 static void linflex_release_port(struct uart_port *port)
0520 {
0521     /* nothing to do */
0522 }
0523 
0524 static int linflex_request_port(struct uart_port *port)
0525 {
0526     return 0;
0527 }
0528 
0529 /* configure/auto-configure the port */
0530 static void linflex_config_port(struct uart_port *port, int flags)
0531 {
0532     if (flags & UART_CONFIG_TYPE)
0533         port->type = PORT_LINFLEXUART;
0534 }
0535 
0536 static const struct uart_ops linflex_pops = {
0537     .tx_empty   = linflex_tx_empty,
0538     .set_mctrl  = linflex_set_mctrl,
0539     .get_mctrl  = linflex_get_mctrl,
0540     .stop_tx    = linflex_stop_tx,
0541     .start_tx   = linflex_start_tx,
0542     .stop_rx    = linflex_stop_rx,
0543     .break_ctl  = linflex_break_ctl,
0544     .startup    = linflex_startup,
0545     .shutdown   = linflex_shutdown,
0546     .set_termios    = linflex_set_termios,
0547     .type       = linflex_type,
0548     .request_port   = linflex_request_port,
0549     .release_port   = linflex_release_port,
0550     .config_port    = linflex_config_port,
0551 };
0552 
0553 static struct uart_port *linflex_ports[UART_NR];
0554 
0555 #ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
0556 static void linflex_console_putchar(struct uart_port *port, unsigned char ch)
0557 {
0558     unsigned long cr;
0559 
0560     cr = readl(port->membase + UARTCR);
0561 
0562     writeb(ch, port->membase + BDRL);
0563 
0564     if (!(cr & LINFLEXD_UARTCR_TFBM))
0565         while ((readl(port->membase + UARTSR) &
0566                     LINFLEXD_UARTSR_DTFTFF)
0567                 != LINFLEXD_UARTSR_DTFTFF)
0568             ;
0569     else
0570         while (readl(port->membase + UARTSR) &
0571                     LINFLEXD_UARTSR_DTFTFF)
0572             ;
0573 
0574     if (!(cr & LINFLEXD_UARTCR_TFBM)) {
0575         writel((readl(port->membase + UARTSR) |
0576                     LINFLEXD_UARTSR_DTFTFF),
0577                     port->membase + UARTSR);
0578     }
0579 }
0580 
0581 static void linflex_earlycon_putchar(struct uart_port *port, unsigned char ch)
0582 {
0583     unsigned long flags;
0584     char *ret;
0585 
0586     if (!linflex_earlycon_same_instance) {
0587         linflex_console_putchar(port, ch);
0588         return;
0589     }
0590 
0591     spin_lock_irqsave(&init_lock, flags);
0592     if (!during_init)
0593         goto outside_init;
0594 
0595     if (earlycon_buf.len >= 1 << CONFIG_LOG_BUF_SHIFT)
0596         goto init_release;
0597 
0598     if (!earlycon_buf.cap) {
0599         earlycon_buf.content = kmalloc(EARLYCON_BUFFER_INITIAL_CAP,
0600                            GFP_ATOMIC);
0601         earlycon_buf.cap = earlycon_buf.content ?
0602                    EARLYCON_BUFFER_INITIAL_CAP : 0;
0603     } else if (earlycon_buf.len == earlycon_buf.cap) {
0604         ret = krealloc(earlycon_buf.content, earlycon_buf.cap << 1,
0605                    GFP_ATOMIC);
0606         if (ret) {
0607             earlycon_buf.content = ret;
0608             earlycon_buf.cap <<= 1;
0609         }
0610     }
0611 
0612     if (earlycon_buf.len < earlycon_buf.cap)
0613         earlycon_buf.content[earlycon_buf.len++] = ch;
0614 
0615     goto init_release;
0616 
0617 outside_init:
0618     linflex_console_putchar(port, ch);
0619 init_release:
0620     spin_unlock_irqrestore(&init_lock, flags);
0621 }
0622 
0623 static void linflex_string_write(struct uart_port *sport, const char *s,
0624                  unsigned int count)
0625 {
0626     unsigned long cr, ier = 0;
0627 
0628     ier = readl(sport->membase + LINIER);
0629     linflex_stop_tx(sport);
0630 
0631     cr = readl(sport->membase + UARTCR);
0632     cr |= (LINFLEXD_UARTCR_TXEN);
0633     writel(cr, sport->membase + UARTCR);
0634 
0635     uart_console_write(sport, s, count, linflex_console_putchar);
0636 
0637     writel(ier, sport->membase + LINIER);
0638 }
0639 
0640 static void
0641 linflex_console_write(struct console *co, const char *s, unsigned int count)
0642 {
0643     struct uart_port *sport = linflex_ports[co->index];
0644     unsigned long flags;
0645     int locked = 1;
0646 
0647     if (sport->sysrq)
0648         locked = 0;
0649     else if (oops_in_progress)
0650         locked = spin_trylock_irqsave(&sport->lock, flags);
0651     else
0652         spin_lock_irqsave(&sport->lock, flags);
0653 
0654     linflex_string_write(sport, s, count);
0655 
0656     if (locked)
0657         spin_unlock_irqrestore(&sport->lock, flags);
0658 }
0659 
0660 /*
0661  * if the port was already initialised (eg, by a boot loader),
0662  * try to determine the current setup.
0663  */
0664 static void __init
0665 linflex_console_get_options(struct uart_port *sport, int *parity, int *bits)
0666 {
0667     unsigned long cr;
0668 
0669     cr = readl(sport->membase + UARTCR);
0670     cr &= LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN;
0671 
0672     if (!cr)
0673         return;
0674 
0675     /* ok, the port was enabled */
0676 
0677     *parity = 'n';
0678     if (cr & LINFLEXD_UARTCR_PCE) {
0679         if (cr & LINFLEXD_UARTCR_PC0)
0680             *parity = 'o';
0681         else
0682             *parity = 'e';
0683     }
0684 
0685     if ((cr & LINFLEXD_UARTCR_WL0) && ((cr & LINFLEXD_UARTCR_WL1) == 0)) {
0686         if (cr & LINFLEXD_UARTCR_PCE)
0687             *bits = 9;
0688         else
0689             *bits = 8;
0690     }
0691 }
0692 
0693 static int __init linflex_console_setup(struct console *co, char *options)
0694 {
0695     struct uart_port *sport;
0696     int baud = 115200;
0697     int bits = 8;
0698     int parity = 'n';
0699     int flow = 'n';
0700     int ret;
0701     int i;
0702     unsigned long flags;
0703     /*
0704      * check whether an invalid uart number has been specified, and
0705      * if so, search for the first available port that does have
0706      * console support.
0707      */
0708     if (co->index == -1 || co->index >= ARRAY_SIZE(linflex_ports))
0709         co->index = 0;
0710 
0711     sport = linflex_ports[co->index];
0712     if (!sport)
0713         return -ENODEV;
0714 
0715     if (options)
0716         uart_parse_options(options, &baud, &parity, &bits, &flow);
0717     else
0718         linflex_console_get_options(sport, &parity, &bits);
0719 
0720     if (earlycon_port && sport->mapbase == earlycon_port->mapbase) {
0721         linflex_earlycon_same_instance = true;
0722 
0723         spin_lock_irqsave(&init_lock, flags);
0724         during_init = true;
0725         spin_unlock_irqrestore(&init_lock, flags);
0726 
0727         /* Workaround for character loss or output of many invalid
0728          * characters, when INIT mode is entered shortly after a
0729          * character has just been printed.
0730          */
0731         udelay(PREINIT_DELAY);
0732     }
0733 
0734     linflex_setup_watermark(sport);
0735 
0736     ret = uart_set_options(sport, co, baud, parity, bits, flow);
0737 
0738     if (!linflex_earlycon_same_instance)
0739         goto done;
0740 
0741     spin_lock_irqsave(&init_lock, flags);
0742 
0743     /* Emptying buffer */
0744     if (earlycon_buf.len) {
0745         for (i = 0; i < earlycon_buf.len; i++)
0746             linflex_console_putchar(earlycon_port,
0747                 earlycon_buf.content[i]);
0748 
0749         kfree(earlycon_buf.content);
0750         earlycon_buf.len = 0;
0751     }
0752 
0753     during_init = false;
0754     spin_unlock_irqrestore(&init_lock, flags);
0755 
0756 done:
0757     return ret;
0758 }
0759 
0760 static struct uart_driver linflex_reg;
0761 static struct console linflex_console = {
0762     .name       = DEV_NAME,
0763     .write      = linflex_console_write,
0764     .device     = uart_console_device,
0765     .setup      = linflex_console_setup,
0766     .flags      = CON_PRINTBUFFER,
0767     .index      = -1,
0768     .data       = &linflex_reg,
0769 };
0770 
0771 static void linflex_earlycon_write(struct console *con, const char *s,
0772                    unsigned int n)
0773 {
0774     struct earlycon_device *dev = con->data;
0775 
0776     uart_console_write(&dev->port, s, n, linflex_earlycon_putchar);
0777 }
0778 
0779 static int __init linflex_early_console_setup(struct earlycon_device *device,
0780                           const char *options)
0781 {
0782     if (!device->port.membase)
0783         return -ENODEV;
0784 
0785     device->con->write = linflex_earlycon_write;
0786     earlycon_port = &device->port;
0787 
0788     return 0;
0789 }
0790 
0791 OF_EARLYCON_DECLARE(linflex, "fsl,s32v234-linflexuart",
0792             linflex_early_console_setup);
0793 
0794 #define LINFLEX_CONSOLE (&linflex_console)
0795 #else
0796 #define LINFLEX_CONSOLE NULL
0797 #endif
0798 
0799 static struct uart_driver linflex_reg = {
0800     .owner      = THIS_MODULE,
0801     .driver_name    = DRIVER_NAME,
0802     .dev_name   = DEV_NAME,
0803     .nr     = ARRAY_SIZE(linflex_ports),
0804     .cons       = LINFLEX_CONSOLE,
0805 };
0806 
0807 static int linflex_probe(struct platform_device *pdev)
0808 {
0809     struct device_node *np = pdev->dev.of_node;
0810     struct uart_port *sport;
0811     struct resource *res;
0812     int ret;
0813 
0814     sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
0815     if (!sport)
0816         return -ENOMEM;
0817 
0818     ret = of_alias_get_id(np, "serial");
0819     if (ret < 0) {
0820         dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
0821         return ret;
0822     }
0823     if (ret >= UART_NR) {
0824         dev_err(&pdev->dev, "driver limited to %d serial ports\n",
0825             UART_NR);
0826         return -ENOMEM;
0827     }
0828 
0829     sport->line = ret;
0830 
0831     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0832     if (!res)
0833         return -ENODEV;
0834 
0835     sport->mapbase = res->start;
0836     sport->membase = devm_ioremap_resource(&pdev->dev, res);
0837     if (IS_ERR(sport->membase))
0838         return PTR_ERR(sport->membase);
0839 
0840     sport->dev = &pdev->dev;
0841     sport->type = PORT_LINFLEXUART;
0842     sport->iotype = UPIO_MEM;
0843     sport->irq = platform_get_irq(pdev, 0);
0844     sport->ops = &linflex_pops;
0845     sport->flags = UPF_BOOT_AUTOCONF;
0846     sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE);
0847 
0848     linflex_ports[sport->line] = sport;
0849 
0850     platform_set_drvdata(pdev, sport);
0851 
0852     return uart_add_one_port(&linflex_reg, sport);
0853 }
0854 
0855 static int linflex_remove(struct platform_device *pdev)
0856 {
0857     struct uart_port *sport = platform_get_drvdata(pdev);
0858 
0859     uart_remove_one_port(&linflex_reg, sport);
0860 
0861     return 0;
0862 }
0863 
0864 #ifdef CONFIG_PM_SLEEP
0865 static int linflex_suspend(struct device *dev)
0866 {
0867     struct uart_port *sport = dev_get_drvdata(dev);
0868 
0869     uart_suspend_port(&linflex_reg, sport);
0870 
0871     return 0;
0872 }
0873 
0874 static int linflex_resume(struct device *dev)
0875 {
0876     struct uart_port *sport = dev_get_drvdata(dev);
0877 
0878     uart_resume_port(&linflex_reg, sport);
0879 
0880     return 0;
0881 }
0882 #endif
0883 
0884 static SIMPLE_DEV_PM_OPS(linflex_pm_ops, linflex_suspend, linflex_resume);
0885 
0886 static struct platform_driver linflex_driver = {
0887     .probe      = linflex_probe,
0888     .remove     = linflex_remove,
0889     .driver     = {
0890         .name   = DRIVER_NAME,
0891         .of_match_table = linflex_dt_ids,
0892         .pm = &linflex_pm_ops,
0893     },
0894 };
0895 
0896 static int __init linflex_serial_init(void)
0897 {
0898     int ret;
0899 
0900     ret = uart_register_driver(&linflex_reg);
0901     if (ret)
0902         return ret;
0903 
0904     ret = platform_driver_register(&linflex_driver);
0905     if (ret)
0906         uart_unregister_driver(&linflex_reg);
0907 
0908     return ret;
0909 }
0910 
0911 static void __exit linflex_serial_exit(void)
0912 {
0913     platform_driver_unregister(&linflex_driver);
0914     uart_unregister_driver(&linflex_reg);
0915 }
0916 
0917 module_init(linflex_serial_init);
0918 module_exit(linflex_serial_exit);
0919 
0920 MODULE_DESCRIPTION("Freescale LINFlexD serial port driver");
0921 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!