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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * dz.c: Serial port driver for DECstations equipped
0004  *       with the DZ chipset.
0005  *
0006  * Copyright (C) 1998 Olivier A. D. Lebaillif
0007  *
0008  * Email: olivier.lebaillif@ifrsys.com
0009  *
0010  * Copyright (C) 2004, 2006, 2007  Maciej W. Rozycki
0011  *
0012  * [31-AUG-98] triemer
0013  * Changed IRQ to use Harald's dec internals interrupts.h
0014  * removed base_addr code - moving address assignment to setup.c
0015  * Changed name of dz_init to rs_init to be consistent with tc code
0016  * [13-NOV-98] triemer fixed code to receive characters
0017  *    after patches by harald to irq code.
0018  * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout
0019  *            field from "current" - somewhere between 2.1.121 and 2.1.131
0020  Qua Jun 27 15:02:26 BRT 2001
0021  * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups
0022  *
0023  * Parts (C) 1999 David Airlie, airlied@linux.ie
0024  * [07-SEP-99] Bugfixes
0025  *
0026  * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk>
0027  * Converted to new serial core
0028  */
0029 
0030 #undef DEBUG_DZ
0031 
0032 #include <linux/bitops.h>
0033 #include <linux/compiler.h>
0034 #include <linux/console.h>
0035 #include <linux/delay.h>
0036 #include <linux/errno.h>
0037 #include <linux/init.h>
0038 #include <linux/interrupt.h>
0039 #include <linux/ioport.h>
0040 #include <linux/kernel.h>
0041 #include <linux/major.h>
0042 #include <linux/module.h>
0043 #include <linux/serial.h>
0044 #include <linux/serial_core.h>
0045 #include <linux/sysrq.h>
0046 #include <linux/tty.h>
0047 #include <linux/tty_flip.h>
0048 
0049 #include <linux/atomic.h>
0050 #include <linux/io.h>
0051 #include <asm/bootinfo.h>
0052 
0053 #include <asm/dec/interrupts.h>
0054 #include <asm/dec/kn01.h>
0055 #include <asm/dec/kn02.h>
0056 #include <asm/dec/machtype.h>
0057 #include <asm/dec/prom.h>
0058 #include <asm/dec/system.h>
0059 
0060 #include "dz.h"
0061 
0062 
0063 MODULE_DESCRIPTION("DECstation DZ serial driver");
0064 MODULE_LICENSE("GPL");
0065 
0066 
0067 static char dz_name[] __initdata = "DECstation DZ serial driver version ";
0068 static char dz_version[] __initdata = "1.04";
0069 
0070 struct dz_port {
0071     struct dz_mux       *mux;
0072     struct uart_port    port;
0073     unsigned int        cflag;
0074 };
0075 
0076 struct dz_mux {
0077     struct dz_port      dport[DZ_NB_PORT];
0078     atomic_t        map_guard;
0079     atomic_t        irq_guard;
0080     int         initialised;
0081 };
0082 
0083 static struct dz_mux dz_mux;
0084 
0085 static inline struct dz_port *to_dport(struct uart_port *uport)
0086 {
0087     return container_of(uport, struct dz_port, port);
0088 }
0089 
0090 /*
0091  * ------------------------------------------------------------
0092  * dz_in () and dz_out ()
0093  *
0094  * These routines are used to access the registers of the DZ
0095  * chip, hiding relocation differences between implementation.
0096  * ------------------------------------------------------------
0097  */
0098 
0099 static u16 dz_in(struct dz_port *dport, unsigned offset)
0100 {
0101     void __iomem *addr = dport->port.membase + offset;
0102 
0103     return readw(addr);
0104 }
0105 
0106 static void dz_out(struct dz_port *dport, unsigned offset, u16 value)
0107 {
0108     void __iomem *addr = dport->port.membase + offset;
0109 
0110     writew(value, addr);
0111 }
0112 
0113 /*
0114  * ------------------------------------------------------------
0115  * rs_stop () and rs_start ()
0116  *
0117  * These routines are called before setting or resetting
0118  * tty->flow.stopped. They enable or disable transmitter interrupts,
0119  * as necessary.
0120  * ------------------------------------------------------------
0121  */
0122 
0123 static void dz_stop_tx(struct uart_port *uport)
0124 {
0125     struct dz_port *dport = to_dport(uport);
0126     u16 tmp, mask = 1 << dport->port.line;
0127 
0128     tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
0129     tmp &= ~mask;           /* clear the TX flag */
0130     dz_out(dport, DZ_TCR, tmp);
0131 }
0132 
0133 static void dz_start_tx(struct uart_port *uport)
0134 {
0135     struct dz_port *dport = to_dport(uport);
0136     u16 tmp, mask = 1 << dport->port.line;
0137 
0138     tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
0139     tmp |= mask;            /* set the TX flag */
0140     dz_out(dport, DZ_TCR, tmp);
0141 }
0142 
0143 static void dz_stop_rx(struct uart_port *uport)
0144 {
0145     struct dz_port *dport = to_dport(uport);
0146 
0147     dport->cflag &= ~DZ_RXENAB;
0148     dz_out(dport, DZ_LPR, dport->cflag);
0149 }
0150 
0151 /*
0152  * ------------------------------------------------------------
0153  *
0154  * Here start the interrupt handling routines.  All of the following
0155  * subroutines are declared as inline and are folded into
0156  * dz_interrupt.  They were separated out for readability's sake.
0157  *
0158  * Note: dz_interrupt() is a "fast" interrupt, which means that it
0159  * runs with interrupts turned off.  People who may want to modify
0160  * dz_interrupt() should try to keep the interrupt handler as fast as
0161  * possible.  After you are done making modifications, it is not a bad
0162  * idea to do:
0163  *
0164  *  make drivers/serial/dz.s
0165  *
0166  * and look at the resulting assemble code in dz.s.
0167  *
0168  * ------------------------------------------------------------
0169  */
0170 
0171 /*
0172  * ------------------------------------------------------------
0173  * receive_char ()
0174  *
0175  * This routine deals with inputs from any lines.
0176  * ------------------------------------------------------------
0177  */
0178 static inline void dz_receive_chars(struct dz_mux *mux)
0179 {
0180     struct uart_port *uport;
0181     struct dz_port *dport = &mux->dport[0];
0182     struct uart_icount *icount;
0183     int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 };
0184     unsigned char ch, flag;
0185     u16 status;
0186     int i;
0187 
0188     while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) {
0189         dport = &mux->dport[LINE(status)];
0190         uport = &dport->port;
0191 
0192         ch = UCHAR(status);     /* grab the char */
0193         flag = TTY_NORMAL;
0194 
0195         icount = &uport->icount;
0196         icount->rx++;
0197 
0198         if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) {
0199 
0200             /*
0201              * There is no separate BREAK status bit, so treat
0202              * null characters with framing errors as BREAKs;
0203              * normally, otherwise.  For this move the Framing
0204              * Error bit to a simulated BREAK bit.
0205              */
0206             if (!ch) {
0207                 status |= (status & DZ_FERR) >>
0208                       (ffs(DZ_FERR) - ffs(DZ_BREAK));
0209                 status &= ~DZ_FERR;
0210             }
0211 
0212             /* Handle SysRq/SAK & keep track of the statistics. */
0213             if (status & DZ_BREAK) {
0214                 icount->brk++;
0215                 if (uart_handle_break(uport))
0216                     continue;
0217             } else if (status & DZ_FERR)
0218                 icount->frame++;
0219             else if (status & DZ_PERR)
0220                 icount->parity++;
0221             if (status & DZ_OERR)
0222                 icount->overrun++;
0223 
0224             status &= uport->read_status_mask;
0225             if (status & DZ_BREAK)
0226                 flag = TTY_BREAK;
0227             else if (status & DZ_FERR)
0228                 flag = TTY_FRAME;
0229             else if (status & DZ_PERR)
0230                 flag = TTY_PARITY;
0231 
0232         }
0233 
0234         if (uart_handle_sysrq_char(uport, ch))
0235             continue;
0236 
0237         uart_insert_char(uport, status, DZ_OERR, ch, flag);
0238         lines_rx[LINE(status)] = 1;
0239     }
0240     for (i = 0; i < DZ_NB_PORT; i++)
0241         if (lines_rx[i])
0242             tty_flip_buffer_push(&mux->dport[i].port.state->port);
0243 }
0244 
0245 /*
0246  * ------------------------------------------------------------
0247  * transmit_char ()
0248  *
0249  * This routine deals with outputs to any lines.
0250  * ------------------------------------------------------------
0251  */
0252 static inline void dz_transmit_chars(struct dz_mux *mux)
0253 {
0254     struct dz_port *dport = &mux->dport[0];
0255     struct circ_buf *xmit;
0256     unsigned char tmp;
0257     u16 status;
0258 
0259     status = dz_in(dport, DZ_CSR);
0260     dport = &mux->dport[LINE(status)];
0261     xmit = &dport->port.state->xmit;
0262 
0263     if (dport->port.x_char) {       /* XON/XOFF chars */
0264         dz_out(dport, DZ_TDR, dport->port.x_char);
0265         dport->port.icount.tx++;
0266         dport->port.x_char = 0;
0267         return;
0268     }
0269     /* If nothing to do or stopped or hardware stopped. */
0270     if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
0271         spin_lock(&dport->port.lock);
0272         dz_stop_tx(&dport->port);
0273         spin_unlock(&dport->port.lock);
0274         return;
0275     }
0276 
0277     /*
0278      * If something to do... (remember the dz has no output fifo,
0279      * so we go one char at a time) :-<
0280      */
0281     tmp = xmit->buf[xmit->tail];
0282     xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1);
0283     dz_out(dport, DZ_TDR, tmp);
0284     dport->port.icount.tx++;
0285 
0286     if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
0287         uart_write_wakeup(&dport->port);
0288 
0289     /* Are we are done. */
0290     if (uart_circ_empty(xmit)) {
0291         spin_lock(&dport->port.lock);
0292         dz_stop_tx(&dport->port);
0293         spin_unlock(&dport->port.lock);
0294     }
0295 }
0296 
0297 /*
0298  * ------------------------------------------------------------
0299  * check_modem_status()
0300  *
0301  * DS 3100 & 5100: Only valid for the MODEM line, duh!
0302  * DS 5000/200: Valid for the MODEM and PRINTER line.
0303  * ------------------------------------------------------------
0304  */
0305 static inline void check_modem_status(struct dz_port *dport)
0306 {
0307     /*
0308      * FIXME:
0309      * 1. No status change interrupt; use a timer.
0310      * 2. Handle the 3100/5000 as appropriate. --macro
0311      */
0312     u16 status;
0313 
0314     /* If not the modem line just return.  */
0315     if (dport->port.line != DZ_MODEM)
0316         return;
0317 
0318     status = dz_in(dport, DZ_MSR);
0319 
0320     /* it's easy, since DSR2 is the only bit in the register */
0321     if (status)
0322         dport->port.icount.dsr++;
0323 }
0324 
0325 /*
0326  * ------------------------------------------------------------
0327  * dz_interrupt ()
0328  *
0329  * this is the main interrupt routine for the DZ chip.
0330  * It deals with the multiple ports.
0331  * ------------------------------------------------------------
0332  */
0333 static irqreturn_t dz_interrupt(int irq, void *dev_id)
0334 {
0335     struct dz_mux *mux = dev_id;
0336     struct dz_port *dport = &mux->dport[0];
0337     u16 status;
0338 
0339     /* get the reason why we just got an irq */
0340     status = dz_in(dport, DZ_CSR);
0341 
0342     if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE))
0343         dz_receive_chars(mux);
0344 
0345     if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE))
0346         dz_transmit_chars(mux);
0347 
0348     return IRQ_HANDLED;
0349 }
0350 
0351 /*
0352  * -------------------------------------------------------------------
0353  * Here ends the DZ interrupt routines.
0354  * -------------------------------------------------------------------
0355  */
0356 
0357 static unsigned int dz_get_mctrl(struct uart_port *uport)
0358 {
0359     /*
0360      * FIXME: Handle the 3100/5000 as appropriate. --macro
0361      */
0362     struct dz_port *dport = to_dport(uport);
0363     unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
0364 
0365     if (dport->port.line == DZ_MODEM) {
0366         if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR)
0367             mctrl &= ~TIOCM_DSR;
0368     }
0369 
0370     return mctrl;
0371 }
0372 
0373 static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl)
0374 {
0375     /*
0376      * FIXME: Handle the 3100/5000 as appropriate. --macro
0377      */
0378     struct dz_port *dport = to_dport(uport);
0379     u16 tmp;
0380 
0381     if (dport->port.line == DZ_MODEM) {
0382         tmp = dz_in(dport, DZ_TCR);
0383         if (mctrl & TIOCM_DTR)
0384             tmp &= ~DZ_MODEM_DTR;
0385         else
0386             tmp |= DZ_MODEM_DTR;
0387         dz_out(dport, DZ_TCR, tmp);
0388     }
0389 }
0390 
0391 /*
0392  * -------------------------------------------------------------------
0393  * startup ()
0394  *
0395  * various initialization tasks
0396  * -------------------------------------------------------------------
0397  */
0398 static int dz_startup(struct uart_port *uport)
0399 {
0400     struct dz_port *dport = to_dport(uport);
0401     struct dz_mux *mux = dport->mux;
0402     unsigned long flags;
0403     int irq_guard;
0404     int ret;
0405     u16 tmp;
0406 
0407     irq_guard = atomic_add_return(1, &mux->irq_guard);
0408     if (irq_guard != 1)
0409         return 0;
0410 
0411     ret = request_irq(dport->port.irq, dz_interrupt,
0412               IRQF_SHARED, "dz", mux);
0413     if (ret) {
0414         atomic_add(-1, &mux->irq_guard);
0415         printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq);
0416         return ret;
0417     }
0418 
0419     spin_lock_irqsave(&dport->port.lock, flags);
0420 
0421     /* Enable interrupts.  */
0422     tmp = dz_in(dport, DZ_CSR);
0423     tmp |= DZ_RIE | DZ_TIE;
0424     dz_out(dport, DZ_CSR, tmp);
0425 
0426     spin_unlock_irqrestore(&dport->port.lock, flags);
0427 
0428     return 0;
0429 }
0430 
0431 /*
0432  * -------------------------------------------------------------------
0433  * shutdown ()
0434  *
0435  * This routine will shutdown a serial port; interrupts are disabled, and
0436  * DTR is dropped if the hangup on close termio flag is on.
0437  * -------------------------------------------------------------------
0438  */
0439 static void dz_shutdown(struct uart_port *uport)
0440 {
0441     struct dz_port *dport = to_dport(uport);
0442     struct dz_mux *mux = dport->mux;
0443     unsigned long flags;
0444     int irq_guard;
0445     u16 tmp;
0446 
0447     spin_lock_irqsave(&dport->port.lock, flags);
0448     dz_stop_tx(&dport->port);
0449     spin_unlock_irqrestore(&dport->port.lock, flags);
0450 
0451     irq_guard = atomic_add_return(-1, &mux->irq_guard);
0452     if (!irq_guard) {
0453         /* Disable interrupts.  */
0454         tmp = dz_in(dport, DZ_CSR);
0455         tmp &= ~(DZ_RIE | DZ_TIE);
0456         dz_out(dport, DZ_CSR, tmp);
0457 
0458         free_irq(dport->port.irq, mux);
0459     }
0460 }
0461 
0462 /*
0463  * -------------------------------------------------------------------
0464  * dz_tx_empty() -- get the transmitter empty status
0465  *
0466  * Purpose: Let user call ioctl() to get info when the UART physically
0467  *          is emptied.  On bus types like RS485, the transmitter must
0468  *          release the bus after transmitting. This must be done when
0469  *          the transmit shift register is empty, not be done when the
0470  *          transmit holding register is empty.  This functionality
0471  *          allows an RS485 driver to be written in user space.
0472  * -------------------------------------------------------------------
0473  */
0474 static unsigned int dz_tx_empty(struct uart_port *uport)
0475 {
0476     struct dz_port *dport = to_dport(uport);
0477     unsigned short tmp, mask = 1 << dport->port.line;
0478 
0479     tmp = dz_in(dport, DZ_TCR);
0480     tmp &= mask;
0481 
0482     return tmp ? 0 : TIOCSER_TEMT;
0483 }
0484 
0485 static void dz_break_ctl(struct uart_port *uport, int break_state)
0486 {
0487     /*
0488      * FIXME: Can't access BREAK bits in TDR easily;
0489      * reuse the code for polled TX. --macro
0490      */
0491     struct dz_port *dport = to_dport(uport);
0492     unsigned long flags;
0493     unsigned short tmp, mask = 1 << dport->port.line;
0494 
0495     spin_lock_irqsave(&uport->lock, flags);
0496     tmp = dz_in(dport, DZ_TCR);
0497     if (break_state)
0498         tmp |= mask;
0499     else
0500         tmp &= ~mask;
0501     dz_out(dport, DZ_TCR, tmp);
0502     spin_unlock_irqrestore(&uport->lock, flags);
0503 }
0504 
0505 static int dz_encode_baud_rate(unsigned int baud)
0506 {
0507     switch (baud) {
0508     case 50:
0509         return DZ_B50;
0510     case 75:
0511         return DZ_B75;
0512     case 110:
0513         return DZ_B110;
0514     case 134:
0515         return DZ_B134;
0516     case 150:
0517         return DZ_B150;
0518     case 300:
0519         return DZ_B300;
0520     case 600:
0521         return DZ_B600;
0522     case 1200:
0523         return DZ_B1200;
0524     case 1800:
0525         return DZ_B1800;
0526     case 2000:
0527         return DZ_B2000;
0528     case 2400:
0529         return DZ_B2400;
0530     case 3600:
0531         return DZ_B3600;
0532     case 4800:
0533         return DZ_B4800;
0534     case 7200:
0535         return DZ_B7200;
0536     case 9600:
0537         return DZ_B9600;
0538     default:
0539         return -1;
0540     }
0541 }
0542 
0543 
0544 static void dz_reset(struct dz_port *dport)
0545 {
0546     struct dz_mux *mux = dport->mux;
0547 
0548     if (mux->initialised)
0549         return;
0550 
0551     dz_out(dport, DZ_CSR, DZ_CLR);
0552     while (dz_in(dport, DZ_CSR) & DZ_CLR);
0553     iob();
0554 
0555     /* Enable scanning.  */
0556     dz_out(dport, DZ_CSR, DZ_MSE);
0557 
0558     mux->initialised = 1;
0559 }
0560 
0561 static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
0562                struct ktermios *old_termios)
0563 {
0564     struct dz_port *dport = to_dport(uport);
0565     unsigned long flags;
0566     unsigned int cflag, baud;
0567     int bflag;
0568 
0569     cflag = dport->port.line;
0570 
0571     switch (termios->c_cflag & CSIZE) {
0572     case CS5:
0573         cflag |= DZ_CS5;
0574         break;
0575     case CS6:
0576         cflag |= DZ_CS6;
0577         break;
0578     case CS7:
0579         cflag |= DZ_CS7;
0580         break;
0581     case CS8:
0582     default:
0583         cflag |= DZ_CS8;
0584     }
0585 
0586     if (termios->c_cflag & CSTOPB)
0587         cflag |= DZ_CSTOPB;
0588     if (termios->c_cflag & PARENB)
0589         cflag |= DZ_PARENB;
0590     if (termios->c_cflag & PARODD)
0591         cflag |= DZ_PARODD;
0592 
0593     baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600);
0594     bflag = dz_encode_baud_rate(baud);
0595     if (bflag < 0)  {           /* Try to keep unchanged.  */
0596         baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600);
0597         bflag = dz_encode_baud_rate(baud);
0598         if (bflag < 0)  {       /* Resort to 9600.  */
0599             baud = 9600;
0600             bflag = DZ_B9600;
0601         }
0602         tty_termios_encode_baud_rate(termios, baud, baud);
0603     }
0604     cflag |= bflag;
0605 
0606     if (termios->c_cflag & CREAD)
0607         cflag |= DZ_RXENAB;
0608 
0609     spin_lock_irqsave(&dport->port.lock, flags);
0610 
0611     uart_update_timeout(uport, termios->c_cflag, baud);
0612 
0613     dz_out(dport, DZ_LPR, cflag);
0614     dport->cflag = cflag;
0615 
0616     /* setup accept flag */
0617     dport->port.read_status_mask = DZ_OERR;
0618     if (termios->c_iflag & INPCK)
0619         dport->port.read_status_mask |= DZ_FERR | DZ_PERR;
0620     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0621         dport->port.read_status_mask |= DZ_BREAK;
0622 
0623     /* characters to ignore */
0624     uport->ignore_status_mask = 0;
0625     if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
0626         dport->port.ignore_status_mask |= DZ_OERR;
0627     if (termios->c_iflag & IGNPAR)
0628         dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR;
0629     if (termios->c_iflag & IGNBRK)
0630         dport->port.ignore_status_mask |= DZ_BREAK;
0631 
0632     spin_unlock_irqrestore(&dport->port.lock, flags);
0633 }
0634 
0635 /*
0636  * Hack alert!
0637  * Required solely so that the initial PROM-based console
0638  * works undisturbed in parallel with this one.
0639  */
0640 static void dz_pm(struct uart_port *uport, unsigned int state,
0641           unsigned int oldstate)
0642 {
0643     struct dz_port *dport = to_dport(uport);
0644     unsigned long flags;
0645 
0646     spin_lock_irqsave(&dport->port.lock, flags);
0647     if (state < 3)
0648         dz_start_tx(&dport->port);
0649     else
0650         dz_stop_tx(&dport->port);
0651     spin_unlock_irqrestore(&dport->port.lock, flags);
0652 }
0653 
0654 
0655 static const char *dz_type(struct uart_port *uport)
0656 {
0657     return "DZ";
0658 }
0659 
0660 static void dz_release_port(struct uart_port *uport)
0661 {
0662     struct dz_mux *mux = to_dport(uport)->mux;
0663     int map_guard;
0664 
0665     iounmap(uport->membase);
0666     uport->membase = NULL;
0667 
0668     map_guard = atomic_add_return(-1, &mux->map_guard);
0669     if (!map_guard)
0670         release_mem_region(uport->mapbase, dec_kn_slot_size);
0671 }
0672 
0673 static int dz_map_port(struct uart_port *uport)
0674 {
0675     if (!uport->membase)
0676         uport->membase = ioremap(uport->mapbase,
0677                          dec_kn_slot_size);
0678     if (!uport->membase) {
0679         printk(KERN_ERR "dz: Cannot map MMIO\n");
0680         return -ENOMEM;
0681     }
0682     return 0;
0683 }
0684 
0685 static int dz_request_port(struct uart_port *uport)
0686 {
0687     struct dz_mux *mux = to_dport(uport)->mux;
0688     int map_guard;
0689     int ret;
0690 
0691     map_guard = atomic_add_return(1, &mux->map_guard);
0692     if (map_guard == 1) {
0693         if (!request_mem_region(uport->mapbase, dec_kn_slot_size,
0694                     "dz")) {
0695             atomic_add(-1, &mux->map_guard);
0696             printk(KERN_ERR
0697                    "dz: Unable to reserve MMIO resource\n");
0698             return -EBUSY;
0699         }
0700     }
0701     ret = dz_map_port(uport);
0702     if (ret) {
0703         map_guard = atomic_add_return(-1, &mux->map_guard);
0704         if (!map_guard)
0705             release_mem_region(uport->mapbase, dec_kn_slot_size);
0706         return ret;
0707     }
0708     return 0;
0709 }
0710 
0711 static void dz_config_port(struct uart_port *uport, int flags)
0712 {
0713     struct dz_port *dport = to_dport(uport);
0714 
0715     if (flags & UART_CONFIG_TYPE) {
0716         if (dz_request_port(uport))
0717             return;
0718 
0719         uport->type = PORT_DZ;
0720 
0721         dz_reset(dport);
0722     }
0723 }
0724 
0725 /*
0726  * Verify the new serial_struct (for TIOCSSERIAL).
0727  */
0728 static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser)
0729 {
0730     int ret = 0;
0731 
0732     if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ)
0733         ret = -EINVAL;
0734     if (ser->irq != uport->irq)
0735         ret = -EINVAL;
0736     return ret;
0737 }
0738 
0739 static const struct uart_ops dz_ops = {
0740     .tx_empty   = dz_tx_empty,
0741     .get_mctrl  = dz_get_mctrl,
0742     .set_mctrl  = dz_set_mctrl,
0743     .stop_tx    = dz_stop_tx,
0744     .start_tx   = dz_start_tx,
0745     .stop_rx    = dz_stop_rx,
0746     .break_ctl  = dz_break_ctl,
0747     .startup    = dz_startup,
0748     .shutdown   = dz_shutdown,
0749     .set_termios    = dz_set_termios,
0750     .pm     = dz_pm,
0751     .type       = dz_type,
0752     .release_port   = dz_release_port,
0753     .request_port   = dz_request_port,
0754     .config_port    = dz_config_port,
0755     .verify_port    = dz_verify_port,
0756 };
0757 
0758 static void __init dz_init_ports(void)
0759 {
0760     static int first = 1;
0761     unsigned long base;
0762     int line;
0763 
0764     if (!first)
0765         return;
0766     first = 0;
0767 
0768     if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100)
0769         base = dec_kn_slot_base + KN01_DZ11;
0770     else
0771         base = dec_kn_slot_base + KN02_DZ11;
0772 
0773     for (line = 0; line < DZ_NB_PORT; line++) {
0774         struct dz_port *dport = &dz_mux.dport[line];
0775         struct uart_port *uport = &dport->port;
0776 
0777         dport->mux  = &dz_mux;
0778 
0779         uport->irq  = dec_interrupt[DEC_IRQ_DZ11];
0780         uport->fifosize = 1;
0781         uport->iotype   = UPIO_MEM;
0782         uport->flags    = UPF_BOOT_AUTOCONF;
0783         uport->ops  = &dz_ops;
0784         uport->line = line;
0785         uport->mapbase  = base;
0786         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_DZ_CONSOLE);
0787     }
0788 }
0789 
0790 #ifdef CONFIG_SERIAL_DZ_CONSOLE
0791 /*
0792  * -------------------------------------------------------------------
0793  * dz_console_putchar() -- transmit a character
0794  *
0795  * Polled transmission.  This is tricky.  We need to mask transmit
0796  * interrupts so that they do not interfere, enable the transmitter
0797  * for the line requested and then wait till the transmit scanner
0798  * requests data for this line.  But it may request data for another
0799  * line first, in which case we have to disable its transmitter and
0800  * repeat waiting till our line pops up.  Only then the character may
0801  * be transmitted.  Finally, the state of the transmitter mask is
0802  * restored.  Welcome to the world of PDP-11!
0803  * -------------------------------------------------------------------
0804  */
0805 static void dz_console_putchar(struct uart_port *uport, unsigned char ch)
0806 {
0807     struct dz_port *dport = to_dport(uport);
0808     unsigned long flags;
0809     unsigned short csr, tcr, trdy, mask;
0810     int loops = 10000;
0811 
0812     spin_lock_irqsave(&dport->port.lock, flags);
0813     csr = dz_in(dport, DZ_CSR);
0814     dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
0815     tcr = dz_in(dport, DZ_TCR);
0816     tcr |= 1 << dport->port.line;
0817     mask = tcr;
0818     dz_out(dport, DZ_TCR, mask);
0819     iob();
0820     spin_unlock_irqrestore(&dport->port.lock, flags);
0821 
0822     do {
0823         trdy = dz_in(dport, DZ_CSR);
0824         if (!(trdy & DZ_TRDY))
0825             continue;
0826         trdy = (trdy & DZ_TLINE) >> 8;
0827         if (trdy == dport->port.line)
0828             break;
0829         mask &= ~(1 << trdy);
0830         dz_out(dport, DZ_TCR, mask);
0831         iob();
0832         udelay(2);
0833     } while (--loops);
0834 
0835     if (loops)              /* Cannot send otherwise. */
0836         dz_out(dport, DZ_TDR, ch);
0837 
0838     dz_out(dport, DZ_TCR, tcr);
0839     dz_out(dport, DZ_CSR, csr);
0840 }
0841 
0842 /*
0843  * -------------------------------------------------------------------
0844  * dz_console_print ()
0845  *
0846  * dz_console_print is registered for printk.
0847  * The console must be locked when we get here.
0848  * -------------------------------------------------------------------
0849  */
0850 static void dz_console_print(struct console *co,
0851                  const char *str,
0852                  unsigned int count)
0853 {
0854     struct dz_port *dport = &dz_mux.dport[co->index];
0855 #ifdef DEBUG_DZ
0856     prom_printf((char *) str);
0857 #endif
0858     uart_console_write(&dport->port, str, count, dz_console_putchar);
0859 }
0860 
0861 static int __init dz_console_setup(struct console *co, char *options)
0862 {
0863     struct dz_port *dport = &dz_mux.dport[co->index];
0864     struct uart_port *uport = &dport->port;
0865     int baud = 9600;
0866     int bits = 8;
0867     int parity = 'n';
0868     int flow = 'n';
0869     int ret;
0870 
0871     ret = dz_map_port(uport);
0872     if (ret)
0873         return ret;
0874 
0875     spin_lock_init(&dport->port.lock);  /* For dz_pm().  */
0876 
0877     dz_reset(dport);
0878     dz_pm(uport, 0, -1);
0879 
0880     if (options)
0881         uart_parse_options(options, &baud, &parity, &bits, &flow);
0882 
0883     return uart_set_options(&dport->port, co, baud, parity, bits, flow);
0884 }
0885 
0886 static struct uart_driver dz_reg;
0887 static struct console dz_console = {
0888     .name   = "ttyS",
0889     .write  = dz_console_print,
0890     .device = uart_console_device,
0891     .setup  = dz_console_setup,
0892     .flags  = CON_PRINTBUFFER,
0893     .index  = -1,
0894     .data   = &dz_reg,
0895 };
0896 
0897 static int __init dz_serial_console_init(void)
0898 {
0899     if (!IOASIC) {
0900         dz_init_ports();
0901         register_console(&dz_console);
0902         return 0;
0903     } else
0904         return -ENXIO;
0905 }
0906 
0907 console_initcall(dz_serial_console_init);
0908 
0909 #define SERIAL_DZ_CONSOLE   &dz_console
0910 #else
0911 #define SERIAL_DZ_CONSOLE   NULL
0912 #endif /* CONFIG_SERIAL_DZ_CONSOLE */
0913 
0914 static struct uart_driver dz_reg = {
0915     .owner          = THIS_MODULE,
0916     .driver_name        = "serial",
0917     .dev_name       = "ttyS",
0918     .major          = TTY_MAJOR,
0919     .minor          = 64,
0920     .nr         = DZ_NB_PORT,
0921     .cons           = SERIAL_DZ_CONSOLE,
0922 };
0923 
0924 static int __init dz_init(void)
0925 {
0926     int ret, i;
0927 
0928     if (IOASIC)
0929         return -ENXIO;
0930 
0931     printk("%s%s\n", dz_name, dz_version);
0932 
0933     dz_init_ports();
0934 
0935     ret = uart_register_driver(&dz_reg);
0936     if (ret)
0937         return ret;
0938 
0939     for (i = 0; i < DZ_NB_PORT; i++)
0940         uart_add_one_port(&dz_reg, &dz_mux.dport[i].port);
0941 
0942     return 0;
0943 }
0944 
0945 module_init(dz_init);
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