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0010 #include <linux/module.h>
0011 #include <linux/console.h>
0012 #include <linux/serial_core.h>
0013 #include <linux/serial.h>
0014 #include <linux/clk.h>
0015 #include <linux/io.h>
0016 #include <linux/tty.h>
0017 #include <linux/tty_flip.h>
0018 #include <linux/of.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/workqueue.h>
0021
0022 #define UA_ENABLE 0x00
0023 #define UA_ENABLE_ENABLE BIT(0)
0024
0025 #define UA_CONTROL 0x01
0026 #define UA_CONTROL_RX_ENABLE BIT(0)
0027 #define UA_CONTROL_TX_ENABLE BIT(1)
0028 #define UA_CONTROL_SOFT_RESET BIT(2)
0029
0030 #define UA_STATUS 0x02
0031 #define UA_STATUS_PARITY_ERR BIT(0)
0032 #define UA_STATUS_FRAME_ERR BIT(1)
0033 #define UA_STATUS_OVERRUN_ERR BIT(2)
0034 #define UA_STATUS_TX_READY BIT(6)
0035
0036 #define UA_CONFIG 0x03
0037 #define UA_CONFIG_CHAR_LEN BIT(0)
0038 #define UA_CONFIG_STOP_BITS BIT(1)
0039 #define UA_CONFIG_PARITY BIT(2)
0040 #define UA_CONFIG_ODD_PARITY BIT(4)
0041
0042 #define UA_EMI_REC 0x04
0043
0044 #define UA_HBAUD_LO 0x08
0045 #define UA_HBAUD_HI 0x09
0046
0047 #define UA_STATUS_FIFO 0x0a
0048 #define UA_STATUS_FIFO_RX_EMPTY BIT(2)
0049 #define UA_STATUS_FIFO_RX_INT_ALMOST BIT(3)
0050 #define UA_STATUS_FIFO_TX_FULL BIT(4)
0051 #define UA_STATUS_FIFO_TX_INT_ALMOST BIT(7)
0052
0053 #define UA_CONFIG_FIFO 0x0b
0054 #define UA_CONFIG_FIFO_RX_THRESH 7
0055 #define UA_CONFIG_FIFO_RX_FIFO_MODE BIT(3)
0056 #define UA_CONFIG_FIFO_TX_FIFO_MODE BIT(7)
0057
0058 #define UA_INTFLAG_CLEAR 0x1c
0059 #define UA_INTFLAG_SET 0x1d
0060 #define UA_INT_ENABLE 0x1e
0061 #define UA_INT_STATUS 0x1f
0062
0063 #define UA_INT_TX BIT(0)
0064 #define UA_INT_RX BIT(1)
0065
0066 #define DIGICOLOR_USART_NR 3
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076 struct digicolor_port {
0077 struct uart_port port;
0078 struct delayed_work rx_poll_work;
0079 };
0080
0081 static struct uart_port *digicolor_ports[DIGICOLOR_USART_NR];
0082
0083 static bool digicolor_uart_tx_full(struct uart_port *port)
0084 {
0085 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
0086 UA_STATUS_FIFO_TX_FULL);
0087 }
0088
0089 static bool digicolor_uart_rx_empty(struct uart_port *port)
0090 {
0091 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
0092 UA_STATUS_FIFO_RX_EMPTY);
0093 }
0094
0095 static void digicolor_uart_stop_tx(struct uart_port *port)
0096 {
0097 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
0098
0099 int_enable &= ~UA_INT_TX;
0100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
0101 }
0102
0103 static void digicolor_uart_start_tx(struct uart_port *port)
0104 {
0105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
0106
0107 int_enable |= UA_INT_TX;
0108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
0109 }
0110
0111 static void digicolor_uart_stop_rx(struct uart_port *port)
0112 {
0113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
0114
0115 int_enable &= ~UA_INT_RX;
0116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
0117 }
0118
0119 static void digicolor_rx_poll(struct work_struct *work)
0120 {
0121 struct digicolor_port *dp =
0122 container_of(to_delayed_work(work),
0123 struct digicolor_port, rx_poll_work);
0124
0125 if (!digicolor_uart_rx_empty(&dp->port))
0126
0127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET);
0128
0129 schedule_delayed_work(&dp->rx_poll_work, msecs_to_jiffies(100));
0130 }
0131
0132 static void digicolor_uart_rx(struct uart_port *port)
0133 {
0134 unsigned long flags;
0135
0136 spin_lock_irqsave(&port->lock, flags);
0137
0138 while (1) {
0139 u8 status, ch;
0140 unsigned int ch_flag;
0141
0142 if (digicolor_uart_rx_empty(port))
0143 break;
0144
0145 ch = readb_relaxed(port->membase + UA_EMI_REC);
0146 status = readb_relaxed(port->membase + UA_STATUS);
0147
0148 port->icount.rx++;
0149 ch_flag = TTY_NORMAL;
0150
0151 if (status) {
0152 if (status & UA_STATUS_PARITY_ERR)
0153 port->icount.parity++;
0154 else if (status & UA_STATUS_FRAME_ERR)
0155 port->icount.frame++;
0156 else if (status & UA_STATUS_OVERRUN_ERR)
0157 port->icount.overrun++;
0158
0159 status &= port->read_status_mask;
0160
0161 if (status & UA_STATUS_PARITY_ERR)
0162 ch_flag = TTY_PARITY;
0163 else if (status & UA_STATUS_FRAME_ERR)
0164 ch_flag = TTY_FRAME;
0165 else if (status & UA_STATUS_OVERRUN_ERR)
0166 ch_flag = TTY_OVERRUN;
0167 }
0168
0169 if (status & port->ignore_status_mask)
0170 continue;
0171
0172 uart_insert_char(port, status, UA_STATUS_OVERRUN_ERR, ch,
0173 ch_flag);
0174 }
0175
0176 spin_unlock_irqrestore(&port->lock, flags);
0177
0178 tty_flip_buffer_push(&port->state->port);
0179 }
0180
0181 static void digicolor_uart_tx(struct uart_port *port)
0182 {
0183 struct circ_buf *xmit = &port->state->xmit;
0184 unsigned long flags;
0185
0186 if (digicolor_uart_tx_full(port))
0187 return;
0188
0189 spin_lock_irqsave(&port->lock, flags);
0190
0191 if (port->x_char) {
0192 writeb_relaxed(port->x_char, port->membase + UA_EMI_REC);
0193 port->icount.tx++;
0194 port->x_char = 0;
0195 goto out;
0196 }
0197
0198 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0199 digicolor_uart_stop_tx(port);
0200 goto out;
0201 }
0202
0203 while (!uart_circ_empty(xmit)) {
0204 writeb(xmit->buf[xmit->tail], port->membase + UA_EMI_REC);
0205 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0206 port->icount.tx++;
0207
0208 if (digicolor_uart_tx_full(port))
0209 break;
0210 }
0211
0212 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0213 uart_write_wakeup(port);
0214
0215 out:
0216 spin_unlock_irqrestore(&port->lock, flags);
0217 }
0218
0219 static irqreturn_t digicolor_uart_int(int irq, void *dev_id)
0220 {
0221 struct uart_port *port = dev_id;
0222 u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS);
0223
0224 writeb_relaxed(UA_INT_RX | UA_INT_TX,
0225 port->membase + UA_INTFLAG_CLEAR);
0226
0227 if (int_status & UA_INT_RX)
0228 digicolor_uart_rx(port);
0229 if (int_status & UA_INT_TX)
0230 digicolor_uart_tx(port);
0231
0232 return IRQ_HANDLED;
0233 }
0234
0235 static unsigned int digicolor_uart_tx_empty(struct uart_port *port)
0236 {
0237 u8 status = readb_relaxed(port->membase + UA_STATUS);
0238
0239 return (status & UA_STATUS_TX_READY) ? TIOCSER_TEMT : 0;
0240 }
0241
0242 static unsigned int digicolor_uart_get_mctrl(struct uart_port *port)
0243 {
0244 return TIOCM_CTS;
0245 }
0246
0247 static void digicolor_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0248 {
0249 }
0250
0251 static void digicolor_uart_break_ctl(struct uart_port *port, int state)
0252 {
0253 }
0254
0255 static int digicolor_uart_startup(struct uart_port *port)
0256 {
0257 struct digicolor_port *dp =
0258 container_of(port, struct digicolor_port, port);
0259
0260 writeb_relaxed(UA_ENABLE_ENABLE, port->membase + UA_ENABLE);
0261 writeb_relaxed(UA_CONTROL_SOFT_RESET, port->membase + UA_CONTROL);
0262 writeb_relaxed(0, port->membase + UA_CONTROL);
0263
0264 writeb_relaxed(UA_CONFIG_FIFO_RX_FIFO_MODE
0265 | UA_CONFIG_FIFO_TX_FIFO_MODE | UA_CONFIG_FIFO_RX_THRESH,
0266 port->membase + UA_CONFIG_FIFO);
0267 writeb_relaxed(UA_STATUS_FIFO_RX_INT_ALMOST,
0268 port->membase + UA_STATUS_FIFO);
0269 writeb_relaxed(UA_CONTROL_RX_ENABLE | UA_CONTROL_TX_ENABLE,
0270 port->membase + UA_CONTROL);
0271 writeb_relaxed(UA_INT_TX | UA_INT_RX,
0272 port->membase + UA_INT_ENABLE);
0273
0274 schedule_delayed_work(&dp->rx_poll_work, msecs_to_jiffies(100));
0275
0276 return 0;
0277 }
0278
0279 static void digicolor_uart_shutdown(struct uart_port *port)
0280 {
0281 struct digicolor_port *dp =
0282 container_of(port, struct digicolor_port, port);
0283
0284 writeb_relaxed(0, port->membase + UA_ENABLE);
0285 cancel_delayed_work_sync(&dp->rx_poll_work);
0286 }
0287
0288 static void digicolor_uart_set_termios(struct uart_port *port,
0289 struct ktermios *termios,
0290 struct ktermios *old)
0291 {
0292 unsigned int baud, divisor;
0293 u8 config = 0;
0294 unsigned long flags;
0295
0296
0297 termios->c_cflag &= ~CMSPAR;
0298 termios->c_iflag &= ~(BRKINT | IGNBRK);
0299
0300
0301 baud = uart_get_baud_rate(port, termios, old,
0302 port->uartclk / (0x10000*16),
0303 port->uartclk / 256);
0304 divisor = uart_get_divisor(port, baud) - 1;
0305
0306 switch (termios->c_cflag & CSIZE) {
0307 case CS7:
0308 break;
0309 case CS8:
0310 default:
0311 config |= UA_CONFIG_CHAR_LEN;
0312 termios->c_cflag &= ~CSIZE;
0313 termios->c_cflag |= CS8;
0314 break;
0315 }
0316
0317 if (termios->c_cflag & CSTOPB)
0318 config |= UA_CONFIG_STOP_BITS;
0319
0320 if (termios->c_cflag & PARENB) {
0321 config |= UA_CONFIG_PARITY;
0322 if (termios->c_cflag & PARODD)
0323 config |= UA_CONFIG_ODD_PARITY;
0324 }
0325
0326
0327 port->read_status_mask = UA_STATUS_OVERRUN_ERR;
0328 if (termios->c_iflag & INPCK)
0329 port->read_status_mask |= UA_STATUS_PARITY_ERR
0330 | UA_STATUS_FRAME_ERR;
0331
0332
0333 port->ignore_status_mask = 0;
0334 if (!(termios->c_cflag & CREAD))
0335 port->ignore_status_mask |= UA_STATUS_OVERRUN_ERR
0336 | UA_STATUS_PARITY_ERR | UA_STATUS_FRAME_ERR;
0337
0338 spin_lock_irqsave(&port->lock, flags);
0339
0340 uart_update_timeout(port, termios->c_cflag, baud);
0341
0342 writeb_relaxed(config, port->membase + UA_CONFIG);
0343 writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO);
0344 writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI);
0345
0346 spin_unlock_irqrestore(&port->lock, flags);
0347 }
0348
0349 static const char *digicolor_uart_type(struct uart_port *port)
0350 {
0351 return (port->type == PORT_DIGICOLOR) ? "DIGICOLOR USART" : NULL;
0352 }
0353
0354 static void digicolor_uart_config_port(struct uart_port *port, int flags)
0355 {
0356 if (flags & UART_CONFIG_TYPE)
0357 port->type = PORT_DIGICOLOR;
0358 }
0359
0360 static void digicolor_uart_release_port(struct uart_port *port)
0361 {
0362 }
0363
0364 static int digicolor_uart_request_port(struct uart_port *port)
0365 {
0366 return 0;
0367 }
0368
0369 static const struct uart_ops digicolor_uart_ops = {
0370 .tx_empty = digicolor_uart_tx_empty,
0371 .set_mctrl = digicolor_uart_set_mctrl,
0372 .get_mctrl = digicolor_uart_get_mctrl,
0373 .stop_tx = digicolor_uart_stop_tx,
0374 .start_tx = digicolor_uart_start_tx,
0375 .stop_rx = digicolor_uart_stop_rx,
0376 .break_ctl = digicolor_uart_break_ctl,
0377 .startup = digicolor_uart_startup,
0378 .shutdown = digicolor_uart_shutdown,
0379 .set_termios = digicolor_uart_set_termios,
0380 .type = digicolor_uart_type,
0381 .config_port = digicolor_uart_config_port,
0382 .release_port = digicolor_uart_release_port,
0383 .request_port = digicolor_uart_request_port,
0384 };
0385
0386 static void digicolor_uart_console_putchar(struct uart_port *port, unsigned char ch)
0387 {
0388 while (digicolor_uart_tx_full(port))
0389 cpu_relax();
0390
0391 writeb_relaxed(ch, port->membase + UA_EMI_REC);
0392 }
0393
0394 static void digicolor_uart_console_write(struct console *co, const char *c,
0395 unsigned n)
0396 {
0397 struct uart_port *port = digicolor_ports[co->index];
0398 u8 status;
0399 unsigned long flags;
0400 int locked = 1;
0401
0402 if (oops_in_progress)
0403 locked = spin_trylock_irqsave(&port->lock, flags);
0404 else
0405 spin_lock_irqsave(&port->lock, flags);
0406
0407 uart_console_write(port, c, n, digicolor_uart_console_putchar);
0408
0409 if (locked)
0410 spin_unlock_irqrestore(&port->lock, flags);
0411
0412
0413 do {
0414 status = readb_relaxed(port->membase + UA_STATUS);
0415 } while ((status & UA_STATUS_TX_READY) == 0);
0416 }
0417
0418 static int digicolor_uart_console_setup(struct console *co, char *options)
0419 {
0420 int baud = 115200, bits = 8, parity = 'n', flow = 'n';
0421 struct uart_port *port;
0422
0423 if (co->index < 0 || co->index >= DIGICOLOR_USART_NR)
0424 return -EINVAL;
0425
0426 port = digicolor_ports[co->index];
0427 if (!port)
0428 return -ENODEV;
0429
0430 if (options)
0431 uart_parse_options(options, &baud, &parity, &bits, &flow);
0432
0433 return uart_set_options(port, co, baud, parity, bits, flow);
0434 }
0435
0436 static struct console digicolor_console = {
0437 .name = "ttyS",
0438 .device = uart_console_device,
0439 .write = digicolor_uart_console_write,
0440 .setup = digicolor_uart_console_setup,
0441 .flags = CON_PRINTBUFFER,
0442 .index = -1,
0443 };
0444
0445 static struct uart_driver digicolor_uart = {
0446 .driver_name = "digicolor-usart",
0447 .dev_name = "ttyS",
0448 .nr = DIGICOLOR_USART_NR,
0449 };
0450
0451 static int digicolor_uart_probe(struct platform_device *pdev)
0452 {
0453 struct device_node *np = pdev->dev.of_node;
0454 int irq, ret, index;
0455 struct digicolor_port *dp;
0456 struct resource *res;
0457 struct clk *uart_clk;
0458
0459 if (!np) {
0460 dev_err(&pdev->dev, "Missing device tree node\n");
0461 return -ENXIO;
0462 }
0463
0464 index = of_alias_get_id(np, "serial");
0465 if (index < 0 || index >= DIGICOLOR_USART_NR)
0466 return -EINVAL;
0467
0468 dp = devm_kzalloc(&pdev->dev, sizeof(*dp), GFP_KERNEL);
0469 if (!dp)
0470 return -ENOMEM;
0471
0472 uart_clk = devm_clk_get(&pdev->dev, NULL);
0473 if (IS_ERR(uart_clk))
0474 return PTR_ERR(uart_clk);
0475
0476 dp->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0477 if (IS_ERR(dp->port.membase))
0478 return PTR_ERR(dp->port.membase);
0479 dp->port.mapbase = res->start;
0480
0481 irq = platform_get_irq(pdev, 0);
0482 if (irq < 0)
0483 return irq;
0484 dp->port.irq = irq;
0485
0486 dp->port.iotype = UPIO_MEM;
0487 dp->port.uartclk = clk_get_rate(uart_clk);
0488 dp->port.fifosize = 16;
0489 dp->port.dev = &pdev->dev;
0490 dp->port.ops = &digicolor_uart_ops;
0491 dp->port.line = index;
0492 dp->port.type = PORT_DIGICOLOR;
0493 spin_lock_init(&dp->port.lock);
0494
0495 digicolor_ports[index] = &dp->port;
0496 platform_set_drvdata(pdev, &dp->port);
0497
0498 INIT_DELAYED_WORK(&dp->rx_poll_work, digicolor_rx_poll);
0499
0500 ret = devm_request_irq(&pdev->dev, dp->port.irq, digicolor_uart_int, 0,
0501 dev_name(&pdev->dev), &dp->port);
0502 if (ret)
0503 return ret;
0504
0505 return uart_add_one_port(&digicolor_uart, &dp->port);
0506 }
0507
0508 static int digicolor_uart_remove(struct platform_device *pdev)
0509 {
0510 struct uart_port *port = platform_get_drvdata(pdev);
0511
0512 uart_remove_one_port(&digicolor_uart, port);
0513
0514 return 0;
0515 }
0516
0517 static const struct of_device_id digicolor_uart_dt_ids[] = {
0518 { .compatible = "cnxt,cx92755-usart", },
0519 { }
0520 };
0521 MODULE_DEVICE_TABLE(of, digicolor_uart_dt_ids);
0522
0523 static struct platform_driver digicolor_uart_platform = {
0524 .driver = {
0525 .name = "digicolor-usart",
0526 .of_match_table = of_match_ptr(digicolor_uart_dt_ids),
0527 },
0528 .probe = digicolor_uart_probe,
0529 .remove = digicolor_uart_remove,
0530 };
0531
0532 static int __init digicolor_uart_init(void)
0533 {
0534 int ret;
0535
0536 if (IS_ENABLED(CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE)) {
0537 digicolor_uart.cons = &digicolor_console;
0538 digicolor_console.data = &digicolor_uart;
0539 }
0540
0541 ret = uart_register_driver(&digicolor_uart);
0542 if (ret)
0543 return ret;
0544
0545 ret = platform_driver_register(&digicolor_uart_platform);
0546 if (ret)
0547 uart_unregister_driver(&digicolor_uart);
0548
0549 return ret;
0550 }
0551 module_init(digicolor_uart_init);
0552
0553 static void __exit digicolor_uart_exit(void)
0554 {
0555 platform_driver_unregister(&digicolor_uart_platform);
0556 uart_unregister_driver(&digicolor_uart);
0557 }
0558 module_exit(digicolor_uart_exit);
0559
0560 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
0561 MODULE_DESCRIPTION("Conexant Digicolor USART serial driver");
0562 MODULE_LICENSE("GPL");